JP2009047659A - Ranging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ranging device capable of performing accurate ranging, while suppressing the output saturation. <P>SOLUTION: A plurality of capacitors C1b, C2b respectively accumulate carriers distributed into each semiconductor domain FD1, FD2. Comparators COMP1, COMP2 and a AND circuit as determination means determine whether all the values (output voltages V<SB>OUT1</SB>, V<SB>OUT2</SB>), corresponding to the charge quantity of carriers accumulated in the capacitors C1b, C2b, exceed the threshold Vth. When the determination means indicates that all the values (output voltages V<SB>OUT1</SB>, V<SB>OUT2</SB>) corresponding to the charge quantity of the carriers accumulated in the capacitors C1b, C2b exceed the threshold Vth, switches SW1a, SW2a and charge extraction capacitors C1a, C2a as subtraction means subtract a fixed charge quantity from the charge quantity of the carriers accumulated in each capacitor C1b, C2b. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a distance measuring device.

  The distance measuring device described in Patent Document 1 irradiates an object with light emitted from a light source, measures reflected light from the object with a light detection element, and is based on a phase difference between the irradiated light and reflected light. To find the distance to the object. Here, in the distance measuring device described in Patent Document 1, the detection period is set according to the monitored light amount so that the light detection element is not saturated. The photodetection element detects reflected light in two periods, a long period and a short period, selects the amount of charge during a period when the photodetection element is not saturated, and discards the amount of charge during the other period.

  Similarly to Patent Document 1, the distance measuring device described in Patent Document 2 irradiates the object with light emitted from the light source, and measures reflected light from the object with a light detection element. The distance to the object is obtained based on the phase difference of the reflected light. Here, in the distance measuring device described in Patent Document 2, the exposure period of the light detection element is appropriately set according to the initially detected light amount level to suppress saturation of the light detection element.

  The distance measuring device described in Patent Document 3 realizes a distance measuring operation similar to the above using a microprocessor.

The distance measuring device described in Patent Document 4 resets a pixel when one of two detection signals having a phase difference is saturated.
JP 2006-84430 A US Patent Application Publication No. 2006/0176467 US Pat. No. 6,919,549 US Pat. No. 7,157,685

  However, in any document, the saturation of signal charge is suppressed, but the detection accuracy of distance information is not sufficient. In particular, Patent Document 4 resets the differential signal that is distance information, and there is a problem that the detection accuracy of the distance information is lowered instead of performing saturation suppression.

  The present invention has been made in view of such a problem, and an object of the present invention is to provide a distance measuring device capable of accurate distance measurement while suppressing output saturation.

  In order to solve the above-described problem, the distance measuring device according to the present invention irradiates a target with modulated light, and distributes carriers generated in response to the incidence of light reflected by the target in a time-sharing manner. In a distance measuring device that calculates the distance to an object based on the amount of charge of the distributed carriers, a plurality of capacitors that store the distributed carriers, and a value that corresponds to the amount of charge of the carriers stored in the capacitor If the determination means indicates that all of the values corresponding to the charge amount of carriers accumulated in the capacitors have exceeded the threshold, the determination means for determining whether or not all of the threshold values have been exceeded is stored in each capacitor. Subtracting means for subtracting a constant charge amount from the charge amount of the generated carrier.

  According to the distance measuring apparatus according to the present invention, the amount of electric charge accumulated in each capacitor depends on the distance to the object, and in this, light other than the reflected light from the object, that is, outside light is also included. include. Therefore, since the external light is a constant value, when all the values exceed the threshold value, the subtraction unit can suppress the saturation of the capacitor by subtracting the constant value from the accumulated charge amount. Here, even if a certain value is subtracted, the carrier generated by the reflected light from the object remains in the capacitor as a ranging effective charge, and after the subtraction, the ranging effective charge is further accumulated in the capacitor. be able to. Therefore, the S / N ratio of the charge accumulated in the capacitor is improved by charge integration, so that accurate distance measurement is possible.

  The threshold is preferably set to 50% or less of the value corresponding to the saturation charge amount of the capacitor. That is, in the present invention, the subtraction is not performed for the first time after the capacitor is saturated, but is performed at a value much lower than the saturation of the capacitor. As a result, the capacitor is not saturated even if the number of integrations of the ranging effective charge is increased. Therefore, by increasing the number of integrations, the S / N ratio is improved and more accurate ranging is possible.

  The distance measuring device according to the present invention further includes a charge amplifier including each capacitor between the input and output terminals. The input terminal and the output terminal of the charge amplifier are reset at different potentials, and carrier accumulation in the capacitor is performed after the reset. Is preferably performed.

  The input charge to the charge amplifier is converted into a voltage and output. In this case, the value corresponding to the charge stored in the capacitor is the output voltage of the charge amplifier. By changing the potential at the time of resetting the charge amplifier, the dynamic range of the amount of charge that can be accumulated in the capacitor can be widened.

  The subtracting means includes a charge extracting capacitor connected to the input side of each capacitor via a switch, and all the values corresponding to the amount of carrier charges accumulated in the capacitor exceed the threshold value. When the determination means indicates, the switch is connected.

  In this case, when the switch is connected, the charge amount accumulated in the original capacitor is moved to the extraction capacitor, so that the subtraction process of the charge amount accumulated in the original capacitor is performed.

  Further, the determination means includes a plurality of comparators to which values corresponding to the amount of carrier charges accumulated in the respective capacitors are input, a plurality of D latch circuits to which the outputs of the comparators are respectively input, and a D latch And an AND circuit to which the output of the circuit is input, and the output of the AND circuit is preferably input to the subtracting means.

  In this case, since there is a delay in the period from when the output of the comparator is switched to when it is input to the logical product circuit, the logical product circuit reliably recognizes that all values exceed the threshold value, and then performs the subtraction process. In case of unintentional output from the comparator, such as when resetting, the AND circuit does not recognize that all values exceed the threshold value. It is possible to suppress malfunctions based on.

  According to the distance measuring apparatus according to the present invention, accurate distance measurement can be performed while suppressing output saturation.

  Hereinafter, the distance measuring apparatus according to the embodiment will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

  FIG. 1 is an explanatory diagram showing the configuration of the distance measuring apparatus.

The distance measuring sensor 1 of this example is a back-illuminated distance measuring sensor, but may be a front-illuminated distance measuring sensor. The distance measuring device includes a distance measuring sensor 1, a light source 3 for emitting near-infrared light, a driving circuit 4 for giving a pulse drive signal S _P to the light source 3, included in each pixel of the back-illuminated distance measuring sensor 1 first and second gate electrodes (TX1, TX2: see FIG. 5), the pulse drive signal _S gate signal detection is synchronous with the _{P S} L, a control circuit 2 to give _{S R,} the first distance measuring sensor 1 And a calculation circuit (calculation) for calculating the distance to the object H such as a pedestrian from the signal d ′ (m, n) indicating the distance information read from the second semiconductor region (FD1, FD2: see FIG. 5). Means) 5 is provided. The distance in the horizontal direction D from the distance measuring sensor 1 to the object H is defined as d. In this example, an example in which light is modulated with a pulsed drive signal will be mainly described. However, the drive signal is not limited to a pulse, and may be a sine wave.

The control circuit 2 is input to the pulse drive signal S _P to the switch 4b of the driving circuit 4. A light projecting light source 3 comprising an LED or a laser diode is connected to a power source 4a via a switch 4b. Therefore, when the pulse drive signal S _P is input to the switch 4b, a drive current having the same waveform as the pulse drive signal S _P is supplied to the light source 3, the pulse light L _P as a probe light for distance measurement from the light source 3 Is output.

When the pulse light L _P is irradiated on the object H, the pulse light is reflected by the object H, the pulse light L _D, and enters the back-illuminated distance measuring sensor 1 outputs a pulse detection signal S _D . Pulse detection signal S _D represents the total amount of charges generated in the substrate in response to the incidence of pulsed light L _D, although the timing of the rising and falling is equal to the pulse light L _D, an amount corresponding pulses corresponding to the distance d phase is delayed with respect to the light L _P.

  The distance measuring sensor 1 is fixed on the wiring board 10, and a signal d ′ (m, n) having distance information is output from each pixel via the wiring on the wiring board 10.

The waveform of the pulse drive signal S _P, a square wave of period T, the high level "1", when the low level is "0", the voltage V (t) is given by the following equation.
・ Pulse drive signal S _P :
・ V (t) = 1 (provided that 0 <t <(T / 2))
・ V (t) = 0 (provided that (T / 2) <t <T)
・ V (t + T) = V (t)

The waveforms of the detection gate signals S _L and S _R are square waves with a period T, and the voltage V (t) is given by the following equation.
・ Detection gate signal S _L :
・ V (t) = 1 (provided that 0 <t <(T / 2))
・ V (t) = 0 (provided that (T / 2) <t <T)
・ V (t + T) = V (t)
· Detection gate signal _S R (= _{S L} inversion):
・ V (t) = 0 (provided that 0 <t <(T / 2))
V (t) = 1 (provided that (T / 2) <t <T)
・ V (t + T) = V (t)

The pulse signal _{S P, S L, S R} , S D , it is assumed that has all pulse period 2 × _{T P.} Detection gate signal S _L and the pulse detection signal S _D are both the amount of charge generated in the distance measuring sensor 1 when "1" Q1, the detection gate signal S _R and the pulse detection signal S _D are both "1" In this case, the amount of charge generated in the distance measuring sensor 1 is Q2.

The phase difference between one detection gate signal S _L and the pulse detection signal S _D in the distance measuring sensor 1, the other detection gate signal S _R and the pulse detection signal S _D is the overlap period when the "1", the back surface This is proportional to the amount of charge Q2 generated in the incident type distance measuring sensor 1. That is, the charge amount Q2 is the charge amount for the period logical product of the detection gate signal S _R and the pulse detection signal S _D is "1". The total charge quantity generated in one pixel is Q1 + Q2, when the pulse width of the half cycle of the drive signal _{S P} and _{T P, Δt = T P ×} Q2 / (Q1 + Q2) long enough, with respect to the drive signal _{S P} The pulse detection signal _SD is delayed.

The flight time Δt of one pulsed light is given by Δt = 2d / c, where d is the distance to the object and c is the speed of light. Therefore, two charges are used as a signal d ′ having distance information from a specific pixel. If the amount (Q1, Q2) are output, the arithmetic circuit 5, a charge amount Q1, Q2 input, based on the half cycle pulse width T _P that is known in advance, the distance to the object H d = Calculate (c × Δt) / 2 = c × _TP × Q2 / (2 × (Q1 + Q2)).

  As described above, if the charge amounts Q1 and Q2 are read out separately, the arithmetic circuit 5 can calculate the distance d. The above-described pulse is repeatedly emitted, and the integrated value can be output as the respective charge amounts Q1 and Q2.

  The ratio of the charge amounts Q1 and Q2 to the total charge amount corresponds to the above-described phase difference, that is, the distance to the object H, and the arithmetic circuit 5 determines the distance to the object H according to this phase difference. Is calculated. As described above, when the time difference corresponding to the phase difference is Δt, the distance d is preferably given by d = (c × Δt) / 2, but an appropriate correction operation may be added to this. . For example, when the actual distance and the calculated distance d are different, a coefficient β for correcting the latter is obtained in advance, and the product after shipping is obtained by multiplying the calculated distance d by the coefficient β. The calculation distance d may be used. In addition, when the outside air temperature is measured and the light speed c varies depending on the outside air temperature, the distance calculation can be performed after performing the calculation for correcting the light speed c. Further, the relationship between the signal input to the arithmetic circuit and the actual distance may be stored in advance in the memory, and the distance may be calculated by a lookup table method. The calculation method can also be changed depending on the sensor structure, and a conventionally known calculation method can be used for this.

  As described above, the arithmetic circuit 5 calculates the distance to the object H based on the ratio of the read charge Q1 (Q2) to the total charge amount (Q1 + Q2). Since the distance to the object H depends on such a ratio, the arithmetic circuit 5 can calculate the distance based on the ratio. In the above description, an example in which the two gate electrodes TX1 and TX2 (see FIG. 5) are driven with a phase difference of 180 degrees has been described.

  The charge amounts Q1 and Q2 are output from the semiconductor regions FD1 and FD2 positioned at both ends in the horizontal direction of the photogate electrode PG (FIG. 5). Charge amounts Q3 and Q4 can also be output from the semiconductor region located. In this case, the vertical structure is the same as the horizontal structure.

In this case, the four gate electrodes are driven with a phase difference of 90 degrees, and Q1, Q2, Q3, and Q4 are output from each semiconductor region. In this case, the distance d = Φ × c / 2 × 2πf is given. Incidentally, when the drive signal is sinusoidal is, f is the repetition frequency of the drive signal _{S P,} is given by the phase Φ = -arctan ((Q2-Q4 ) / (Q1-Q3)).

  FIG. 2 is a plan view of the distance measuring sensor 1.

  The distance measuring sensor 1 includes a semiconductor substrate 1A having an imaging region 1B composed of a plurality of pixels P (m, n) arranged in a two-dimensional manner. From each pixel P (m, n), two charge amounts (Q1, Q2) are output as the signal d '(m, n) having the above-described distance information. Since each pixel P (m, n) outputs a signal d ′ (m, n) corresponding to the distance to the object H as a minute distance measuring sensor, the reflected light from the object H is coupled to the imaging region 1B. If an image is obtained, a distance image of the object as a collection of distance information to each point on the object H can be obtained.

  FIG. 3 is a cross-sectional view taken along the line III-III of the distance measuring sensor shown in FIG.

The distance measuring sensor 1, the pulse light _{L D} is made incident from the light incident surface 1BK. A surface 1FT opposite to the light incident surface 1BK of the back-illuminated distance measuring sensor 1 is connected to the wiring substrate 10 via an adhesive region AD. The adhesion region AD is a region including an adhesion element such as a bump, and has an insulating adhesive or filler as necessary. The semiconductor substrate 1A constituting the back-illuminated distance measuring sensor 1 has a reinforcing frame portion F and a thin plate portion TF thinner than the frame portion F, and these are integrated. The thickness of the thin plate portion TF is 10 μm or more and 100 μm or less. The thickness of the frame portion F in this example is 200 μm or more and 600 μm or less.

  FIG. 4 is a cross-sectional view of a distance measuring sensor according to a modification.

  This distance measuring sensor differs from that shown in FIG. 3 only in the shape of the semiconductor substrate 1A, and the other configurations are the same. The semiconductor substrate 1A further includes reinforcing portions AF formed in a stripe shape or a lattice shape, and a thin plate portion TF is formed between the reinforcing portions AF, and these are integrated. The thickness of the reinforcing portion AF in this example is the same as the thickness of the frame portion AF, and is 200 μm or more and 600 μm or less. Each pixel described above is formed in the thin plate portion TF. The thin plate portion TF is formed by wet etching using an alkaline etching solution such as KOH. The roughness of the exposed surface formed by etching is 1 μm or less.

  FIG. 5 is an enlarged view of the region V of the distance measuring sensor shown in FIG. 3 or FIG.

The back-illuminated distance measuring sensor 1 is provided with a P-type semiconductor substrate 1A having a light incident surface on which an antireflection film 1D is provided and a surface opposite to the light incident surface, and an insulating layer 1E on the surface. And the first and second gate electrodes TX1 and TX2 provided adjacent to the photogate electrode PG via the insulating layer 1E on the surface. The material of the antireflection film 1D is SiO ₂ or SiN (silicon nitride).

  In a region in the semiconductor substrate (epitaxial layer) 1A outside the gate electrode TX1, high-concentration N-type impurities are added from the surface side of the substrate, and a floating diffusion region composed of the N-type semiconductor region FD1 is formed. Has been. In the region inside the semiconductor substrate 1A outside the gate electrode TX2, a high-concentration N-type impurity is added from the substrate surface side, and a floating diffusion region composed of the N-type semiconductor region FD2 is formed. The semiconductor regions FD1 and FD2 constitute drains of field effect transistors including the gate electrodes TX1 and TX2, respectively. Note that a slight positive DC potential is applied to the photogate electrode PG.

When reflected light from the object is incident on the semiconductor substrate 1A via the antireflection film 1D, carriers are generated in a region immediately below the photogate electrode PG in the semiconductor substrate 1A. Alternately to the gate electrode TX1, TX2 provide a high potential (the detection gate signal _S L, is applied to _{S R),} the carriers generated in the substrate, alternately flows into the semiconductor regions FD1, the FD2. At this time, a fringing electric field is formed in the semiconductor substrate 1A. By increasing the thickness of the insulating layer 1E, a fringing electric field can be formed in the semiconductor substrate. A preferable thickness of the insulating layer 1E for forming a fringing electric field is 50 to 5000 nm.

  The electrodes 18a and 21a are in contact with the semiconductor regions FD1 and FD2, and electrode wirings 18g and 18g formed on the surface of the semiconductor substrate 10A constituting the wiring substrate through internal wirings embedded in the adhesive layer AD. It is electrically connected to 21g. The gate electrodes TX1, PG, TX2 are electrically connected to the electrode wirings 12g, 13g, 14g formed on the surface of the semiconductor substrate 10A via internal wirings embedded in the adhesive layer AD, respectively. Yes. In order to connect the potential of the semiconductor substrate 1A to a reference potential such as a ground potential, a back gate electrode is provided at an appropriate position in the semiconductor substrate 1A, but a through electrode penetrating in the thickness direction in the substrate is provided. This may be connected to the ground potential.

FIG. 6 is a circuit diagram showing a circuit in the wiring board 10. Using the output from the control circuit 2, the actual configuration of the drive circuit 4 to which the light source 3 and the power source 4a are connected by the switch 4b to which the pulse drive signal _SP is input is shown at the same time. In the figure, the photogate electrode PG and the gate electrodes TX1 and TX2 are shown as the gate electrodes of the respective field effect transistors. For convenience of explanation, the transistors are denoted by the same reference numerals as the gate electrodes. .

Carriers generated immediately below the photogate electrode PG due to the incidence of light flow into the node P1 which is the input terminal of the charge amplifier CA1 through the electrode wiring 18g when a high potential is applied to the gate electrode TX1. . Assuming that the charge amplifier CA1 is reset, the carriers flowing into the node P1 are accumulated in the capacitor C1b connected between the input and output terminals of the charge amplifier CA1 by disconnecting the switches SW1r and SW1a. . Since the gate electrode TX1 is repeatedly given a high potential, the amount of carriers stored in the capacitor C1b gradually increases, and the output voltage of the charge amplifier CA1 rises. When the potential of the node P2 that is the output terminal of the charge amplifier CA1 exceeds the threshold value Vth, the output V _COMP1 of the comparator _COMP1 becomes high level, and the output of the comparator COMP1 is slightly passed through the D latch FF1. After being given a delay, it is input to an AND circuit (AND circuit) AND.

Similarly, the carriers generated immediately below the photogate electrode PG due to the incidence of light, when a high potential is applied to the gate electrode TX2, are connected to the node that is the input terminal of the charge amplifier CA2 via the electrode wiring 21g. It flows into P3. Assuming that the charge amplifier CA2 is reset, the carriers flowing into the node P3 are accumulated in the capacitor C2b connected between the input and output terminals of the charge amplifier CA2 by disconnecting the switches SW2r and SW2a. . Since the gate electrode TX2 is repeatedly given a high potential, the amount of charge of carriers accumulated in the capacitor C2b gradually increases, and the output voltage of the charge amplifier CA2 rises. When the potential of the node P4, which is the output terminal of the charge amplifier CA2, exceeds the threshold value Vth, the output VCOMP2 of the comparator _COMP2 becomes high level, and the output of the comparator COMP2 is slightly passed through the D latch FF2. After being given a delay, it is input to an AND circuit (AND circuit) AND.

The AND circuit AND sets the level of the node P5, which is an output terminal, to a high level when both inputs are at a high level. When the output of the AND circuit AND is high, the switches SW1a and SW2a are connected. The switches SW1a and SW2a are connected between the nodes P1 and P3 and the charge extracting capacitors C1a and C2a, respectively. Short-circuit switches SW1c and SW2c are connected between both ends of the charge extracting capacitors C1a and C2a, respectively, and one end of each of the capacitors C1a and C2a is connected to the potential _VA . When the switches SW1a and SW2a are connected while the short-circuit switches SW1c and SW2c are disconnected, carriers (charges) accumulated in the capacitors C1b and C2b flow into the capacitors C1a and C2a, and are constant from the capacitors C1b and C2b. The amount of charge is subtracted.

As a result, the output voltages of the charge amplifiers CA1 and CA2 are greatly reduced by reducing the direct current component corresponding to the external light. Accordingly, the outputs of the comparators V _COMP1 and V _COMP2 become low level, and after a slight delay after being switched to low level by the D latches FF1 and FF2, the output of the AND circuit AND is switched to low level, and the switches SW1a, SW1a, SW2a is disconnected.

  After the carriers are extracted, in a state where the switches SW1a and SW2a are disconnected, the short-circuit switches SW1c and SW2c provided in the capacitors C1a and C2a are connected to discharge the charges accumulated in the capacitors C1a and C2a.

  As a result, the charge corresponding to the signal remains in the capacitors C1b and C2b. The above operation is repeated until the residual charge amount reaches a certain value, and integration is performed.

  As described above, the charge extracting capacitors C1a and C2a constituting the subtracting means are connected to the input sides of the respective capacitors C1b and C2b via the switches SW1a and SW2a, and the carriers accumulated in the capacitors C1b and C2b. When the determination means indicates that all the values corresponding to the amount of charges exceed the threshold value Vth, the switches SW1a and SW2a are connected. In this case, when the switches SW1a and SW2a are connected, the amount of charge accumulated in the original capacitors C1b and C2b moves to the extraction capacitors C1a and C2a, so that the amount of charge accumulated in the original capacitors C1b and C2b is subtracted. Processing has been performed.

After that, reset. At reset, the switches SW1r and SW2r are connected, and the nodes P2 and P4 are connected to the reference potential Vref. As a result, the potential on the output side of the capacitors C1b and C2b becomes the reference potential Vref. On the other hand, the capacitor C1b, input side potential of C2b is the virtual ground of the operational amplifier A1, A2, are fixed to the potential V _B, forcibly short-circuited a switch between the two input terminals of the operational amplifier, It may be fixed to the potential V _B.

  That is, the nodes P1 and P3 which are input terminals of the charge amplifiers CA1 and CA2 including the capacitors C1b and C2b between the input and output terminals and the nodes P2 and P4 which are output terminals are reset at different potentials. Carrier accumulation in C2b is performed.

Input charges to the charge amplifiers CA1 and CA2 are converted into voltages and output. The values corresponding to the charges accumulated in the capacitors C1b and C2b are the output voltages V _OUT1 and V _OUT2 of the charge amplifiers C1b and C2b. By changing the potentials of the input terminal and the output terminal when the charge amplifiers CA1 and CA2 are reset, the dynamic range of the amount of charge that can be accumulated in the capacitors C1b and C2b can be widened.

Note that the potentials V _A , V _B , and Vref are set to achieve the above-described function. Further, V _OUT1 and V _OUT2 correspond to the charge amounts Q1 and Q2, respectively, and the distance can be calculated therefrom according to the above formula. Furthermore, another light detection element for measuring the external light intensity may be provided, and the threshold value Vth may be set according to the external light intensity detected by the light detection element.

  As described above, the distance measuring apparatus according to the embodiment irradiates the object with the modulated light, and distributes and distributes the carriers generated in response to the incident light reflected by the object in a time division manner. A distance measuring device that obtains the distance to the object based on the charge amount of the carrier is the object.

Here, the plurality of capacitors C1b and C2b store the carriers distributed to the semiconductor regions FD1 and FD2, respectively. Further, the comparators COMP1 and COMP2 and the AND circuit AND as the determination means all have values (output voltages V _OUT1 and V _OUT2 ) corresponding to the carrier charge amounts accumulated in the capacitors C1b and C2b exceeding the threshold value Vth. It is determined whether or not. When the determination means indicates that the values (output voltages V _OUT1 , V _OUT2 ) corresponding to the charge amounts of the carriers accumulated in the capacitors C1b and C2b all exceed the threshold value Vth, the subtraction means The switches SW1a and SW2a and the charge extracting capacitors C1a and C2a subtract a certain amount of charge from the amount of carriers stored in the capacitors C1b and C2b.

  The amount of charge accumulated in each of the capacitors C1b and C2b depends on the distance d to the object, but this includes light other than the reflected light from the object, that is, outside light. Since the external light is a constant value, when all the values exceed the threshold value Vth, the subtracting unit subtracts the constant value from the accumulated charge amount to suppress the saturation of the capacitors C1b and C2b. Here, even if a constant value is subtracted, the carriers generated by the reflected light from the object remain in the capacitors C1b and C2b as the ranging effective charges, and the distances are measured in the capacitors C1b and C2b after the subtraction. Effective charges can be further accumulated. Accordingly, since the S / N ratio of the charges accumulated in the capacitors C1b and C2b is improved by the charge integration, accurate distance measurement is possible.

In addition, as described above, the determination unit includes a plurality of comparators COMP1 and COMP2 to which values (output voltages V _OUT1 and V _OUT2 ) corresponding to the charge amounts of carriers accumulated in the capacitors C1b and C2b are respectively input. A plurality of D latch circuits FF1 and FF2 to which the outputs of the comparators COMP1 and COMP2 are respectively input, and an AND circuit AND to which the outputs of the D latch circuits FF1 and FF2 are input. Is input to the switches SW1a and SW2a of the subtracting means.

  In this case, since there is a delay in the period from when the outputs of the comparators COMP1 and COMP2 are switched to when they are input to the AND circuit AND, the AND circuit AND reliably recognizes that all values exceed the threshold value. From the above, the subtracting process can be performed, and when an unintentional output is instantaneously output from the comparators COMP1 and COMP2 at the time of resetting or the like, the AND circuit AND outputs all the values. Since it is not recognized that the threshold value is exceeded, malfunctions based on misrecognition can be suppressed.

FIG. 7 is a timing chart for explaining the operation of the above-described circuit. Note that the comparator outputs V _COMP1 and V _COMP2 indicate outputs at the subsequent stage of the D latch circuit.

Output voltages V _OUT1 and V _OUT2 of charge amplifiers CA1 and CA2 are reset in advance to reference potential Vref. In this state, as time elapses, the output voltages V _OUT1 and V _OUT2 rise, and when one output voltage V _OUT1 exceeds the threshold value Vth (time t ₁ ), the comparator V _COMP1 is slightly delayed _. Is output to the AND circuit AND as a high level (time t ₂ ), and when the other output voltage V _OUT2 exceeds the threshold value Vth (time t ₃ ), the comparator V is slightly delayed. The output from _COMP2 is input to the AND circuit AND as a high level (time t ₄ ), the output of the AND circuit AND becomes a high level, and the above-described charge extraction is performed. As a result, the output voltage V _OUT1 decreases by ΔV, and the voltage A corresponding to the ranging effective charge that becomes the signal component remains. Similarly, the output voltage V _OUT2 also decreases by ΔV, and the ranging effective charge that becomes the signal component A voltage B corresponding to remains. Thereafter, both comparator outputs V _COMP1 and V _COMP2 are switched to a low level, and the output voltages V _OUT1 and V _OUT2 begin to rise again. This operation continues until a reset is performed.

Here, the threshold value Vth is a value corresponding to the saturation charge amount of the capacitors C1b and C2b (output voltages V _OUT1 and V _OUT2 when the capacitors C1b and C2b and the charge amplifiers CA1 and CA2 are saturated) = half of Vsat (50 %) Or less is preferably set. That is, the subtraction is not performed for the first time after the capacitors C1b and C2b are saturated, but is performed at a value much lower than the saturation of the capacitors. As a result, the capacitors C1b and C2b do not saturate even when the number of effective ranging charge accumulations is increased. Therefore, increasing the number of integrations improves the S / N ratio and enables more accurate distance measurement. .
In the above-described apparatus, when the detected signal is small, the subtraction process is not performed, so that the measurement can be performed as it is. Further, a photodiode to which a reverse bias is applied can be used instead of the above-described transistor PG.

It is explanatory drawing which shows the structure of a distance measuring device. 2 is a plan view of the distance measuring sensor 1. FIG. FIG. 3 is a sectional view of the distance measuring sensor shown in FIG. 2 along arrows III-III. It is sectional drawing of the distance measuring sensor which concerns on a modification. FIG. 5 is an enlarged view of a region V of the distance measuring sensor shown in FIG. 3 or FIG. 4. 2 is a circuit diagram showing a circuit in the wiring board 10. FIG. It is a timing chart for explaining circuit operation.

Explanation of symbols

PG ... Photo gate electrode, TX1, TX2 ... Gate electrode, COMP1, COMP2 ... Comparator, AND ... AND circuit, C1b, C2b ... Capacitor, C1a, C2a ... Charge extraction Capacitor.

Claims (5)

The target is irradiated with the modulated light, the carriers generated in response to the incident light reflected by the target are distributed in a time-sharing manner, and the distance to the target is determined based on the charge amount of the distributed carriers. In the distance measuring device that calculates
A plurality of capacitors each storing the sorted carriers;
A determination means for determining whether or not all values corresponding to the charge amount of carriers accumulated in the capacitor have exceeded a threshold;
When the determination means indicates that all the values corresponding to the charge amount of the carriers accumulated in the capacitors have exceeded the threshold value, a constant charge is obtained from the charge amount of the carriers accumulated in the respective capacitors. Subtracting means for reducing the amount;
Comprising
A distance measuring device characterized by that. The threshold value is set to 50% or less of a value corresponding to the saturation charge amount of the capacitor.
The distance measuring apparatus according to claim 1. A charge amplifier including each of the capacitors between the input and output terminals;
The input terminal and the output terminal of the charge amplifier are reset at different potentials, and after the reset, carrier accumulation in the capacitor is performed.
The distance measuring apparatus according to claim 1 or 2, wherein The subtracting means is
A charge extracting capacitor connected to the input side of each capacitor via a switch;
When the determination means indicates that all the values corresponding to the amount of charge of carriers accumulated in the capacitor have exceeded the threshold, the switch is connected,
The distance measuring apparatus according to any one of claims 1 to 3, wherein A plurality of comparators each receiving a value corresponding to a charge amount of carriers accumulated in each capacitor;
A plurality of D latch circuits each receiving an output of the comparator;
An AND circuit to which the output of the D latch circuit is input;
The output of the AND circuit is input to the subtracting means.
The distance measuring device according to any one of claims 1 to 4, wherein

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