JP2009047661A - Ranging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ranging device capable of measuring the distance to an object, accurately and simply in a short detection time. <P>SOLUTION: When level of a transmission voltage is lowered in proportion to the intensity of external light during transmission, a barrier is set high, and more carriers of the charge quantity remain inside first and second potential wells ϕ<SB>CD1</SB>, ϕ<SB>CD2</SB>. A unit period is set, independently of the intensity of the external light. Many carriers remain, in proportion to the intensity of the external light, and are finally removed from read-out carriers. The number of times of transfer per unit period is increased if it is proportional to the intensity of the external light, and transfer is performed prior to the saturation of the carriers accumulated in the first and second potential wells ϕ<SB>CD1</SB>, ϕ<SB>CD2</SB>; and if the external light is weak, the number of times of transfer per unit period is decreased, extra transfers are avoided, the accumulated charge quantity per unit time can be increased, and detection accuracy can be improved during short detection time. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a distance measuring device.

  Conventional distance measuring devices are described in Patent Literature 1, Patent Literature 2, and Patent Literature 3.

  The distance measuring device described in Patent Document 1 irradiates an object with light emitted from a light source, measures reflected light from the object with a light detection element, and is based on a phase difference between the irradiated light and reflected light. To find the distance to the object. Here, in the distance measuring device described in Patent Document 1, the detection period is set according to the monitored light amount so that the light detection element is not saturated. The photodetection element detects reflected light in two periods, a long period and a short period, selects the amount of charge during a period when the photodetection element is not saturated, and discards the amount of charge during the other period.

  Similarly to Patent Document 1, the distance measuring device described in Patent Document 2 irradiates the object with light emitted from the light source, and measures reflected light from the object with a light detection element. The distance to the object is obtained based on the phase difference of the reflected light. Here, in the distance measuring device described in Patent Document 2, the exposure period of the light detection element is appropriately set according to the initially detected light amount level to suppress saturation of the light detection element.

The distance measuring device described in Patent Document 3 realizes a distance measuring operation similar to the above using a microprocessor.
JP 2006-84430 A US Patent Application Publication No. 2006/0176467 US Pat. No. 6,919,549

  However, since the distance measuring device described in Patent Document 1 discards charges that do not contribute to detection, the detection time for obtaining the necessary charge amount becomes longer, and the distance detection accuracy deteriorates if the detection time is shortened. There is a problem of doing. In the distance measuring device described in Patent Document 2, since the exposure period of the light detection element is different, it is necessary to control the time for reading the charge from the light detection element for each light amount level, which is complicated in the subsequent circuit. There is a problem that signal processing is required. The problem with the apparatus described in Patent Document 3 is the same.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a distance measuring device that can accurately and easily measure the distance to an object in a short detection time.

  In order to solve the above-described problems, a distance measuring device according to the present invention alternately applies a voltage to a light source that emits modulated light toward an object and first and second gate electrodes provided on a semiconductor substrate. Thus, the first and second potential wells that alternately accumulate carriers generated according to the incident light, the third and fourth potential wells adjacent to the first and second potential wells, respectively, and the transfer voltage are A third gate electrode that sets a barrier height for carriers between the first potential well and the third potential well to a predetermined value by being applied; and a transfer voltage that is applied to the second potential well; And a fourth gate electrode for setting a barrier height against carriers between the fourth potential well to a predetermined value, and the third and fourth potential wells after the end of the unit period. A distance measuring device that reads out each of the accumulated charges, a detection unit that detects external light, a transfer voltage application unit that applies a transfer voltage, and an intensity of external light detected by the detection unit. And a control means for controlling the transfer voltage application means so as to decrease the magnitude of the transfer voltage and increase the number of times of transfer voltage application per unit period.

  When the modulated light emitted from the light source is reflected by the object, the reflected light enters the semiconductor substrate. Depending on the phase difference between the reflected light and the modulated light, the amount of charge of carriers accumulated in the first and second potential wells differs. Since this phase difference depends on the distance to the object, the distance to the object can be obtained from the ratio of the accumulated charge amount.

  The carriers accumulated in the first and second potential wells flow into the third and fourth potential wells when the barrier height between the third and fourth potential wells decreases. This barrier height depends on the magnitude of the transfer voltage applied to the third and fourth gate electrodes. When a large transfer voltage is applied, the barrier height becomes small, and many carriers flow from the first and second potential wells into the third and fourth potential wells.

  If the barrier height is set so that carriers having a charge amount equal to the charge amount of carriers generated in response to the incidence of external light remain in the first and second potential wells, the external light component is transferred during transfer. The carriers from which the ions are removed flow into the third and fourth potential wells from the first and second potential wells. By alternately applying a voltage to the first and second gate electrodes, carriers are accumulated in the first and second potential wells. Among the carriers accumulated in these potential wells, carriers having a charge amount from which the external light component has been removed flow into the third and fourth potential wells and are read out.

  At the time of transfer, the higher the intensity of the external light detected by the detection means, the lower the transfer voltage, the higher the barrier height, and more charge carriers are transferred to the first and second potential wells. Remains in. That is, the higher the intensity of external light, the more carriers remain and are removed from the carrier that is finally read.

  Here, the number of times of application of the transfer voltage per unit period increases as the intensity of external light increases. That is, if the external light is strong, the number of transfers per unit period increases, and transfer is performed before the carriers accumulated in the first and second potential wells are saturated. If the external light is weak, the number of transfers per unit period is reduced, and unnecessary transfer is not performed, thereby increasing the amount of accumulated charges per unit time and improving the detection accuracy in a short detection time.

  Since this unit period does not depend on the intensity of external light, it is only necessary to periodically read out the carriers accumulated in the third and fourth potential wells after the end of the unit period, and reading requires special control. do not do. That is, according to the distance measuring apparatus of the present invention, distance detection can be performed with a simple configuration.

  In the distance measuring apparatus according to the present invention, the first, second, third and fourth gate electrodes are preferably provided on the side opposite to the light incident surface. This distance measuring device constitutes a back-illuminated type distance measuring sensor, and carriers generated in a region opposite to the light incident surface of the semiconductor substrate can be efficiently collected. Distance measurement can be performed.

  In this way, the calculation means calculates the distance to the object based on the ratio of the read charges to the total charge amount. Since the distance to the object depends on such a ratio, the calculation means can calculate the distance based on the ratio.

  According to the distance measuring apparatus of the present invention, it is possible to accurately and easily measure the distance to an object in a short detection time.

  Hereinafter, the distance measuring apparatus according to the embodiment will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

  FIG. 1 is an explanatory diagram showing the configuration of the distance measuring apparatus.

The distance measuring sensor 1 of this example is a back-illuminated distance measuring sensor, but can also be a front-illuminated distance measuring sensor as will be described later. The distance measuring device includes a distance measuring sensor 1, a light source 3 for emitting near-infrared light, a driving circuit 4 for giving a pulse drive signal S _P to the light source 3, included in each pixel of the back-illuminated distance measuring sensor 1 first and second gate electrodes (TX1, TX2: see FIG. 5), the pulse drive signal _S gate signal detection is synchronous with the _{P S} L, a control circuit 2 to give _{S R,} the first distance measuring sensor 1 And a calculation circuit (calculation) for calculating the distance to the object H such as a pedestrian from the signal d ′ (m, n) indicating the distance information read from the second semiconductor region (FD1, FD2: see FIG. 5). Means) 5 is provided. The distance in the horizontal direction D from the distance measuring sensor 1 to the object H is defined as d.

The control circuit 2 is input to the pulse drive signal S _P to the switch 4b of the driving circuit 4. A light projecting light source 3 comprising an LED or a laser diode is connected to a power source 4a via a switch 4b. Therefore, when the pulse drive signal S _P is input to the switch 4b, a drive current having the same waveform as the pulse drive signal S _P is supplied to the light source 3, the pulse light L _P as a probe light for distance measurement from the light source 3 Is output.

When the pulse light L _P is irradiated on the object H, the pulse light is reflected by the object H, the pulse light L _D, and enters the back-illuminated distance measuring sensor 1 outputs a pulse detection signal S _D . Pulse detection signal S _D represents the total amount of charges generated in the substrate in response to the incidence of pulsed light L _D, although the timing of the rising and falling is equal to the pulse light L _D, an amount corresponding pulses corresponding to the distance d phase is delayed with respect to the light L _P.

  The distance measuring sensor 1 is fixed on the wiring board 10, and a signal d ′ (m, n) having distance information is output from each pixel via the wiring on the wiring board 10.

The waveform of the pulse drive signal S _P, a square wave of period T, the high level "1", when the low level is "0", the voltage V (t) is given by the following equation.
・ Pulse drive signal S _P :
・ V (t) = 1 (provided that 0 <t <(T / 2))
・ V (t) = 0 (provided that (T / 2) <t <T)
・ V (t + T) = V (t)

The waveforms of the detection gate signals S _L and S _R are square waves with a period T, and the voltage V (t) is given by the following equation.
・ Detection gate signal S _L :
・ V (t) = 1 (provided that 0 <t <(T / 2))
・ V (t) = 0 (provided that (T / 2) <t <T)
・ V (t + T) = V (t)
· Detection gate signal _S R (= _{S L} inversion):
・ V (t) = 0 (provided that 0 <t <(T / 2))
V (t) = 1 (provided that (T / 2) <t <T)
・ V (t + T) = V (t)

The pulse signal _{S P, S L, S R} , S D , it is assumed that has all pulse period 2 × _{T P.} Detection gate signal S _L and the pulse detection signal S _D are both the amount of charge generated in the distance measuring sensor 1 when "1" Q1, the detection gate signal S _R and the pulse detection signal S _D are both "1" In this case, the amount of charge generated in the distance measuring sensor 1 is Q2.

The phase difference between one detection gate signal S _L and the pulse detection signal S _D in the distance measuring sensor 1, the other detection gate signal S _R and the pulse detection signal S _D is the overlap period when the "1", the back surface This is proportional to the amount of charge Q2 generated in the incident type distance measuring sensor 1. That is, the charge amount Q2 is the charge amount for the period logical product of the detection gate signal S _R and the pulse detection signal S _D is "1". The total charge quantity generated in one pixel is Q1 + Q2, when the pulse width of the half cycle of the drive signal _{S P} and _{T P, Δt = T P ×} Q2 / (Q1 + Q2) long enough, with respect to the drive signal _{S P} The pulse detection signal _SD is delayed.

The flight time Δt of one pulsed light is given by Δt = 2d / c, where d is the distance to the object and c is the speed of light. Therefore, two charges are used as a signal d ′ having distance information from a specific pixel. If the amount (Q1, Q2) are output, the arithmetic circuit 5, a charge amount Q1, Q2 input, based on the half cycle pulse width T _P that is known in advance, the distance to the object H d = Calculate (c × Δt) / 2 = c × _TP × Q2 / (2 × (Q1 + Q2)).

  As described above, if the charge amounts Q1 and Q2 are read out separately, the arithmetic circuit 5 can calculate the distance d. The above-described pulse is repeatedly emitted, and the integrated value can be output as the respective charge amounts Q1 and Q2.

  The ratio of the charge amounts Q1 and Q2 to the total charge amount corresponds to the above-described phase difference, that is, the distance to the object H, and the arithmetic circuit 5 determines the distance to the object H according to this phase difference. Is calculated. As described above, when the time difference corresponding to the phase difference is Δt, the distance d is preferably given by d = (c × Δt) / 2, but an appropriate correction operation may be added to this. . For example, when the actual distance and the calculated distance d are different, a coefficient β for correcting the latter is obtained in advance, and the product after shipping is obtained by multiplying the calculated distance d by the coefficient β. The calculation distance d may be used. In addition, when the outside air temperature is measured and the light speed c varies depending on the outside air temperature, the distance calculation can be performed after performing the calculation for correcting the light speed c. Further, the relationship between the signal input to the arithmetic circuit and the actual distance may be stored in advance in the memory, and the distance may be calculated by a lookup table method. The calculation method can also be changed depending on the sensor structure, and a conventionally known calculation method can be used for this.

  As described above, the arithmetic circuit 5 calculates the distance to the object H based on the ratio of the read charge Q1 (Q2) to the total charge amount (Q1 + Q2). Since the distance to the object H depends on such a ratio, the arithmetic circuit 5 can calculate the distance based on the ratio.

  FIG. 2 is a plan view of the distance measuring sensor 1.

  The distance measuring sensor 1 includes a semiconductor substrate 1A having an imaging region 1B composed of a plurality of pixels P (m, n) arranged in a two-dimensional manner. From each pixel P (m, n), two charge amounts (Q1, Q2) are output as the signal d '(m, n) having the above-described distance information. Since each pixel P (m, n) outputs a signal d ′ (m, n) corresponding to the distance to the object H as a minute distance measuring sensor, the reflected light from the object H is coupled to the imaging region 1B. If an image is obtained, a distance image of the object as a collection of distance information to each point on the object H can be obtained.

  FIG. 3 is a cross-sectional view taken along the line III-III of the distance measuring sensor shown in FIG.

The distance measuring sensor 1, the pulse light _{L D} is made incident from the light incident surface 1BK. A surface 1FT opposite to the light incident surface 1BK of the back-illuminated distance measuring sensor 1 is connected to the wiring substrate 10 via an adhesive region AD. The adhesion region AD is a region including an adhesion element such as a bump, and has an insulating adhesive or filler as necessary. The semiconductor substrate 1A constituting the back-illuminated distance measuring sensor 1 has a reinforcing frame portion F and a thin plate portion TF thinner than the frame portion F, and these are integrated. The thickness of the thin plate portion TF is 10 μm or more and 100 μm or less. The thickness of the frame portion F in this example is 200 μm or more and 600 μm or less.

  FIG. 4 is a cross-sectional view of a distance measuring sensor according to a modification.

  This distance measuring sensor differs from that shown in FIG. 3 only in the shape of the semiconductor substrate 1A, and the other configurations are the same. The semiconductor substrate 1A further includes reinforcing portions AF formed in a stripe shape or a lattice shape, and a thin plate portion TF is formed between the reinforcing portions AF, and these are integrated. The thickness of the reinforcing portion AF in this example is the same as the thickness of the frame portion AF, and is 200 μm or more and 600 μm or less. Each pixel described above is formed in the thin plate portion TF. The thin plate portion TF is formed by wet etching using an alkaline etching solution such as KOH. The roughness of the exposed surface formed by etching is 1 μm or less.

  FIG. 5 is an enlarged view of the region V of the distance measuring sensor shown in FIG. 3 or FIG.

  The back-illuminated distance measuring sensor 1 includes a semiconductor substrate 1A, 1A ′ having a light incident surface 1BK and a surface 1FT opposite to the light incident surface 1BK, and a photogate provided on the surface 1FT via an insulating layer 1E. An electrode PG and first and second gate electrodes TX1, TX2 provided adjacent to the photogate electrode PG via the insulating layer 1E on the surface 1FT are provided.

  Further, the back-illuminated distance measuring sensor 1 includes third and fourth gate electrodes TX1 ′, TX2 provided adjacent to the outside of the first and second gate electrodes TX1, TX2 via the insulating layer 1E on the surface 1FT. Is equipped with.

  A region in the epitaxial layer 1A ′ between the first gate electrode TX1 and the third gate electrode TX1 ′ is doped with high-concentration N-type impurities from the surface 1FT side, so that the temporary carrier accumulation region CD1 is formed. Is formed. Also, a region in the epitaxial layer 1A ′ between the second gate electrode TX2 and the fourth gate electrode TX2 ′ is doped with a high concentration N-type impurity from the surface 1FT side, so that a temporary carrier accumulation region CD2 is formed.

  In the region in the epitaxial layer 1A ′ outside the third gate electrode TX1 ′, a high-concentration N-type impurity is added from the surface 1FT side, and a floating diffusion region composed of the N-type semiconductor region FD1 is formed. ing. In the region in the epitaxial layer 1A ′ outside the fourth gate electrode TX2 ′, a high-concentration N-type impurity is added from the surface 1FT side, and a floating diffusion region composed of the N-type semiconductor region FD2 is formed. ing. The semiconductor regions FD1 and FD2 constitute drains of field effect transistors including the third and fourth gate electrodes TX1 'and TX2', respectively, and the accumulation regions CD1 and CD2 constitute sources.

  Carriers (electrons e) generated in the semiconductor region immediately below the photogate electrode PG flow into regions immediately below the first and second gate electrodes TX1 and TX2, and are temporarily stored in the storage regions CD1 and CD2, respectively. . Thereafter, a transfer voltage is applied to the gate electrodes TX1 'and TX2' of the field effect transistor to transfer the field effect transistors into the semiconductor regions FD1 and FD2. Carriers accumulated in the semiconductor regions FD1 and FD2 are read as charge amounts Q1 and Q2, respectively.

In this example, the semiconductor substrates 1A and 1A ′ are made of Si, and the insulating layer 1E is made of SiO ₂ . By increasing the thickness of the insulating layer 1E, a fringing electric field can be formed in the semiconductor substrate. A preferable thickness of the insulating layer 1E for forming a fringing electric field is 50 to 5000 nm.

  The semiconductor substrate of this example includes a substrate body 1A having a light incident surface and an epitaxial layer 1A 'on the gate electrode side, but the epitaxial layer may be omitted.

  The semiconductor substrates 1A and 1A 'are made of a low impurity concentration P-type semiconductor substrate. The accumulation regions CD1 and CD2 and the semiconductor regions FD1 and FD2 are each made of an N-type semiconductor having a high impurity concentration, and are formed in the epitaxial layer 1A '.

The portions on the photogate electrode PG side of the storage regions CD1 and CD2 are close to or in contact with regions immediately below the gate electrodes TX1 and TX2 in the epitaxial layer 1A ′ of the semiconductor substrate. The portions of the first and second semiconductor regions FD1, FD2 on the photogate electrode PG side are close to or in contact with regions immediately below the gate electrodes TX1 ′, TX2 ′ in the epitaxial layer 1A ′ of the semiconductor substrate. An antireflection film 1D is provided on the light incident surface 1BK side of the semiconductor substrates 1A and 1A ′. The surface roughness of the exposed surface of the semiconductor substrate 1A, that is, the difference between the maximum height and the minimum height of the surface irregularities is 1 μm or less. The material of the antireflection film 1D is SiO ₂ or SiN (silicon nitride).

  Note that a region immediately below the region between the gate electrodes TX1 and TX2 is a P-type having the same conductivity type as the semiconductor substrates 1A and 1A ′, and has an impurity concentration lower than that of the semiconductor substrates 1A and 1A ′. It may have a high impurity concentration. Such a region can be formed using an epitaxial growth method, an impurity diffusion method, or an ion implantation method.

  The wiring board 10 includes a semiconductor substrate 10A made of Si, charge discharge wirings 11h and 15h formed on the semiconductor substrate 10A, and signal readout wirings 18h and 21h. The wirings 11h and 15h are respectively stored in the storage region CD1. , CD2 and wirings 18h and 21h are electrically connected to semiconductor regions FD1 and FD2, respectively.

  Between the regions CD1, CD2, FD1, FD2 and the wirings 11h, 15h, 18h, 21h, contact electrodes 11a, 15a, 18a, 21a, pad electrodes 11b, 15b, 18b, 21b, bumps 11c, 15c, respectively. 18c, 21c, pad electrodes 11d, 15d, 18d, 21d, contact electrodes 11e, 15e, 18e, 21e, intermediate electrodes 11f, 15f, 18f, 21f, and contact electrodes 11g, 15g, 18g, 21g.

  A first gate line 12g, a second gate line 14g, a main gate line 13g, a third gate line 19g, and a fourth gate line 20g are provided on the semiconductor substrate 10A, and each of them is a first gate electrode TX1. The second gate electrode TX2, the photogate electrode PG, the third gate electrode TX1 ′, and the fourth gate electrode TX2 ′ are electrically connected.

  Between the gate electrodes TX1, TX2, PG, TX1 ′, TX2 ′ and the gate wirings 12g, 14g, 13g, 19g, 20g, contact electrodes 12a, 14a, 13a, 19a, 20a, pad electrodes 12b, 14b, 13b, 19b, 20b, bumps 12c, 14c, 13c, 19c, 20c, pad electrodes 12d, 14d, 13d, 19d, 20d, contact electrodes 12e, 14e, 13e, 19e, 20e, intermediate electrodes 12f, 14f, 13f , 19f, 20f are interposed.

  Each contact electrode is embedded in a contact hole provided in the insulating layers 1F, 10B, and 10C as shown in the figure.

  The adhesion area AD includes an adhesion layer AD1 made of resin and bumps 11c, 12c, 13c, 14c, 15c, 18c, and 19c for connecting each electrode of the back-illuminated distance measuring sensor 1 to various wirings on the wiring board 10. , 20c, 21c.

  In this distance measuring device, the front surface 1FT of the back-illuminated distance measuring sensor 1 is fixed on the mounting surface M of the wiring substrate 10 via the insulating layer 1E, various electrodes, and the adhesion region AD, and the first gate electrode TX1. The second gate electrode TX2, the photogate electrode PG, the third gate electrode TX1 ′, the fourth gate electrode TX2 ′, the N-type semiconductor regions CD1, CD2, FD1, and FD2 are bumped on the wiring on the wiring substrate 10. Connected through. In this distance measuring device, when the back-illuminated distance measuring sensor 1 is mounted on the wiring board 10, the signal can be given to each electrode through each wiring, and the device is miniaturized.

  A light absorption layer SH made of a black resin is formed on the mount surface M of the wiring board 10 to suppress the incidence of light transmitted through the back-illuminated distance measuring sensor 1 to the wiring board 10 and The light reflected by the wiring on the wiring board 10 is prevented from returning to the back-illuminated distance measuring sensor 1 and causing crosstalk. The various electrodes or wirings described above are made of aluminum or polysilicon. The thickness t1 of the semiconductor substrate made of Si in the back-illuminated distance measuring sensor 1 is 10 to 100 μm, preferably 15 to 50 μm, and 20 μm in this example.

  In this back-illuminated distance measuring sensor 1, carriers generated in the deep part of the semiconductor in response to the incidence of light for projection are drawn into a potential well provided in the vicinity of the carrier generation position on the side opposite to the light incident surface 1BK. High speed and accurate distance measurement are possible.

Semiconductor substrate 1A, 'the pulse light L _D from the object incident from the light incident surface (back surface) 1BK of the semiconductor substrate 1A, 1A' 1A to just below the region of the surface side of the photo gate electrode PG of (photosensitive region) It reaches. Carriers generated in the semiconductor substrates 1A and 1A ′ with the incidence of the pulsed light are distributed from the photosensitive region to the regions immediately below the first and second gate electrodes TX1 and TX2. That is, the first and second gate electrodes TX1, TX2 to the light source drive signal _S gate signal detection is synchronous with the _{P S} L, the _{S R,} via the wiring board 10, given alternately photosensitive region and Carriers generated in the nearby semiconductor region flow into regions immediately below the first and second gate electrodes TX1 and TX2, respectively, and flow into the storage regions CD1 and CD2.

  Carriers stored in the storage regions CD1 and CD2 are transferred to the semiconductor regions FD1 and FD2, respectively, by applying a transfer voltage to the third and fourth gate electrodes.

The ratio of the charge amounts Q1 and Q2 of the carriers accumulated in the first semiconductor region FD1 or the second semiconductor region FD2 to the total charge amount (Q1 + Q2) is the emitted pulse light emitted by applying the drive signal _SP to the light source. This corresponds to the phase difference of the detected pulse light that has returned by reflecting the emitted pulse light by the object H.

Even if the charge distribution speed is increased by increasing the frequency of the drive signals (detection gate signals S _L and S _R ) to the gate electrodes TX1 and TX2, it is generated in response to the incidence of near-infrared light. Since the carrier generation region is closer to the surface 1FT on the opposite side than the light incident surface 1BK of the semiconductor substrate 1A, many carriers flow from the photosensitive region to the storage regions CD1 and CD2, and from these regions, the semiconductor region FD1 , FD2 are transferred, and the stored charges Q1 and Q2 can be read out via the wirings 18h and 21h of the wiring board 10. In addition, since light having a wavelength shorter than near infrared tends to be removed in the region on the light incident surface 1BK side of the semiconductor substrates 1A and 1A ′, a visible light cut filter is not provided on the light incident surface side. The detection accuracy of the detection pulse light for distance measurement can be improved.

  The N-type semiconductor regions FD1 and FD2 serving as the floating diffusion regions are reset after reading the accumulated charges. When a positive potential is applied to the semiconductor regions FD1 and FD2, the semiconductor regions FD1 and FD2 are reset. The carriers remaining in the storage regions CD1 and CD2 are also discharged to the outside through the wirings 11h and 15h after the transfer voltage is applied.

The thickness / impurity concentration of each semiconductor region is as follows.
Substrate body 1A: thickness 10 to 100 μm / impurity concentration 1 × 10 ¹² to 10 ¹⁹ cm ⁻³
Epitaxial layer 1A ′: thickness 1 to 5 μm / impurity concentration 1 × 10 ¹² to 10 ¹⁵ cm ⁻³
Semiconductor regions FD1, FD2: thickness 0.1 to 0.4 μm / impurity concentration 1 × 10 ¹⁸ to 10 ²⁰ cm ⁻³
Storage regions CD1, CD2: thickness 0.1 to 0.4 μm / impurity concentration 1 × 10 ¹⁸ to 10 ²⁰ cm ⁻³

Note that the thickness of the semiconductor substrate of this example is 20 μm, the impurity concentration is 1 × 10 ¹² cm ⁻³ , and the impurity concentrations of the regions FD1, FD2, CD1, and CD2 are 1 × 10 ¹⁹ cm ⁻³ .

  Note that a reference potential such as a ground potential is applied to the semiconductor substrates 1A and 1A 'via a back gate or a through electrode.

  FIG. 6 is a cross-sectional view in the vicinity of the back gate.

  That is, in order to fix the potentials of the semiconductor substrates 1A and 1A ′ of the back-illuminated distance measuring sensor 1 to the reference potential, the distance measuring sensor according to the present embodiment has a high concentration in the P-type epitaxial layer 1A ′. A P-type back gate semiconductor region BG containing impurities is provided. A ground wiring 16h is provided on the semiconductor substrate 10A of the wiring substrate 10 provided with the signal readout circuit. A contact electrode 16a, a pad electrode 16b, a bump 16c, a pad electrode 16d, a contact electrode 16e, an intermediate electrode 16f, and a contact electrode 16g are interposed between the back gate semiconductor region BG and the ground wiring 16h. Electrically connected.

  FIG. 7 is a sectional view of the vicinity of the through electrode.

  In order to fix the potential of the semiconductor substrate 1A of the back-illuminated distance measuring sensor 1 to the reference potential, a P-type semiconductor layer such as a P-type diffusion region W4 embedded in the substrate is used instead of the back gate electrode. However, the through electrode 17x electrically connected thereto may be provided. A ground wiring 17 h is provided on the semiconductor substrate 10 </ b> A of the wiring substrate 10. A contact electrode 17a, a pad electrode 17b, a bump 17c, a pad electrode 17d, a contact electrode 17e, an intermediate electrode 17f, and a contact electrode 17g are interposed between the through electrode 17x and the ground wiring 17h. Connected to.

  FIG. 8 is a potential diagram in the vicinity of the substrate surface for explaining the carrier accumulation operation according to the embodiment.

In this potential diagram, the downward direction is the positive direction of the potential. When light is incident, the potential φ _PG of the region immediately below the photogate electrode PG (photosensitive region) is the substrate potential when the potential (φ _TX2 ) of the region immediately below the adjacent gate electrode at the time of no bias is used as a reference potential. Is set higher than. The potential φ _PG of this photosensitive region is higher than the potential φ _TX2 , and the potential diagram of this region has a shape recessed downward in the drawing.

In the storage area CD1, CD2, since the N-type impurity is added, is concave the potential in the positive direction, given a high potential to the gate electrode TX1, the potential of the photosensitive region phi _PG is one of the storage areas CD1 Tilt only in the direction of.

In this figure, the potential phi _TX1 in the region immediately below the gate electrode TX1, the region of potential phi _TX2 immediately under the gate electrode TX2, the potential phi _PG in the photosensitive region immediately under the photo gate electrode PG, the potential of the accumulation region CD1 phi _CD1, the potential phi _CD2 storage area CD2, the potential phi _FD1 of the semiconductor area FD1, potential phi _FD2 of the semiconductor area FD2 is shown.

High potential of the detection gate signal S _L is inputted to the gate electrode TX1, the carriers generated in the vicinity of the photosensitive region (electrons e), according to the potential gradient, through a region immediately below the gate electrode TX1 Then, the charge is accumulated in the potential well of the accumulation region CD1, and the charge amount Q1 corresponding to the charge amount Q1 + external light component is accumulated in the potential well. For the sake of convenience, the charge amounts of carriers generated by a plurality of pulse irradiations are also indicated by Q1 and Q2.

  FIG. 9 is a potential diagram in the vicinity of the substrate surface for explaining the carrier accumulation operation.

During the light incidence, the potential phi _PG in the photosensitive region is slightly set higher than the potential phi _TX1 in the region immediately below the adjacent gate electrodes TX1.

Following detection gate signal S _L, the high potential of the detection gate signal S _R is inputted to the gate electrode TX2, carriers generated in the light-sensitive area (electrons e), according to the potential gradient, the gate The charge is accumulated in the potential well of the accumulation region CD2 via the region immediately below the electrode TX2, and the charge amount Q2 + corresponding to the external light component is accumulated in the potential well.

Detection gate signal S _L, the high potential of the detection gate signal S _R after applying a plurality of times alternately to the gate electrode TX1, TX2, respectively, carriers generated in response to external light, the storage area CD1, the CD2 In order to remain, the barrier height with respect to the electrons of the potentials φ _TX1 ′ and φ _TX2 ′ is lowered. That is, when a high potential is applied to the third and fourth gate electrodes TX1 ′, TX2 ′, the charge amount ΔQ corresponding to the external light component among the carriers accumulated in the accumulation regions CD1, CD2 is a potential barrier (φ _TX1 ', Φ _TX2 ') cannot be exceeded, and only the carriers of the charge amounts Q1, Q2 generated corresponding to the incidence of the pulsed light are transferred into the potentials φ _FD1 , φ _FD2 , respectively.

As described above, the external light is applied to the third gate electrode TX1 ′ and the fourth gate electrode TX2 ′ by applying a transfer voltage having such a magnitude that the charge amount of the external light component remains in the potentials φ _CD1 and φ _CD2 . The signal from which the component is removed can be read from the semiconductor regions FD1 and FD2. As described above, the charges Q1 and Q2 accumulated in each potential well are read out to the outside through the read wirings 18h and 21h (see FIG. 5) provided on the wiring board 10.

As described above, the carriers accumulated in the first and second potential wells (φ _CD1 , φ _CD2 ) are barriers between the third and fourth potential wells (φ _FD1 , φ _FD2 ) (φ _TX1 ′, ( _φTX2 ′) When the height is reduced, the _gas flows into the third and fourth potential wells ( _φFD1 , _φFD2 ), respectively. The height of this barrier ( _φTX1 ′, _φTX2 ′) depends on the magnitude of the transfer voltage applied to the third and fourth gate electrodes TX1 ′, TX2 ′. When a large transfer voltage is applied, the barrier height is reduced, and many carriers are transferred from the first and second potential wells (φ _CD1 , φ _CD2 ) to the third and fourth potential wells (φ _FD1 , φ _FD2). ) Flows into.

Barriers (φ _TX1 ′, φ _TX2 ) so that carriers having a charge amount equal to the amount of carriers generated in response to the incidence of external light remain in the first and second potential wells (φ _CD1 , φ _CD2 ). If the height of ') is set, carriers from which external light components are removed during transfer are transferred from the first and second potential wells (φ _CD1 , φ _CD2 ) to the third and fourth potential wells (φ _FD1). , Φ _FD2 ). Carriers are accumulated in the first and second potential wells (φ _CD1 , φ _CD2 ) by alternately applying a voltage to the first and second gate electrodes TX 1, TX ₂ . Among the carriers accumulated in these potential wells, carriers having a charge amount from which the external light component has been removed flow into the third and fourth potential wells (φ _FD1 , φ _FD2 ) and are read out.

At the time of transfer, the higher the intensity of external light detected by the detection means (photodetecting element PD) shown in FIGS. 12 and 13, the lower the transfer voltage, the higher the barrier height (φ _TX1 ′, φ _TX2 ′) becomes higher, and more charge carriers remain in the first and second potential wells (φ _CD1 , φ _CD2 ). That is, the higher the intensity of external light, the more carriers remain and are removed from the carrier that is finally read.

  Further, if the gate electrodes PG, TX1, TX2, TX1 ′, TX2 ′ are made of metal or a metal film is formed on the light incident surface side as polysilicon, the light once transmitted through the semiconductor substrate by this metal. Since the light is reflected, the light use efficiency can be increased.

  Further, a visible band cut filter may be deposited on the light incident surface side of the semiconductor substrate. Moreover, the above-mentioned distance measuring sensor can also be modularized including a light source.

  FIG. 10 is a plan view of the distance measuring sensor when the distance measuring sensor according to the above-described embodiment is viewed from the gate electrode side. Note that the insulating layer is omitted.

  In this distance measuring sensor, gate electrodes TX1 and TX2 are arranged adjacent to the photogate electrode PG in one pixel P (m, n). Accumulation regions CD1 and CD2 are located between the gate electrodes TX1 and TX2 and the gate electrodes TX1 'and TX2', respectively. Semiconductor regions FD1 and FD2 are located outside the accumulation regions CD1 and CD2. The accumulation regions CD1 and CD2 constitute the source of a field effect transistor having the charge discharge gate electrodes TBD1 and TBD2 as gates, and the discharge regions CD1 'and CD2' constitute the drain. When a transfer voltage is applied to the charge discharge gate electrodes TBD1 and TBD2, carriers accumulated in the accumulation regions CD1 and CD2 are transferred to the discharge regions CD1 'and CD2', respectively, and discharged to the outside. Note that a reset transistor having gate electrodes (RG1, RG2) and connected to the storage regions CD1, CD2 may be formed in one pixel as necessary.

  FIG. 11 is a circuit diagram showing a carrier reading circuit.

  In the back-illuminated distance measuring sensor described above, the distance measuring sensor is mounted on the wiring board via bumps. In this case, the carrier readout transistor connected to the pixel P (m, n) is provided on the wiring board side, and the number of elements included in the distance measuring sensor alone is reduced. As will be described later, the distance measuring sensor can be a front-illuminated type, and a carrier reading transistor can be disposed on the same semiconductor substrate. In this case, the transistor is provided in the semiconductor substrate of the distance measuring sensor. Therefore, the number of elements included in a single pixel (indicated by a dotted line as P ′ (m, n)) increases. In other words, if the pixel area of the back-illuminated distance measuring sensor is the same as that of the front-illuminated distance measuring sensor, the area of the photosensitive region can be increased.

  In the figure, gate electrodes TX1, TX2, PG, TX1 ′, TX2 ′, TBD1, TBD2, RG1, and RG2 constitute the gate electrode of the field effect transistor. These field effect transistors are denoted by the same reference numerals as the corresponding gate electrodes (TX1, TX2, PG, TX1 ′, TX2 ′, TBD1, TBD2, RG1, RG2).

  When the high potential is applied to the gate electrode TX1, carriers generated in the photosensitive region immediately below the photogate electrode PG have the field effect transistor (TX1) turned on (the field effect transistor (TX2) is OFF), it flows into the potential well constituted by the storage region CD1 via this field effect transistor (TX1).

  On the other hand, when a high potential is applied to the gate electrode TX2, carriers generated in the photosensitive region immediately below the photogate electrode PG have the field effect transistor (TX2) turned on (field effect transistor (TX1)). ) Is OFF), and flows into the potential well formed by the storage region CD2 via the field effect transistor (TX2).

  Such accumulation is performed a plurality of times alternately.

  The carriers (charges) accumulated in the accumulation regions CD1 and CD2 are transferred to the semiconductor regions FD1 and FD2 by turning on the transfer transistors (TX1 ′, TX2 ′), and the gate electrodes of the field effect transistors QFD1 are respectively supplied. (Readout wiring 18h: see FIG. 5) and the gate electrode of the field effect transistor QFD2 (readout wiring 21h: see FIG. 5).

  The power supply potential V + and the sources of the selection transistors SEL1 and SEL2 are connected according to the potential input to the gate electrodes of the field effect transistors QFD1 and QFD2, and a high level read potential is applied to the gate electrodes of the selection transistors SEL1 and SEL2. Then, charges corresponding to the charge amount of carriers accumulated in the semiconductor regions FD1 and FD2 are held in the sample hold circuits S / H (1) and S / H (2) via the vertical read lines LL and RL. Is done. The charges accumulated in the sample hold circuits S / H (1) and S / H (2) are transferred to the horizontal read lines H1 and H2 by inputting the horizontal read signal from the horizontal shift register to the switches SW1 and SW2. Is output.

  When the reading of the charge is completed, a high potential is applied to the reset gate electrodes RG1 and RG2, the field effect transistors (RG1 and RG2) are turned on, the reset drain regions RD1 and RD2 connected to the power supply potential V ++, and the storage region CD1. , CD2 are connected to each other, and the storage areas CD1. CD2 is reset. At this time, if the transistors (TX1 ', TX2') are turned on, the semiconductor regions FD1, FD2 as the floating diffusion regions are also reset. Note that when electrons are accumulated in the semiconductor region, the potential thereof decreases as the negative charge increases.

  Note that the sample hold circuits S / H (1) and S / H (2) sample the charges from the drains of the select transistors SEL1 and SEL2 at the time of resetting and at the end of charge accumulation. That is, the potentials of the semiconductor regions FD1 and FD2 at the time of resetting and the semiconductor regions FD1. By holding both potentials of FD2 in the sample hold circuits S / H (1) and S / H (2), the difference between these potentials is detected as the amount of charge accumulated in the semiconductor regions FD1 and FD2, The difference can be output as the accumulated charge amounts Q1 and Q2 to the horizontal readout lines H1 and H2 via the switches SW1 and SW2. Note that carriers remaining in the accumulation regions CD1 and CD2 after carrier transfer can be discharged to the outside by turning on the transistors (TBD1 and TBD2).

  As described above, the charge amount Q1 is input to the horizontal read line H1, and the charge amount Q2 is input to the horizontal read line H2, and is output to the outside.

  FIG. 12 is a circuit diagram of a transfer voltage application circuit to the third and fourth gate electrodes TX1 ', TX2'.

  The distance measuring sensor described above includes a light detection element PD such as a photodiode. The light detection element PD detects the intensity of external light, and is provided with an inversion circuit INV and a switch SWX on the output side. The higher the intensity of external light, the third and fourth gate electrodes TX1 ′, The magnitude of the transfer voltage applied to TX2 ′ is reduced, that is, the potential barrier at the time of carrier transfer is high, and the amount of carriers corresponding to external light remains in the accumulation region. The transfer voltage is applied to the third and fourth gate electrodes TX1 'and TX2' by turning on the switch SWX.

  The output of the light detection element PD is input to the control circuit CONT. As the intensity of the external light detected by the light detection element PD is higher, the control circuit CONT increases the number of times the switch SWX is turned ON per unit time.

  FIG. 13 is a circuit diagram of a transfer voltage application circuit to the third and fourth gate electrodes TX1 'and TX2'.

  The output of the light detection element PD is input to the control circuit CONT, and the control circuit CONT controls the transfer voltage output from the transfer voltage application circuit TVA according to the input output of the light detection element PD. The transfer voltage is input to the third and fourth gate electrodes TX1 'and TX2'. The control circuit CONT applies the transfer voltage so that the magnitude of the transfer voltage applied to the third and fourth gate electrodes TX1 ′ and TX2 ′ decreases as the external light intensity detected by the light detection element PD increases. Control the circuit TVA.

  In addition, the higher the intensity of external light detected by the light detection element PD, the greater the number of times that the control circuit CONT applies the transfer voltage per unit time.

As described above, the distance measuring device reads the charges accumulated in the wells of the third and fourth potentials φ _{TX1 ′} and φ _{TX2 ′} after the end of the unit period _TF. Is provided with a light detecting element (detecting means) PD. As the light detection element PD, the output of its own pixel, that is, the carrier discharged from the storage regions CD1 and CD2 can be used.

Further, the distance measuring device reduces the magnitude of the transfer voltage as the intensity of external light detected by the transfer voltage application means (TVA, SWX) for applying the transfer voltage and the detection means increases, and Control means CONT is provided for controlling the transfer voltage application means (TVA, SWX) so as to increase the transfer voltage application frequency N per unit period _TF .

As described above, the distance measuring device according to the above-described embodiment includes the light source 3 that emits the modulated light toward the object H, and the first and second gate electrodes TX1 provided on the semiconductor substrates 1A and 1A ′. , TX2 by alternately applying a voltage, first and second potential wells (φ _CD1 , φ _CD2 ) for alternately accumulating carriers generated according to incident light, and first and second potential wells ( Third and fourth potential wells (φ _CD3 , φ _CD4 ) adjacent to φ _CD1 , φ _CD2 ), respectively, and a transfer voltage is applied, whereby the first potential well (φ _CD1 ) and the third potential well (φ barrier to carrier between _FD1) (φ _{TX1 ')} third gate electrode TX1 to set the height to a predetermined value', by the transfer voltage is applied, the second potential well (phi _{C 2)} and the fourth barrier (phi _TX2 to carrier between the potential well (phi _FD2) and a 'a) Height fourth gate electrode TX2 is set to a predetermined value', the unit period _{(T F)} since the end of _Are distance measuring devices that respectively read out the charges accumulated cumulatively in the third and fourth potential wells (φ _FD1 , φ _FD2 ), detecting means (PD) for detecting external light, and application of transfer voltage The transfer voltage application means (TVA, SWX) for performing the transfer and the intensity of the external light detected by the detection means (PD), the smaller the transfer voltage, and the transfer per unit period (T _F ) Control means CONT for controlling transfer voltage application means (TVA, SWX) so as to increase the number of times of voltage application
And.

The transfer voltage application frequency N per unit period _TF increases as the intensity of external light increases. That is, if the external light is strong, the number of carrier transfers per unit period _TF increases, and the transfer is performed before the carriers accumulated in the wells of the first and second potentials φ _TX1 and φ _TX2 are saturated. Is called. If the outside light is weak, the number of carrier transfers per unit period _TF decreases, and unnecessary transfer is not performed, thereby increasing the amount of accumulated charge per unit time _TF and improving detection accuracy in a short detection time. Can be made.

Since this unit period _TF does not depend on the intensity of external light, the carriers accumulated in the wells of the third and fourth potentials φ _TX1 ′ and φ _TX2 ′ after the end of the unit period _TF are periodically transferred. It only needs to be read, and no special control is required for reading. That is, according to the distance measuring apparatus according to the embodiment, distance detection can be performed with a simple configuration.

  Further, as shown in FIG. 5, the distance measuring device described above includes the first, second, third and fourth gate electrodes TX1, TX2, TX1 ′, TX2 ′ on the side opposite to the light incident surface 1BK. This distance measuring device constitutes a back-illuminated distance measuring sensor so that carriers generated in a region opposite to the light incident surface 1BK of the semiconductor substrate can be efficiently collected. Thus, it is possible to perform highly accurate distance measurement.

  14 to 16 are timing charts of charge reading.

The unit period _{T F} is given in the period up to time _t 1 _{~t 24.} Pulse drive signal S _P and the detection gate signal S _L are in phase, the gate signal S _R for detecting the pulse drive signal S _P is antiphase. Before the start of carrier distribution, the detection gate signals S _L and S _R , the external light accumulation signal T _N , and the carrier discharge signal S _EX are at a high level from time t _{1 to} t ₂ , and are stored in the accumulation areas CD 1 and CD 2. The accumulated carriers are discharged to the outside, and the output of the light detection element PD is accumulated as external light. Note that carriers discharged from the accumulation regions CD1 and CD2 can be used as external light. Until time _t 1 ~t _2, the transfer voltage (transfer signal) _{S T} is at a low level, the carrier transfer is not performed from the storage area CD1, CD2 to the semiconductor regions FD1, FD2.

In the unit period _TF , when N = 4 carrier transfers are performed (FIG. 16), the period until the first carrier transfer is finished is defined as a predetermined period _TF ′. The unit period T _F corresponds to X (= N) times the predetermined period T _F ′. In FIG. 16, a half period (T _M / 2) of the carrier distribution period T _M is set as the external light accumulation period. Do this by, to become the same amount of carriers and carriers accumulated in one accumulation region in the carrier distribution within the period T _M is generated by the light detecting element, the level adjustment of the transfer voltage in proportion to the ambient light It becomes easy.

Note that the carrier distribution period in FIG. 14 is from time t _{3 to} t ₂₂ , and the external light accumulation period is set to, for example, half (T _M / 2) of this period. Further, the carrier distribution period in FIG. 15 is from time t _{3 to} t ₁₀ , and the external light accumulation period is set to, for example, half (T _M / 2) of this period.

When performing N = 1 single carrier transfer as in FIG. 14, at time _t 23 _{~t 24} after the carrier sorting ends, the transfer signal _{S T} is at a high level, it is stored in the storage area CD1, the CD2 carrier , are transferred to the semiconductor region FD1, in FD2, then, by the carrier discharging signal _{S EX} is high level at time _t 23 _{~t 24,} residual carriers in the accumulation region CD1, the CD2 is discharged to the outside, then The storage areas CD1 and CD2 and the semiconductor areas FD1 and FD2 are reset. By sampling and holding the potentials of the semiconductor regions FD1 and FD2 immediately after the carrier transfer and the reset potential, the amount of charge accumulated in the semiconductor regions FD1 and FD2 can be detected.

When performing N = 2 times the carrier transfer as in FIG. 15, in each of the carrier distribution after the end time _t 11 _~t 12 _of, t 23 _{~t 24,} the transfer signal _{S T} is at a high level, the storage area CD1, carriers stored in the CD2 is transferred to the semiconductor region FD1, in FD2, then, by the carrier discharging signal _{S EX} is high level at time _{t 13 ~t 14, t 25 ~t} 26, storage area CD1 , The carriers remaining in CD2 are discharged to the outside, and after discharge of the carriers immediately after the unit period, the storage regions CD1, CD2 and the semiconductor regions FD1, FD2 are reset. By sampling and holding the potentials of the semiconductor regions FD1 and FD2 immediately after the carrier transfer and the reset potential, the amount of charge accumulated in the semiconductor regions FD1 and FD2 can be detected.

When performing carrier transfer N = 4 times as shown in FIG. 16, transfer is performed at times t _{5 to} t ₆ , t _{11 to} t ₁₂ , t _{17 to} t ₁₈ , and t _{23 to} t ₂₄ after the completion of the carrier allocation. signal _{S T} becomes high level, the accumulated carriers in the accumulation region CD1, the CD2 is transferred to the semiconductor region FD1, in FD2, then, the carrier discharging signal _{S EX} is time _t 7 _{~t 8, t} 13 _{~t 14} , t _{19 to} t ₂₀ , t _{25 to} t ₂₆ , the carriers remaining in the accumulation regions CD 1 and CD 2 are discharged to the outside, and after discharging the carriers immediately after the unit period, the accumulation regions CD 1 and CD 2 The semiconductor regions FD1 and FD2 are reset. By sampling and holding the potentials of the semiconductor regions FD1 and FD2 immediately after the last carrier transfer in the unit period and the reset potential, the amount of charge accumulated in the semiconductor regions FD1 and FD2 can be detected.

According to the control described above, the number of transfer voltage applications per unit period _TF increases as the intensity of external light increases. That is, if the external light is strong, the number of transfers N per unit period _TF increases, and the transfer is performed before the carriers accumulated in the wells of the first and second potentials φ _CD1 and φ _CD2 are saturated. . If the outside light is weak, the number of transfers N per unit period T _F decreases, and unnecessary transfer is not performed, thereby increasing the accumulated charge amount per unit time T _F and improving the detection accuracy in a short detection time. be able to. That is, in FIG. 14, since only one carrier transfer is performed, more carriers can be accumulated per unit period _TF than in the control of FIGS. Since only carrier transfer is performed twice in FIG. 15, more carriers can be accumulated per unit period _TF than in the control of FIG. Further, it is possible to reduce transfer noise by reducing the number of transfers, and it is possible to reduce the power of the light source by increasing the number of carrier integrations without saturating the potential.

  As described above, in the distance measuring apparatus described above, the accumulation time and the transfer period (external light cancellation period) are set as one cycle, and the irradiation light is first applied within a predetermined period (one frame) until the accumulated charge is read. The number of repetitions of one cycle within one frame is determined according to the monitored light amount, and the charge accumulated at the end of one frame is read out.

When the number of transfers (external light cancellation) is four, it is assumed that 10,000 charge distributions are performed. Also, the external light accumulation period is set to T _{M /} 2 period, the external light cancel period allocated with T _{M /} 2 period. In this case, the number of times of charge distribution is reduced by an amount corresponding to the external light accumulation period. For example, the charge distribution may be performed 40000 times when the external light cancel count is 4 times, 60000 times when the external light cancel count is 2 times, 70,000 times when the external light cancel count is once, and 80000 times when the external light cancel is not performed. it can.

  When the external light is very small, the total accumulation time is assigned to the charge distribution period as shown in FIG. 14, and when the external light exceeds saturation, the number of external light cancellations is adaptively shown in accordance with the light intensity. 15. As shown in FIG. 16, external light can be canceled while changing to avoid saturation. When the accumulation time is different, the absolute value of the accumulated signal amount changes. However, since the difference in the modulation signal is used for distance measurement in the distance measurement principle, the influence of the absolute value of the signal amount is reduced.

Even when the external light is strong, the signal within the predetermined period T _F ′ is accumulated in the potential well (memory) in the pixel while using the external light cancellation function, and at the end of the unit period (frame). The signal can be read out. Thereby, even when the external light is strong (that is, the exposure time is short), a high S / N signal can be acquired.

  Next, an example of application to the surface incidence type distance measuring sensor having the above structure will be described. The circuit structure can also be applied to a back-illuminated distance measuring sensor.

  FIG. 17 is a plan view of the surface incidence type distance measuring sensor 1.

  The distance measuring sensor 1 includes a semiconductor substrate 1A having an imaging region 1B composed of a plurality of pixels P (m, n) arranged in a two-dimensional manner. Each pixel P (m, n) has the same circuit structure as the pixel P ′ (m, n) shown in FIG. From each pixel P (m, n), two charge amounts (Q1, Q2) are output as the signal d '(m, n) having the above-described distance information. Since each pixel P (m, n) outputs a signal d ′ (m, n) corresponding to the distance to the object H as a minute distance measuring sensor, the reflected light from the object H is coupled to the imaging region 1B. If an image is obtained, a distance image of the object as a collection of distance information to each point on the object H can be obtained.

  On the semiconductor substrate 1A, there is provided a sample hold circuit group SHG having the sample hold circuit S / H shown in FIG. 11 for each pixel column, and each sample hold circuit S / H is shown in FIG. The switches SW1 and SW2 are connected to the horizontal readout lines H1 and H2 through a readout switch group RS having each pixel column. The horizontal read lines H1 and H2 are input to the amplifier AP. Each switch of the read switch group RS is turned ON / OFF by a horizontal read signal from a horizontal shift register HS formed on (or in the vicinity of) the semiconductor substrate 1A.

A vertical shift register VS is formed on (or in the vicinity of) the semiconductor substrate 1A, and the selection signals S _{SEL (i),} S _{SEL (i + 1),} ... Applied to the transistor SEL1 (SEL2) in FIG. For each pixel row, the voltage is sequentially applied to the gate electrodes of the transistors SEL1 (SEL2) (see FIG. 11) in each pixel row. A reset signal applied to the reset gate electrodes RG1 and RG2 in FIG. 11 is also supplied from the vertical shift register VS.

  The reference clock signal from the timing generation circuit TG is input to the horizontal shift register HS and the vertical shift register VS, and the horizontal shift register HS and the vertical shift register VS receive a horizontal read signal and a selection signal based on the reference clock signal. And a reset signal.

  FIG. 18 is a cross-sectional view of one pixel in the surface incidence type distance measuring sensor.

  A light shielding film SHL having an opening above the photogate electrode PG is disposed on the light incident surface side. This structure is the same as that of the back-illuminated distance measuring sensor 1 shown in FIG. 5 except that the semiconductor substrates 1A and 1A ′ are thicker than the back-illuminated distance measuring sensor. . The thickness of the semiconductor substrates 1A and 1A 'is 200 μm or more, and the antireflection film 1D on the back side of the substrate shown in FIG. 5 is omitted.

  Note that the above-described photogate electrode PG may be one for each distance measuring sensor, and a plurality of minute distance measuring sensors including the photogate electrode PG are arranged in a one-dimensional or two-dimensional manner as pixels, and then one-dimensional or two-dimensional. It is good also as a ranging sensor which can obtain the distance image. It is also possible to provide a light-shielding film SHL opened only above the photosensitive region on the light incident surface side of the back-illuminated distance measuring sensor 1, thereby causing crosstalk due to oblique incidence on the semiconductor regions FD1 and FD2. It can also be reduced.

  Next, a case where each pixel P (m, n) has four transfer gate electrodes around the photogate electrode PG will be described.

  FIG. 19 is a plan view of such a pixel.

  The structures of the electrodes and the semiconductor regions arranged in the horizontal direction are the same as those shown in FIG. 10, but the positions of the gate electrodes TBD1 and TBD2 for discharging carriers are point-symmetric with respect to the center of gravity of the photogate electrode PG. Is different from the above.

  The structure of the electrodes arranged in the vertical direction and the respective semiconductors is a group in which the group arranged in the horizontal direction is rotated 90 degrees around the center of gravity of the photogate electrode PG, and the semiconductor region FD1a and the gate electrode TX1a are sequentially formed from one end. ', The storage region CD1a, the gate electrode TX1a, the photogate electrode PG, the gate electrode TX2a, the storage region CD2a, the gate electrode TX2a, and the photogate electrode FD2a are arranged, and the respective elements are the semiconductor region FD1, the gate electrode TX1', This is the same as the storage region CD1, the gate electrode TX1, the photogate electrode PG, the gate electrode TX2, the storage region CD2, the gate electrode TX2, and the photogate electrode FD2.

  The storage regions CD1a and CD2a are connected to the discharge regions CD1a ′ and CD2a ′ via the gate electrodes TBD1a and TBD2a. The relationship between the storage regions CD1 and CD2, the gate electrodes TBD1 and TBD2, and the discharge regions This is the same as the relationship between CD1 ′ and CD2a ′.

  Assume that charge amounts Q1 and Q2 are output from the semiconductor regions FD1 and FD2 located at both ends in the horizontal direction, and charge amounts Q3 and Q4 are output from the semiconductor regions FD1a and FD2a located at both ends in the vertical direction.

In the above-described embodiment, an example in which the two gate electrodes TX1 and TX2 are driven with a phase difference of 180 degrees has been described. TX2a is driven. In this case, the distance d = Φ × c / 2 × 2πf is given. Incidentally, when the drive signal is sinusoidal is, f is the repetition frequency of the drive pulse signal _{S P,} is given by the phase Φ = -arctan ((Q2-Q4 ) / (Q1-Q3)).

  FIG. 20 is a plan view of the distance measuring sensor 1 having the pixels of FIG.

  This distance measuring sensor 1 is obtained by adding a horizontal shift register HS2, an amplifier AP2, horizontal readout lines H1 ′ and H2 ′, a switch group RS2, and a sample hold circuit group SHG2 to those shown in FIG. Is the same as the horizontal shift register HS, the amplifier AP, the horizontal readout lines H1 and H2, the switch group RS, and the sample hold circuit group SHG, and the charge amount output from each pixel is replaced by Q3 and Q4. It is what.

  That is, the amplifier AP outputs a signal d (Q1, Q2), and the amplifier AP2 outputs a signal d (Q3, Q4).

  As described above, with the distance measuring device according to the above-described embodiment, the distance to the object can be measured accurately and easily in a short detection time.

It is explanatory drawing which shows the structure of a distance measuring device. 2 is a plan view of the distance measuring sensor 1. FIG. FIG. 3 is a sectional view of the distance measuring sensor shown in FIG. 2 along arrows III-III. It is sectional drawing of the distance measuring sensor which concerns on a modification. FIG. 5 is an enlarged view of a region V of the distance measuring sensor shown in FIG. 3 or FIG. 4. It is sectional drawing of the back gate vicinity. It is sectional drawing of the penetration electrode vicinity. It is a potential diagram in the vicinity of the substrate surface for explaining the carrier accumulation operation. It is a potential diagram in the vicinity of the substrate surface for explaining the carrier accumulation operation. It is a top view of the pixel of the ranging sensor which looked at the ranging sensor from the gate electrode side. It is a circuit diagram which shows the read-out circuit of a carrier. It is a circuit diagram of a transfer voltage application circuit. It is a circuit diagram of the application circuit of another transfer voltage. It is a timing chart of charge reading. It is a timing chart of charge reading. It is a timing chart of charge reading. 2 is a plan view of the distance measuring sensor 1. FIG. It is sectional drawing of 1 pixel in a surface incidence type distance measuring sensor. It is a top view of the pixel of the ranging sensor which looked at the ranging sensor from the gate electrode side. 2 is a plan view of the distance measuring sensor 1. FIG.

Explanation of symbols

  1A (1A ') ... Semiconductor substrate, PG ... Photogate electrode, TX1, TX2 ... Gate electrode, CD1, CD2 ... Storage region, FD1, FD2 ... Semiconductor region (floating diffusion region) ).

Claims (3)

A light source that emits modulated light toward an object;
First and second potential wells that alternately accumulate carriers generated according to incident light by alternately applying a voltage to first and second gate electrodes provided on a semiconductor substrate;
Third and fourth potential wells adjacent to the first and second potential wells, respectively;
A third gate electrode that sets a barrier height for carriers between the first potential well and the third potential well to a predetermined value by applying a transfer voltage;
A fourth gate electrode that sets a barrier height for carriers between the second potential well and the fourth potential well to a predetermined value by applying a transfer voltage;
With
A distance measuring device that reads out charges accumulated in the third and fourth potential wells after the end of a unit period,
Detection means for detecting outside light;
Transfer voltage applying means for applying the transfer voltage;
Control for controlling the transfer voltage application means so that the magnitude of the transfer voltage is reduced and the number of transfer voltage application times per unit period is increased as the intensity of the external light detected by the detection means is higher. Means,
A distance measuring device comprising:   2. The distance measuring apparatus according to claim 1, wherein the first, second, third and fourth gate electrodes are provided on the opposite side of the light incident surface.   The distance measuring apparatus according to claim 1, further comprising a calculation unit that calculates a distance to the target object based on a ratio of the read charges to the total charge amount.

Images