JP2009037277A - Appearance color histogram creation circuit and image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor not requiring a CPU to perform processing to specify the most frequently appearing color when performing image processing which needs the most frequently appearing color. <P>SOLUTION: An image processor of a composite machine or the like is equipped with an appearance color histogram creation circuit 20 for obtaining and storing the most frequently appearing color (the most frequently appearing color register 25) related to image data to be processed while creating an appearance color histogram related to the image data on an SRAM 23. The circuit 20 stores the frequency and color data in a frequency register 24 and a most frequently appearing color register 25, respectively, when writing the frequency exceeding a value on the frequency register 24 in the SRAM 23. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image processing apparatus having a function of performing image processing that requires the most frequently occurring color on image data, and an appearance color histogram creation circuit used as a component of such an image processing apparatus. .

  In image processing performed by an image processing apparatus such as a copier (an apparatus that processes image data to perform a target process), the appearance frequency distribution of each color in the processing target image data (hereinafter referred to as appearance) There are those that require a color histogram (for example, see Patent Document 1).

  If the CPU creates the appearance color histogram, it takes time. Therefore, a general image processing apparatus that performs image processing that requires the appearance color histogram (see, for example, Patent Document 2). ) Is equipped with hardware for creating an appearance color histogram (hereinafter referred to as an appearance color histogram creation circuit).

  However, since the appearance color histogram creation circuit mounted in the existing image processing apparatus is a circuit that can only create the appearance color histogram, the existing image processing apparatus has the most frequently appearing colors (most frequently appearing frequency). When image processing requiring high color) (only the most frequently occurring color or image processing requiring the most frequently occurring color and appearance color histogram) is to be executed, the CPU The apparatus is configured to read out a relatively large number (for example, 4096) of data (appearance frequency) in the appearance color histogram and specify the most frequently appearing color.

JP 7-85275 A JP 2002-369034 A

  Accordingly, an object of the present invention is to provide an image processing apparatus that does not require the CPU to perform processing for specifying the most frequently occurring color at the time of image processing that requires the most frequently occurring color, and to use such an image. An object of the present invention is to provide an appearance color histogram creation circuit capable of realizing a processing device.

  In order to solve the above problems, an appearance color histogram creation circuit according to the present invention includes an appearance color having a most frequently appearing color register to which an external circuit can perform read access, a frequency register, and a plurality of storage areas to which the external circuit can perform read access. For each color data in the histogram storage circuit and the processing target image data composed of a plurality of color data, the value stored in the storage area specified by the value of the color data in the appearance color histogram storage circuit is “1”. "A color data processing circuit that performs an increase process, and if the updated value after the increase is larger than the value stored in the frequency register, the most frequent color register, frequency Each register includes information indicating a storage area storing the update value, a color data processing circuit that performs processing for setting the update value, and a color data processing circuit. And a processing completion notification circuit for notifying the completion of the process to an external circuit, provided.

  That is, the appearance color histogram creation circuit of the present invention is a process for creating an appearance color histogram relating to processing target image data [by the color data processing circuit. For each color data, the process of increasing the value stored in the storage area specified by the value of the color data in the appearance color histogram storage circuit by “1” and the most frequently appearing color for the processing target image data [When the update value by the color data processing circuit is larger than the value stored in the frequency register, the update value is stored in the most frequent color register and the frequency register, respectively. In other words, the circuit has a circuit configuration in which the information indicating the storage area being stored and the process of setting the update value are performed in parallel. Therefore, if this appearance color histogram creation circuit is used, it is not necessary to cause the CPU to perform processing for specifying the most frequently occurring color at the time of image processing requiring the most frequently occurring color (requires the most frequently occurring color). An image processing apparatus / image processing apparatus according to claim 4 that completes image processing at a higher speed can be realized.

  The “color data” in the present invention is data indicating chromatic colors or achromatic colors. When the appearance color histogram creation circuit of the present invention is manufactured, such color data itself and the appearance color histogram memory are stored. The storage area on the circuit may have a 1: 1 correspondence, a color data group that satisfies a specific condition (e.g., each higher bit of R, G, B gradation values is equal), and an appearance color histogram The storage area on the storage circuit may correspond to 1: 1. The processing completion notification circuit, which is a component of the appearance color histogram creation circuit of the present invention, is connected to an external circuit. It may be a circuit that actively / actively notifies the completion of processing (a circuit that outputs an interrupt signal, etc.), and holds information that can be used to determine whether or not the processing is complete (one that can be read by an external circuit) It may be a circuit.

  A value stored in the second frequency register that is less than or equal to the value stored in the frequency register is added by adding a second frequent color register and a second frequency register to which the external circuit can perform read access. If the value is larger than the value, information indicating the storage area storing the updated value in the second frequent color register and the second frequency register, and color data for performing processing for setting the updated value, respectively. The appearance color histogram creation circuit of the present invention can also be manufactured by adopting the processing circuit. If the appearance color histogram creation circuit manufactured in this way is used, an image that can perform image processing that requires the second-most frequently occurring color (a color that can be specified from information in the second frequent color register) at high speed can be performed. A processing apparatus can be manufactured.

  In addition, when the appearance color histogram creation circuit of the present invention is the one in which the second frequent color register is added, the number of color data that has not been processed by the color data processing circuit is further monitored, When the number of color data matches the value obtained by subtracting the value on the second frequency register from the value on the recording frequency register, a stop control circuit for stopping the processing by the color data processing circuit can be added. If an appearance color histogram creation circuit having such a configuration is used, an image processing circuit capable of starting actual image processing requiring the most frequently occurring color in a shorter time can be manufactured.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

<< First Embodiment >>
First, the outline of the image processing apparatus 10 according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

  As shown in FIG. 1, the image processing apparatus 10 according to this embodiment is an apparatus that includes a scanner 11, an operation panel 12, a controller 13, and a print engine 14. The image processing apparatus 10 can be used without being connected to a PC (Personal Computer), but is usually used by connecting to several PCs via a network (and / or direct connection). It is a device (that is, a multifunction device having a function as a printer).

  An operation panel 12 provided in the image processing apparatus 10 according to the present embodiment is provided in the image processing apparatus 10 in order to obtain various instructions from the user (and to present the state of the image processing apparatus 10 to the user). Unit. The operation panel 12 is a unit composed of an LCD, a plurality of LEDs, a plurality of push button switches, and the like.

  The print engine 14 is a unit for performing color / monochrome printing on paper. The scanner 11 is a unit that generates image data (a set of color data relating to each pixel) of the original by scanning the original set on the scanner 11. The scanner 11 outputs image data including color data including 8-bit R gradation data, 8-bit G gradation data, and 8-bit B gradation data for each pixel.

  The controller 13 is a unit having the configuration shown in FIG. 2 for controlling each part in the image processing apparatus 10 in an integrated manner.

  The image processing apparatus 10 according to the present embodiment includes the configuration / function of the appearance color histogram creation circuit 20 (“creation circuit” in the drawing) in the memory control ASIC mounted on the controller 13, and the controller 13. Only the contents of the firmware on the ROM are different from the existing image processing apparatus (the image processing apparatus on which the image processing apparatus 10 is based).

  Based on the above, the configuration and operation of the image processing apparatus 10 according to the present embodiment will be described more specifically below.

  The appearance color histogram creation circuit 20 (the appearance color histogram creation circuit 20 in the memory control ASIC installed in the controller 13 of the image processing apparatus 10) used in the image processing apparatus 10 according to the present embodiment is shown in FIG. As shown, the circuit includes a data read / address conversion circuit 21, an SRAM control circuit 22, an SRAM 23, a frequency register 24, and a most frequent color register 25.

  The SRAM 23 provided in the appearance color histogram creation circuit 20 is an SRAM (SRAM that can specify a storage area to be read / written with a 12-bit address) having 4096 storage areas capable of storing data of one word. Both the frequency register 24 and the most frequent color register 25 are registers that can store data of one word (16 bits), and the appearance color histogram creation circuit 20 is data stored in the registers 23 and 24 and the SRAM 23. The circuit can be read by the CPU.

  The data read / address conversion circuit 21 includes a DMA transfer start address register, a DMA transfer data amount register, a start register, an interrupt necessity register, etc. (all of which are accessible by the CPU). The data reading / address converting circuit 21 is a zero clear circuit (FIG. 3) provided in the appearance color histogram creating circuit 20 when a predetermined value (“1” in the present embodiment) is written in the start register. The circuit that writes “0” to each storage area of the SRAM (not shown in FIG. 4) functions to clear all the storage areas of the SRAM 23 to “0”, and the frequency register 24 and the most frequent color register 25 are set to “0”. “After clearing processing,“ the number set in the DMA transfer data number register after the address set in the DMA transfer start address register on the SDRAM (see FIG. 2) (hereinafter referred to as DMA transfer data). 12-bit data (R, G, etc.) obtained by removing the lower 4 bit data of each color component Of on converted into data) that combines the upper four bits of the gradation data, sequentially, and has a circuit for starting the process "for the DMA transfer to the SRAM control circuit 22.

  Further, the data read / address conversion circuit 21 includes an untransferred data number register for managing (counting and storing) the number of untransferred data (= the number of DMA transfer data−the number of data for which DMA transfer has been completed). In this circuit, the value of the start register is returned to “0” when the value of the transfer data number register (number of untransferred data) becomes “0”. Further, when a predetermined value is set in the interrupt necessity register, the data read / address conversion circuit 21 outputs an interrupt signal when the number of untransferred data becomes “0” ( It is also a circuit that performs processing for changing the signal level of a specific terminal of the memory control ASIC.

  The SRAM control circuit 22 is a circuit that performs the processing shown in FIG. 4 every time 12-bit color data is input from the data read / address conversion circuit 21.

  That is, when color data is input, the SRAM control circuit 22 uses the color data as a target address (read or write address) to read the target address data RD on the SDRAM 23 (step S101), and RD 1 is added to the SDRAM 23 as the address data of interest (step S102). When color data is input, the WD and the data MFD stored in the frequency register 24 are stored. When the size relationship is determined (step S103) and WD> MFD is satisfied (step S103; YES), the WD and the address of interest (input color data) are respectively set in the frequency register 24 and the most frequently appearing color. The circuit is set in the register 25 (step S104). In the flowchart of FIG. 4, the process of step S104 is performed after the process of step S102 is completed, but the actual SDRAM control circuit 22 performs the process of step S104 almost simultaneously with the process of step S102. It has a circuit configuration to perform.

  When the image processing apparatus 10 according to the present embodiment performs image processing that requires the most frequently occurring color on image data (usually, image data generated by the scanner 11) on the SDRAM as firmware. When the CPU operates the appearance color histogram creation circuit 20 by performing various information settings and then receives an interrupt signal (or the value of the start register in the appearance color histogram creation circuit 20 is “0”). The data stored in the most frequently appearing color register 25 in the appearance color histogram creating circuit 20 (that is, the most frequently appearing color) is read out, and actual image processing is performed using the read data. The device is prepared (created) and used.

  As described above, the image processing apparatus 10 according to the first embodiment of the present invention processes image data (the data read / address conversion circuit 21 converts the data into 12 bits and supplies the color data to the SRAM control circuit 22. The apparatus includes an appearance color histogram creation circuit 20 that obtains the most frequently appearing color for the processing target image data while creating the appearance color histogram for the image data. The image processing apparatus 10 is an apparatus in which the CPU performs image processing using the most frequently occurring color (the value of the most frequently occurring color register 25) obtained by the appearance color histogram creating circuit 20, and therefore the image processing apparatus 10 Since the CPU does not perform the process of obtaining the most frequently occurring color from the appearance color histogram prepared by hardware, the image processing that requires the most frequently occurring color is completed earlier than the existing image processing apparatus. Will be.

<< Second Embodiment >>
The image processing apparatus according to the second embodiment of the present invention is an apparatus having the same hardware configuration (see FIGS. 1 and 2) as the image processing apparatus 10 according to the first embodiment of the present invention. However, the memory control ASIC implemented in the image processing apparatus according to the second embodiment includes the appearance color histogram creation circuit 30 having the configuration shown in FIG.

The SRAM 33 provided in the appearance color histogram creation circuit 30 is a memory having the same specification and the same application as the SRAM 23. The first frequency register 34 ₁ and the first frequent color register 35 ₁ are registers having the same specifications and uses as the frequency register 24 and the most frequent color register 25, respectively.

Second frequent color register 35 _2, the color appearance histogram creation circuit 30 operates, occurrence frequency large color data in the second (that of 12-bit length, hereinafter referred to as second frequent color) that is stored Is a register (which can store one word of data in this embodiment). Second frequency register 34 _2, the color appearance histogram creation circuit 30 operates, in the register (in this embodiment that the frequency of occurrence of the second frequent color (number of occurrences) is to be stored, capable of storing one word of data ).

The data read / address conversion circuit 31 is a circuit having the same function as the data read / address conversion circuit 21. However, the data read-address conversion circuit 31 is a predetermined value to start register (in this embodiment, "1") if is written, a second frequency register 34 ₂ and the second frequent color register 35 ₂ is also "0" It is a circuit to clear. Further, when a predetermined stop instruction signal is input from the stop control circuit 36 (details will be described later), the data read / address conversion circuit 31 stops the data DMA transfer process and sets the value of the start register to “0”. This is a circuit that stops the operation after performing the process of returning to the above and the process of outputting an interrupt signal.

  The SRAM control circuit 32 is a circuit that performs the processing shown in FIG. 6 every time 12-bit color data is input from the data read / address conversion circuit 31.

In other words, the SRAM control circuit 32 is a circuit that performs the same processing (steps S201 to S204) as that performed by the SRAM control circuit 22 when color data is input, and FD1 ≧ WD> FD2 is satisfied. If, WD, attention address (input color data), respectively, the second frequency register 34 _2, it has a circuit that performs processing (steps S205 and S206) to set the second frequent color register 35 _2. Incidentally, FD1, FD2 and, respectively, the first frequency register 34 value of _1, is that of the second frequency register 34 ₂ values.

  The SRAM control circuit 32 is also a circuit that terminates the operation when the stop instruction signal is input from the stop control circuit 36.

The stop control circuit 36 (FIG. 5) is untransmitted data number data read-address conversion circuit 31 is managed by RN, the first frequency register 34 ₁ value FD1, relationship for the second frequency register 34 ₂ values FD2 When “RN = FD1-FD2-1” is satisfied [that is, even if all the color data processed after that is the second frequent color data, the total number (FD2) of the second frequent color data is the current A circuit having a function of outputting the above stop instruction signal to the data read / address conversion circuit 31 and the SRAM control circuit 32 when it is determined that the total number of the first frequent color data (FD1) is not exceeded. is there. The stop control circuit 36 is a circuit that allows the CPU to specify whether to operate (output a stop instruction signal).

  In short, the appearance color histogram creation circuit 30 included in the image processing apparatus according to the present embodiment can create an accurate appearance color histogram when the stop control circuit 36 is not operated, and also obtains the second frequent color. When the stop control circuit 36 is operated, the appearance color histogram (data group on the SRAM 33) to be created is not accurate, but the first frequent color is shortened in a shorter time. It functions as a circuit that can be obtained by

  Since the image processing apparatus according to this embodiment is an apparatus including such an appearance color histogram creation circuit 30, the CPU stops when performing image processing that requires only the most frequently occurring colors. When the appearance color histogram creation circuit 30 is operated in a state in which the control circuit 36 is operating, and when performing image processing that requires an accurate appearance color histogram or the second frequent color, the CPU controls the stop control circuit 36. Thus, the firmware is created so that the appearance color histogram creation circuit 30 is operated in a state in which the device does not operate.

  Therefore, in the image processing apparatus according to the second embodiment of the present invention, image processing that requires only the most frequently occurring color (processing that does not require an accurate appearance color histogram) is performed by the image processing apparatus 10 according to the first embodiment. It can be said that the apparatus completes earlier than the image processing apparatus 10 according to the first embodiment, and the image processing that requires the second frequent color is also completed.

<< Third Embodiment >>
The image processing apparatus according to the third embodiment of the present invention is a modification of the image processing apparatus according to the second embodiment of the present invention. For this reason, hereinafter, the same reference numerals as those used in the description of the second embodiment are used, and the image processing according to the third embodiment of the present invention will be focused on the parts different from the image processing apparatus according to the second embodiment. The configuration and operation of the device will be described.

Third according to an embodiment the image processing apparatus has color appearance histogram creation circuit 30 used in the (circuit on the memory control ASIC) is a circuit that does not include a second frequent color register 35 ₂ and the second frequency register 34 ₂ . Furthermore, color appearance histogram creation circuit 30 according to the third embodiment, as an SRAM control circuit 32, step S205, processing is not performed circuitry S206 is used, the stop control circuit 36, a first frequency register 34 the value of ₁ This circuit uses a circuit that outputs a stop instruction signal when FD1 exceeds 1/2 of the number of DMA transfer data managed by the data read / address conversion circuit 31.

  In short, the appearance color histogram creation circuit included in the image processing apparatus according to the present embodiment functions as a circuit that can create an accurate appearance color histogram when the stop control circuit 36 is not operated. When it is operated, the generated appearance color histogram (data group on the SRAM 33) is not accurate, but functions as a circuit that can obtain the first frequent color in a shorter time. Yes.

  Since the image processing apparatus according to this embodiment is an apparatus including such an appearance color histogram creation circuit, the CPU performs stop control when performing image processing that requires only the most frequently occurring colors. When the appearance color histogram creation circuit 30 is operated in a state where the circuit 36 is operating, and when performing image processing that requires an accurate appearance color histogram, the CPU appears in a state where the stop control circuit 36 is not operating. The firmware is created so that the color histogram creation circuit 30 is operated.

  Therefore, in the image processing apparatus according to the third embodiment of the present invention, image processing that requires only the most frequently occurring color (processing that does not require an accurate appearance color histogram) is performed by the image processing apparatus 10 according to the first embodiment. It can be said that the device is completed as soon as possible.

<Deformation>
The image processing apparatus and the appearance color histogram creation circuit according to each embodiment described above can perform various modifications. For example, the appearance color histogram creation circuits 20 and 30 described above are transformed into a circuit for creating an appearance color (in this case, achromatic color) histogram related to monochrome multi-tone image data, and the image processing apparatus according to each embodiment is changed to a monochrome image. It can be transformed into a multifunction device. In addition, the appearance color histogram creation circuit 30 can be modified to a circuit that can obtain frequent colors up to the N (> 2) th appearance frequency.

  Although the above-described image processing apparatus is a so-called multi-function machine, the appearance color histogram creation circuits 20 and 30 can be used for any apparatus that performs image processing. Accordingly, it is a matter of course that an image processing apparatus (digital camera, scanner, video data processing apparatus, etc.) other than the multifunction machine may be realized using the above technique.

1 is a configuration diagram of an image processing apparatus according to a first embodiment of the present invention. 1 is a configuration diagram of a controller included in an image processing apparatus according to a first embodiment. FIG. 3 is a configuration diagram of an appearance color histogram creation circuit included in a memory control ASIC used in the image processing apparatus according to the first embodiment. 6 is a flowchart for explaining the function of the SRAM control circuit in the appearance color histogram creation circuit according to the first embodiment; The block diagram of the appearance color histogram creation circuit with which the memory control ASIC used for the image processing apparatus which concerns on 2nd Embodiment of this invention is provided. 9 is a flowchart for explaining functions of an SRAM control circuit in an appearance color histogram creation circuit according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Image processing apparatus, 11 Scanner, 12 Operation panel 13 Controller, 14 Print engine 20, 30 Appearance color histogram creation circuit 21, 31 Data reading / address conversion circuit 22, 32 SRAM control circuit, 23, 33 SRAM
24 frequency register, 25 most frequent color register 34 ₁ first frequency register, 34 ₂ second frequency register 35 ₁ first frequent color register, 35 ₂ second frequent color register, 36 stop control circuit

Claims (4)

The most frequent color register that can be read by an external circuit;
A frequency register;
An appearance color histogram storage circuit having a plurality of storage areas to which an external circuit can perform read access;
Processing for incrementing the value stored in the storage area specified by the value of the color data in the appearance color histogram storage circuit for each color data in the processing target image data composed of a plurality of color data. In the color data processing circuit that performs the above, when the updated value that is the increased value is larger than the value stored in the frequency register, the most frequent color register, the frequency Information indicating the storage area storing the update value in the register, a color data processing circuit for performing processing for setting the update value, and
An appearance color histogram creation circuit comprising: a processing completion notification circuit for notifying an external circuit of completion of processing by the color data processing circuit. A second frequent color register from which an external circuit can perform read access;
A second frequency register, and
The color data processing circuit is
If the updated value is less than the value stored in the frequency register and greater than the value stored in the second frequency register, the second frequent color register, the second frequency The appearance color histogram creation circuit according to claim 1, wherein each register is a circuit that performs processing for setting information indicating the storage area storing the update value and the update value. When the number of color data that has not been processed by the color data processing circuit is monitored and the number of color data matches the value obtained by subtracting the value on the second frequency register from the value on the recording frequency register, The appearance color histogram creation circuit according to claim 2, further comprising: a stop control circuit that stops processing by the color data processing circuit. An appearance color histogram creation circuit according to any one of claims 1 to 3,
Image processing means for performing image processing that requires information on the most frequently appearing color register in the appearance color histogram creation circuit on the processing target image data that has been processed by the appearance color histogram creation circuit; An image processing apparatus comprising:

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