JP2009207014A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processing apparatus capable of easily adding and changing image processing functions. <P>SOLUTION: Image data read by a scanner 2 is transferred to an image processing chip 4 via a system bus 7. The image processing chip 4 stores the image data received from the scanner 2 in an image memory 9 controlled by the chip itself, according to instruction from SoC 3 (in path 30). The image data stored in the image memory 9 is subjected to image processing by the image processing chip 4, the image processing being instructed in advance by SoC 3, and after the image processing is completed, the image data is transferred to an HDD controller in an I/O chip 5 via the system bus 7, and the I/O chip 5 stores the image data received from the image processing chip 4 via the system bus 7 in an HDD 11 (in path 31). The I/O chip 5 transfers the image data stored in the HDD 11 to a print engine 6, so that it is outputted and printed (in path 32). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an image processing apparatus including an image processing unit that performs image processing for printing and a graphic processing unit that performs image processing for image display.

  In digital multi-function peripherals equipped with a scanner function, a print function, a facsimile function, and the like, the amount of data and the processing speed that must be processed continue to increase day by day with the demand for higher speed, higher resolution, and higher functionality. In order to satisfy such requirements, the hardware configuration of the digital multifunction peripheral is configured by providing a plurality of dedicated ASICs (Application Specific Integrated Circuits) specialized for the digital multifunction peripheral to improve the performance of the entire multifunction peripheral. It is normal to plan.

  ASICs are advantageous in terms of processing speed, scale, and cost compared to FPGAs (Field Programmable Gate Arrays) that can change the circuit configuration in a programmable manner, but they cannot be changed easily once they are completed. You must pay attention to design, verify, and develop.

  However, as long as they are created by humans, problems such as bugs always occur and cannot be completely avoided. If a problem occurs, unless it can be solved by hardware, it can only be avoided by changing the control method with firmware. If that is still not possible, recreate the ASIC at high cost and time. There is a need.

  In addition, since digital multifunction peripherals have high functions and multiple functions, their operations may be complicated, and improvements in user interfaces that are easier to operate are required. For example, operability can be improved by providing a pointing device such as a touch panel as an input device and adopting a GUI (Graphical User Interface). A liquid crystal display and an organic EL (electro-luminescence) display are combined with the touch panel, and input is performed using software keys. For this reason, a digital multi-function peripheral needs a circuit configuration for performing image processing of a user interface display, and if it can display an animation, a graphic chip having a more advanced image processing function is required.

  The display device described in Patent Document 1 forms image data for each video component by arithmetic processing in the GPU, and stores the image data formed in the storage circuit of the corresponding pixel. The stored image data is synthesized by the processing circuit of each pixel and converted into a video signal by the display processing circuit.

JP 2003-167558 A

  If a problem occurs in an ASIC for image processing among ASICs mounted on a digital multi-function peripheral, the function of the entire apparatus is lowered, which becomes an important problem.

  An object of the present invention is to provide an image processing apparatus capable of easily adding or changing an image processing function.

The present invention includes a main control unit that controls the operation of the entire apparatus,
An image processing unit for performing image processing for printing;
A graphic processing unit for performing image processing for image display,
The graphic processing unit is configured to be capable of executing the image display image processing and a part of the printing image processing in parallel.

  In addition, the invention is characterized in that a part of the printing image processing is processing further added to processing to be performed by the image processing unit.

  In addition, the invention is characterized in that a part of the printing image processing is processing for solving problems of processing to be performed by the image processing unit.

The present invention also includes an external storage device interface unit that controls transmission / reception of image data to / from an external storage device,
The external storage device interface unit and the graphic processing unit are configured in the same semiconductor chip.

  According to the present invention, the main control unit is configured to be able to change the execution order of the image processing for printing performed by instructing the image processing unit and the graphic processing unit, respectively. .

The present invention also includes a main control unit that controls the operation of the entire apparatus,
An image processing unit that performs image processing for printing,
The main control unit is configured to be able to execute control of the entire apparatus and a part of the printing image processing in parallel.

The present invention also includes an external storage device interface unit that controls transmission / reception of image data to / from an external storage device,
The external storage device interface unit and the main control unit are configured in the same semiconductor chip.

  Further, the present invention is characterized in that the main control unit is configured to be able to change the execution order of the printing image processing performed by instructing the image processing unit and the main control unit itself. .

  According to the present invention, the graphic processing unit is configured to be able to execute the image display image processing and a part of the printing image processing in parallel.

  According to the present invention, part of the printing image processing is processing that is further added to the processing to be performed by the image processing unit.

  According to the invention, part of the processing for image processing for printing is processing for solving a problem of processing to be performed by the image processing unit.

  Thereby, for example, it is possible to easily execute a process for adding a new function or solving a defect such as a bug.

  In addition, according to the present invention, the external storage device interface unit that controls transmission / reception of image data with the external storage device is provided, and the external storage device interface unit and the graphic processing unit are configured in the same semiconductor chip.

  Thereby, the image data can be transferred efficiently, and the processing speed can be improved.

  According to the invention, the main control unit can change the execution order of the image processing for printing performed by instructing the image processing unit and the graphic processing unit, respectively.

  Accordingly, the graphic processing unit can efficiently execute a part of the printing image processing.

  Further, according to the present invention, the main control unit is configured to be able to execute the control of the entire apparatus and a part of the printing image processing in parallel.

  Thereby, for example, it is possible to easily execute a process for adding a new function or solving a defect such as a bug.

  In addition, according to the present invention, the external storage device interface unit that controls transmission / reception of image data with the external storage device is provided, and the external storage device interface unit and the main control unit are configured in the same semiconductor chip.

  Thereby, the image data can be transferred efficiently, and the processing speed can be improved.

  According to the invention, the main control unit can change the execution order of the image processing for printing performed by instructing the image processing unit and the main control unit itself.

  Accordingly, the main control unit can efficiently execute a part of the printing image processing.

  FIG. 1 is a block diagram showing a configuration of an image processing apparatus 1 according to an embodiment of the present invention. The image processing apparatus 1 includes an SoC (System On a Chip) 3 that is a main control unit, an image processing chip 4 that is an image processing unit, an I / O (Input / Output) chip 5, a print engine 6, and a system. It consists of bus 7.

  The scanner 2 is connected to the image processing apparatus 1 and performs reading of a document image and image processing such as shading and light amount correction.

  The SoC 3 is a main control unit that controls the image processing apparatus 1 using the main memory 8 as a work memory area.

  The image processing chip 4 performs image processing on image data received from the scanner 2 or an external personal computer (hereinafter referred to as “PC (Personal Computer)”). A processing unit, a color correction unit, a black generation and under color removal unit, a spatial filter processing unit, an output tone correction unit, a color / monochrome conversion unit, an image compression process, an image decompression process, and a rotation processing unit are included. As the image processing chip 4, a dedicated ASIC (Application Specific Integrated Circuit) developed exclusively for image processing or a general-purpose IC (Integrated Circuit) having an image processing function is generally used. The image processing chip 4 can store the received image data in the image memory 9 controlled by the image processing chip 4 according to an instruction from the SoC 3 serving as the main control unit, and can perform image processing.

  The I / O chip 5 performs an interface with an external device. As an example, the I / O chip 5 includes a GPU (Graphics Processing Unit) 23 having an LCDC (Liquid Crystal Display Controller) function for displaying a user interface. Calculation processing necessary for displaying 3D graphics is performed. It also has an HDD (Hard disk drive) controller and NIC (Network Interface Card). The I / O chip 5 stores the received image data in the LCDC memory 10 or HDD 11 controlled by itself.

  The I / O chip 5 can also transmit and receive data to and from an external device via a LAN (Local Area Network) 12. The I / O chip 5 generally has not only the LAN 12 but also several types of external interfaces such as a facsimile machine and a USB (Universal Serial Bus), and realizes not only a copying operation but also a printing operation and a facsimile operation. It becomes possible.

The print engine 6 receives the data after image processing and executes print processing.
The system bus 7 is configured by a general-purpose system bus such as PCI (Peripheral Component Interconnect), PCI-Express, and a dedicated bus, and is used for internal transmission and reception of control data and image data.

  FIG. 2 is a block diagram showing the configuration of the I / O chip 5. The I / O chip 5 includes a system bus I / F (Interface) 21, a local bus I / F 22, a GPU 23, an HDD I / F 24, a network I / F 25, and an LCDC memory I / F 26.

  The system bus I / F 21 is a block that controls transmission and reception of image data and the like with each IC.

  The local bus I / F 22 is a block that controls the operation of the I / O chip 5 by communicating with the SoC 3. Connected to the local bus 27 directly connected to the SoC 3, and controls the I / O chip 5 in accordance with an instruction from the SoC 3.

  The GPU 23 performs liquid crystal display display and image processing of image data to be displayed. The LCDC memory I / F 26 includes a memory control function for providing the LCDC memory 10 for storing image data in order to perform liquid crystal display display.

  The HDD I / F 24 has an HDD controller function and an interface function. The network I / F 25 transmits / receives data to / from an external device via the LAN 12.

  It may be configured with multiple ICs, such as when the system configuration is different and multiple image processing chips that perform different processing are installed, or when the I / O chip function is divided to make the GPU function independent. It is done.

  FIG. 3 is a diagram showing the flow of image data during the copy operation, superimposed on the block diagram of FIG. The image processing will be described by taking a copy operation of the image processing apparatus 1 as an example.

  When a copy button provided in the user interface is pressed by a user operation, the scanner 2 reads the document placed on the document table, converts the analog image data into digital image data, and then passes through the system bus 7 to the image processing chip. 4, the image processing chip 4 stores the image data received from the scanner 2 in the image memory 9 controlled by the image processing chip 4 according to an instruction from the SoC 3 (path 30).

  The image data stored in the image memory 9 is processed in advance by the image processing chip 4 after image processing instructed by the SoC 3, and after completion of the image processing, the system bus is connected to an HDD controller (not shown) in the I / O chip 5. 7, and the I / O chip 5 stores the image data received from the image processing chip 4 via the system bus 7 in the HDD 11 (path 31).

  The I / O chip 5 transfers the image data stored in the HDD 11 to the print engine 6 for printing out (path 32).

  The print engine 6 receives image data from the I / O chip 5 and executes a printing operation on a recording medium. At this time, the SoC 3 controls the I / O chip 5 and the print engine 6.

  As an example of operations other than the copy operation, there is a print operation for outputting data received from an external device. In this case, since image data is transferred via the LAN 12, the image data input path is an example of a copy operation. Unlike the path 30 in FIG. 3, the image data is transferred from the I / O chip 5 to the image processing chip 4 via the system bus 7, and the image processing chip 4 is transferred from the I / O chip 5 according to an instruction from the SoC 3. The received image data is stored in the image memory 9 controlled by itself (path 33).

  Subsequent transfer of image data, image processing, and the like are the same as in the case of copy difference. However, the detailed contents of the image processing differ depending on the type of input image data.

  FIG. 4 is a diagram showing the flow of image data in the I / O chip 5 superimposed on the block diagram of FIG.

  In the case of the data transfer paths of the path 31 and the path 32 shown in FIG. 3, the exchange between the HDD I / F 24 and the system bus I / F 21 is performed in the I / O chip 5 as indicated by the path 40.

  During a write operation to the HDD 11, image data input from the system bus I / F 21 is transferred to the HDD I / F 24 via the internal bus of the I / O chip 5. The HDD I / F 24 stores the received data in the HDD 11 that is an external storage device. During a read operation from the HDD 11, image data read from the HDD 11 is transferred to the system bus I / F 21 via the internal bus of the I / O chip 5. The system bus I / F 21 outputs the received image data from the system bus to the outside of the I / O chip 5.

  Next, a flow of transferring image data to be displayed on the LCD 28 as a display device will be described.

  A path 41 is a flow when the SoC 3 reads / writes image data from the LCDC memory 10, a path 42 is a flow when the GPU 23 reads / writes image data from the LCDC memory 10, and a path 43 is This is a flow of transferring image data to be displayed on the LCD 28 by the LCDC memory I / F 26.

  The transfer of these image data occurs in order to rewrite the image data displayed on the LCD 28. Therefore, it is processed independently from the transfer of image data generated in the copying operation.

  The internal bus of the I / O chip 5 may be configured with two independent internal buses in order to improve the transfer performance of the image data transferred by the copy operation and the image data transferred by the LCD display operation. It is done.

  Now, the GPU 23 used for LCD display operation and the like and realizing graphics image processing has been improved in high-speed frequency operation and high functionality, and can be selected from those having very wide performance. A high-speed, high-performance GPU can realize advanced image processing by creating a firmware program. By enabling image processing to be executed by such a high-performance GPU, in addition to image processing executed by the image processing chip 4, other image processing is performed, or image processing executed by the image processing chip 4 is performed. It becomes possible to take over a part of and help.

  For example, when it is necessary to improve the function of image processing after the completion of a product whose circuit configuration is determined for each IC chip, the image processing chip 4 is configured with an ASIC that is advantageous in terms of cost and speed as described above. Therefore, it is very difficult to add or change a function that is not implemented in advance as a function.

  Accordingly, in such a case, if the image processing chip 4 is configured so that the image processing can be further executed by the GPU 23 after the image processing to be performed by the image processing chip 4 is completed, the function of the image processing can be improved. . Of course, the GPU 23 has a lower image processing speed than an ASIC dedicated to image processing. Therefore, even if the function can be improved, the processing speed and image data transfer capability of the entire apparatus are reduced. As a result, the function of the entire apparatus is reduced, and it is also necessary to satisfy the processing speed and image data transfer capability of the entire apparatus. In order to satisfy the image processing speed and the image data transfer capability, it is desirable that the GPU 23, the HDD I / F 24, and the LCDC memory I / F 26 are configured in the same IC chip as shown in FIG. . In addition, as long as the configuration satisfies the processing speed and image data transfer capability of the entire device, the configuration may be such that these functions are divided into independent IC chips.

  Further, the GPU 23 is used not only for improving the function by adding functions as described above, but also when a defect is detected in a part of the image processing after the image processing chip 4 is manufactured and it is necessary to correct it. Can do. In such a case, with respect to a part of the processing in which a problem has occurred in the image processing chip 4, the GPU 23 can take over the part of the process instead and perform a substitute process to solve the problem.

  Regardless of whether a further function is added or a problem is solved, the image processing executed by the GPU 23 is performed before or after the completion of the image processing flow to be executed by the image processing chip 4 and in the middle of the image processing flow. It is assumed that this must be done.

Hereinafter, the flow of image data will be described for each case.
In the first embodiment, FIG. 5 shows a flow of image data when additional image processing is performed by the GPU 23 after execution of image processing to be performed by the image processing chip 4 is completed. The image processing added by the GPU 23 may be processing for further adding a function, or processing for eliminating a problem of image processing to be performed by the image processing chip 4.

  Since the path 30 and the path 32 shown in FIG. 3 are pre-processing and post-processing rather than the image processing flow, they are omitted in the description of FIG.

  When the image processing to be performed by the image processing chip 4 is completed, the image processing chip 4 transfers the image data to the I / O chip 5 via the system bus 7 (path 50). Normally, image data that has been subjected to image processing is directly stored in the HDD 11 as in the path 31 shown in FIG. 3, but is transferred from the image processing chip 4 in order to perform additional image processing in the GPU 23. The image data is stored in the LCDC memory 10. Thereafter, additional image processing is performed by the GPU 23 and then stored in the HDD 11 (path 51).

  FIG. 6 is a diagram for explaining in detail processing inside the I / O chip 5 in the first embodiment. Image data for which image processing to be performed by the image processing chip 4 has been completed is stored in the path 60 from the system bus I / F 21 to the LCDC memory 10 via the internal bus and the LCDC memory I / F 26. The stored image data is sequentially read from the LCDC memory 10 via the internal bus in order to execute additional image processing by the GPU 23, and after the additional image processing is executed by the GPU 23, the LCDC is transmitted via the internal bus. Returned to the memory 10 (path 61).

  In order to share the LCDC memory 10, the image data is transferred while communicating the processing status between the LCDC memory I / F 26 and the GPU 23. Since the image data that has undergone image processing in the GPU 23 has been subjected to all necessary image processing, the image data is stored in the HDD 11 via the path 62 and a series of processing is completed.

  In the second embodiment, FIG. 7 shows a flow of image data when additional image processing is temporarily performed by the GPU 23 while image processing to be performed by the image processing chip 4 is being performed.

  The image processing added by the GPU 23 may be processing for further adding a function, or processing for eliminating a problem of image processing to be performed by the image processing chip 4.

  When the image processing up to the step to be processed in advance by the image processing chip 4 is completed, the image processing chip 4 transfers the image data in the image memory 9 to the I / O chip 5 via the system bus 7 (path). 70). Normally, the image data that has been subjected to image processing is directly stored in the HDD 11 as in the path 31 shown in FIG. 3, but the image transferred from the image processing chip 4 in order to perform additional image processing in the GPU 23. Data is stored in the LCDC memory 11. Thereafter, after additional image processing is performed by the GPU 23, the image data is transferred again to the image memory 9 (path 71). The image processing chip 4 that has received the image data performs the remaining image processing and transfers the image data to the I / O chip 5 again. At this time, since all image processing to be performed is completed, it is stored in the HDD 11 (path 72).

  FIG. 8 is a diagram for explaining in detail processing inside the I / O chip 5 in the second embodiment. When the image processing up to the step to be processed in advance by the image processing chip 4 is completed, the image data is stored in the LCDC memory 10 via the internal bus and the LCDC memory I / F 26 via the path 80. The stored image data is sequentially read out from the LCDC memory in order to execute additional image processing in the GPU 23, and after the additional image processing is executed in the GPU 23, it is returned to the LCDC memory 10 through the internal bus. (Path 81). In order to share the LCDC memory 10, the image data is transferred while communicating the processing status between the LCDC memory I / F 26 and the GPU 23. The image data that has undergone the additional image processing in the GPU 23 is transferred through the path 80 in order to perform the remaining image processing in the image processing chip 4 again. The image data for which the remaining image processing has been completed by the image processing chip 4 is stored in the HDD 11 via the path 82, and a series of processing is completed.

  The third embodiment is a case where additional image processing is performed by the GPU 23 before executing image processing to be performed by the image processing chip 4, and the flow of the image data is shown in FIG. The image processing added by the GPU 23 may be processing for further adding a function, or processing for eliminating a problem of image processing to be performed by the image processing chip 4.

  When a copy button provided in the user interface is pressed by a user operation, the scanner 2 reads the document placed on the document table, converts it from analog image data to digital image data, and then performs I / O via the system bus 7. While transferring the image data to the chip 5, the IO chip 5 stores the image data received from the scanner 2 in the LCDC memory 10 controlled by the IO chip 5 in accordance with an instruction from the SoC 3 (path 90).

  After performing the additional image processing by the GPU 23, the I / O chip 5 transfers the image data subjected to the additional image processing to the image processing chip 4 via the system bus 7, and the image processing chip 4 Data is stored in the image memory 9 controlled by itself (path 91).

  When the image processing chip 4 completes the image processing to be performed by the image processing chip 4, the image processing chip 4 transfers the image data to the I / O chip 5. At this time, since all image processing to be performed is completed, it is stored in the HDD 11 (path 92).

  FIG. 10 is a diagram for explaining in detail the processing inside the I / O chip 5 in the third embodiment.

  The image data read by the scanner 2 is stored on the path 100 from the system bus I / F 21 to the LCDC memory 10 via the internal bus and the LCDC memory I / F 26. The stored image data is sequentially read from the LCDC memory 10 via the internal bus in order to execute additional image processing by the GPU 23, and after the additional image processing is executed by the GPU 23, the LCDC is transmitted via the internal bus. Returned to the memory 10 (path 101).

  In order to share the LCDC memory 10, the image data is transferred while communicating the processing status between the LCDC memory I / F 26 and the GPU 23. The image data that has undergone the additional image processing in the GPU 23 is transferred through the path 100 in order to perform image processing to be performed by the image processing chip 4. Since the image data that has undergone image processing to be performed by the image processing chip 4 has been subjected to all necessary image processing, it is stored in the HDD 11 via the path 102 and a series of processing is completed.

  Further, as with the GPU 23, as represented by SoC3, in recent years, high-frequency operation and advanced functions have advanced, and the CPU can be selected from those having a very wide range of performance. When a high-speed and high-function SoC 3 is used, advanced image processing can be realized by creating a firmware program. By executing image processing with such a high-function SoC, it is possible to add image processing functions and solve problems with the image processing ASIC as in the image processing system using the GPU 23. In other words, when the GPU 23 performs image processing, the image processing of LCD display image data and the image processing of document image data are performed in parallel. However, when the SoC 3 performs image processing, the image processing device 1 The overall control and image processing of document image data are performed in parallel.

  As in the case of the GPU 23, when image processing is performed with the SoC 3, the configuration having the HDD I / F 24 in the SoC 3 is an effective means for improving the performance. However, if the entire apparatus is satisfied, the HDD I / F 24 in the SoC 3 is satisfactory. It is not always necessary to have Since it can be implemented in the same manner as using the GPU 23, it is not shown in the figure. However, in the case of performing some image processing that should be performed by the image processing chip 4 with the SoC 3, the image processing chip 4 is used. Either a configuration in which additional image processing is performed after completion of power image processing or a configuration in which additional image processing is performed during image processing can be supported, and the order of image processing is determined by an instruction from the SoC 3.

  FIG. 11 is a flowchart showing image processing of the image processing apparatus 1. As an example, a flow of the first embodiment in which additional image processing is performed by the GPU 23 after completion of image processing to be performed by the image processing chip 4 is shown.

  First, in step S1, the SoC 3 recognizes the start of the print section job. Specifically, it recognizes the start of a print job (copy job) of image data read by a scanner or a print job (print job) of image data received from an external device, and starts it from an external device such as a PC via a network. May be activated from the user interface via the input device.

  In step S2, SoC 3 instructs the operation setting of each part. The operation setting instruction for each part is performed by registering the operation method for each part. As the contents of the operation setting, for example, the type of image processing to be executed, the order thereof, and the processing size are instructed.

  In step S3, the SoC instructs each part to start image processing. Actually, the print engine 6, the I / O chip 5, and the image processing chip 4 are activated in this order because they are activated sequentially from the downstream side of the image data flow.

In step S4, each part performs image processing based on the instructed operation setting.
In step S5, when a processing completion notification is received from the print engine 6 after the SoC 3 has finished the final printing process, the end of a series of jobs is recognized.

1 is a block diagram illustrating a configuration of an image processing apparatus 1 according to an embodiment of the present invention. 2 is a block diagram showing a configuration of an I / O chip 5. FIG. FIG. 2 is a diagram showing a flow of image data during a copy operation, superimposed on the block diagram of FIG. 1. FIG. 3 is a diagram showing the flow of image data in the I / O chip 5 superimposed on the block diagram of FIG. 2. It is a figure which shows the flow of the image data in the case of performing additional image processing with GPU23 after execution completion of image processing with the image processing chip 4. FIG. It is a figure for demonstrating in detail the process inside the I / O chip | tip 5 in 1st Embodiment. It is a figure which shows the flow of the image data in the case of performing additional image processing by GPU23 temporarily in the middle of performing the image processing which should be performed by the image processing chip. It is a figure for demonstrating in detail the process inside the I / O chip | tip 5 in 2nd Embodiment. It is a figure which shows the flow of the image data in the case of performing an additional image process by GPU23 temporarily before performing the image process which should be performed by the image processing chip. It is a figure for demonstrating in detail the process inside the I / O chip | tip 5 in 3rd Embodiment. 3 is a flowchart showing image processing of the image processing apparatus 1.

Explanation of symbols

1 Image processing device 2 Scanner 3 SoC
4 Image processing chip 5 I / O chip 6 Print engine 7 System bus 8 Main memory 9 Image memory 10 LCDC memory 11 HDD
21 System bus I / F
22 Local bus I / F
23 GPU
24 HDD I / F
25 Network I / F
26 LCDC memory I / F

Claims (8)

A main control unit that controls the operation of the entire apparatus;
An image processing unit for performing image processing for printing;
A graphic processing unit for performing image processing for image display,
The image processing apparatus, wherein the graphic processing unit is configured to execute the image display image processing and a part of the print image processing in parallel.   The image processing apparatus according to claim 1, wherein a part of the printing image processing is processing further added to processing to be performed by the image processing unit.   The image processing apparatus according to claim 1, wherein a part of the image processing for printing is a process for solving a problem of a process to be performed by the image processing unit. An external storage device interface unit for controlling transmission and reception of image data with the external storage device;
The image processing apparatus according to claim 1, wherein the external storage device interface unit and the graphic processing unit are configured in the same semiconductor chip.   2. The main control unit is configured to be able to change an execution order of image processing for printing performed by instructing the image processing unit and the graphic processing unit, respectively. Image processing apparatus. A main control unit that controls the operation of the entire apparatus;
An image processing unit that performs image processing for printing,
An image processing apparatus, wherein the main control unit is configured to be able to execute control of the entire apparatus and a part of the printing image processing in parallel. An external storage device interface unit for controlling transmission and reception of image data with the external storage device;
The image processing apparatus according to claim 6, wherein the external storage device interface unit and the main control unit are configured in the same semiconductor chip.   The said main control part is comprised so that change of the execution order of the image processing for printing each performed by instruct | indicating to the said image processing part and the main control part itself is characterized by the above-mentioned. Image processing apparatus.

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