JP2009033520A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up a signal reading operation while obtaining difference between an optical output signal and a dark output signal. <P>SOLUTION: Every three storage capacitors C1-C3 are provided according to the respective vertical signal lines 14. A signal in which dark output signals of two selected pixels 11 are superimposed is accumulated in the capacitor C1, a signal corresponding to a signal in which a dark output signal of one of the two selected pixels 11 and an optical output signal of the other pixel are superimposed is accumulated in the capacitor C2, and a signal corresponding to a signal in which optical output signals of the two selected pixels 11 are superimposed is accumulated in the capacitor C3 via switches TV1-TV3. The respective signals accumulated in the capacitors C1-C3 are supplied to horizontal signal lines 16-1 to 16-3 via switches TH1-TH3, respectively, and output via amplifiers AP1-AP3. An external control part obtains difference between output signals of the amplifiers AP1, AP2 and difference between output signals of the amplifiers AP2, AP3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  In a video camera, an electronic still camera, and the like, a CCD type or amplification type solid-state imaging device is used. In such a solid-state imaging device, a plurality of pixels each having a photoelectric conversion unit are arranged in a matrix, and signal charges are generated by the photoelectric conversion unit of each pixel. In the amplification type solid-state imaging device, the signal charge generated and accumulated in the photoelectric conversion unit of the pixel is led to a charge-voltage conversion unit such as a floating diffusion, and the signal charge is converted into a voltage by the charge-voltage conversion unit. The signal is output from the pixel by an amplifier provided in the pixel.

  In such an XY address type solid-state image pickup device such as an amplification type solid-state image pickup device, generally, a vertical signal provided corresponding to each column of a plurality of pixels and supplied with an output signal of a pixel in the corresponding column. A light output signal storage capacitor and a dark output signal storage capacitor provided corresponding to each vertical signal line, and a light output signal from the pixel (a pixel output signal including light information photoelectrically converted by the pixel). ) Is stored in the optical output signal storage capacitor via the vertical signal line, and the dark output signal from the pixel (the pixel output signal not including the optical information) is darkened via the vertical signal line. A dark output signal sampling switch for storing in the output signal storage capacitor, a light output signal horizontal transfer switch for transferring the light output signal stored in the light output signal storage capacitor to the light output signal horizontal signal line, output And a, a horizontal transfer switch dark output signal for transferring the dark output signal stored in the issue for the storage capacitor to the horizontal signal line dark output signal.

  In such a solid-state imaging device, pixels are selected row by row, and the dark output signal and the light output signal of the pixels in the selected row are sequentially stored in the dark output signal storage capacitor and the light output signal storage capacitor, respectively. The dark output signal and the optical output signal stored in the dark output signal storage capacitor and the optical output signal storage capacitor in the horizontal scanning period of the selected row are the dark output signal horizontal transfer switch and the optical output signal horizontal transfer, respectively. The signals are transferred to the dark output signal horizontal signal line and the optical output signal horizontal signal line by the switch.

  And as such a solid-state imaging device, the difference between the dark output signal of the horizontal signal line for dark output signals and the optical output signal of the horizontal signal line for optical output signals is provided in the solid-state imaging device. A differential amplifier or the like that outputs the difference signal to the outside, and the dark output signal of the horizontal signal line for dark output signal and the optical output signal of the horizontal signal line for light output signal in parallel with each other in parallel. It is known that the signal is output to the outside of the image sensor and the difference between both signals is obtained by an external circuit or the like. As an example of the latter, the solid-state imaging device disclosed in Patent Document 1 below can be cited.

According to such a solid-state imaging device, since the difference between the light output signal and the dark output signal can be obtained, noise such as so-called fixed pattern noise is removed, and the image quality is improved.
Japanese Patent Laid-Open No. 1-154678

  However, in a conventional solid-state imaging device as disclosed in Patent Document 1, pixels are selected row by row, and dark output signals and light output signals of pixels in the selected rows are sequentially stored in dark output signal storage capacitors and light outputs. Each of these must be stored in the signal storage capacitor, and it takes a relatively long time to sample the light output signal and the dark output signal from the pixel, and the horizontal scanning period also becomes long. Could not do.

  An object of the present invention is to provide a solid-state imaging device capable of speeding up a signal reading operation even though a difference between a light output signal and a dark output signal can be substantially obtained. .

  As a result of research, the present inventor has found that the light output signal and the dark output signal of each pixel should be stored in separate storage units, contrary to the conventional common sense that the signals (sampling signals) to be stored in each storage unit. ) Is set as in the following first or third aspect, it has been found that the signal sampling operation and the horizontal scanning period can be shortened to speed up the signal readout operation.

  The present invention has been made on the basis of such new knowledge found by the present inventor. In order to solve the above problems, the solid-state imaging device according to the first aspect of the present invention is two-dimensionally arranged. A plurality of pixels for photoelectrically converting incident light, a vertical signal line provided corresponding to each column of the plurality of pixels and supplied with an output signal of the pixel in a corresponding column, and corresponding to each vertical signal line A signal accumulating unit for accumulating N signals (N is an integer of 3 or more) and a supplied signal, and a first switch provided corresponding to each signal accumulating unit, A first switch for turning on / off the supply of a signal from the vertical signal line corresponding to the storage unit to the signal storage unit, and a second switch provided for each of the signal storage units, Supplying signals from the signal storage unit to a predetermined horizontal signal line A second switch for turning on and off, the plurality of pixels and control means for controlling said first and second switches, in which with a. For each of the vertical signal lines, the control unit assigns a number from 1 to N in an arbitrary order to each of the N signal storage units provided corresponding to the vertical signal lines, and the vertical signal lines N-1 pixels selected from the pixels in the column corresponding to are numbered from 1 to N-1 in any order, and m is an integer from 2 to N-1. In some cases, a signal corresponding to a signal on which dark output signals of pixels Nos. 1 to N−1 are superimposed is stored in the first signal storage unit, and the first signal storage unit stores the first signal storage unit. A signal corresponding to a signal obtained by superimposing a dark output signal of pixels No. 1 to m−1 and a light output signal of pixels No. m to No. N−1 is accumulated, and the No. N signal accumulation unit A signal corresponding to a signal in which the light output signals of pixels No. 1 to N−1 are superimposed is accumulated. Controls the plurality of pixels and said first switch.

  In the first aspect, the light output signal is a pixel output signal including light information photoelectrically converted by a pixel. The dark output signal is a pixel output signal that does not include the optical information.

  The solid-state imaging device according to a second aspect of the present invention is the solid-state imaging device according to the first aspect, wherein each of the pixels generates and stores a signal charge corresponding to incident light, receives the signal charge, and receives the signal charge. A charge-voltage conversion unit that converts a voltage into a voltage, an amplification unit that outputs a signal corresponding to the potential of the charge-voltage conversion unit, a charge transfer unit that transfers charges from the photoelectric conversion unit to the charge-voltage conversion unit, and the charge-voltage conversion A reset unit that resets the potential of the unit and a selection unit that selects the pixel.

  The solid-state imaging device according to the third aspect of the present invention includes a plurality of pixels that are two-dimensionally arranged to photoelectrically convert incident light, and an output of the pixels in a corresponding column provided corresponding to each column of the plurality of pixels. A vertical signal line to which a signal is supplied, a signal storage unit that stores N signals (N is an integer of 3 or more) corresponding to each vertical signal line, and stores the supplied signals; A first switch provided correspondingly, the first switch for turning on / off the supply of a signal from the vertical signal line corresponding to the corresponding signal storage unit to the signal storage unit, and each of the signal storage units A second switch provided corresponding to the second switch for turning on / off the supply of a signal from the corresponding signal storage unit to a predetermined horizontal signal line, the plurality of pixels, and the first and second switches And a control means for controlling the switch of 2. Those were. Each of the pixels includes a photoelectric conversion unit that generates and accumulates signal charges according to incident light, a charge-voltage conversion unit that receives the signal charges and converts the signal charges into a voltage, and a voltage according to the potential of the charge-voltage conversion unit An amplification unit that outputs a signal; a charge transfer unit that transfers charges from the photoelectric conversion unit to the charge-voltage conversion unit; a reset unit that resets the potential of the charge-voltage conversion unit; and a selection unit that selects the pixel . The plurality of pixels form a pixel block for every N−1 pixels in which the photoelectric conversion units are sequentially arranged in the column direction. For each pixel block, the N−1 pixels belonging to the pixel block share a set of the charge voltage conversion unit, the amplification unit, the reset unit, and the selection unit. For each of the vertical signal lines, the control unit assigns a number from 1 to N in an arbitrary order to each of the N signal storage units provided corresponding to the vertical signal lines, and the vertical signal lines N-1 pixels of the selected pixel block among the pixels in the column corresponding to are numbered from 1 to N-1 in any order, and m is an integer from 2 to N-1 In the first signal storage unit, the signal charges of the pixel blocks in the state where the signal charges of the pixels from No. 1 to N−1 are not transferred to the charge voltage conversion unit of the pixel block. A signal corresponding to the output signal is accumulated, and the signal charge of the pixels from No. 1 to m−1 is not transferred to the charge voltage conversion unit of the pixel block in the mth signal accumulation unit and the mth signal accumulation unit. To N-1 pixel signal charges Signals corresponding to the output signals of the pixel block in the state transferred to the charge-voltage conversion unit of the pixel block are accumulated, and pixels Nos. 1 to N−1 are stored in the Nth signal accumulation unit. The plurality of pixels and the first switch are controlled so that a signal corresponding to the output signal of the pixel block in a state where the signal charge of the pixel block is transferred to the charge-voltage conversion unit of the pixel block is accumulated.

  The solid-state imaging device according to a fourth aspect of the present invention is the solid-state imaging device according to any one of the first to third aspects, wherein the N signal accumulations corresponding to the vertical signal lines are provided for the vertical signal lines. The signals from the units are supplied to different horizontal signal lines through the second switches respectively corresponding to the N signal storage units.

  The solid-state imaging device according to a fifth aspect of the present invention is the solid-state imaging device according to the fourth aspect, wherein the control means is configured to simultaneously supply signals from the N signal storage units to the different horizontal signal lines. The second switch is controlled.

  In the solid-state imaging device according to the sixth aspect of the present invention, in the fourth or fifth aspect, the number of the horizontal signal lines is N, and each vertical signal line corresponds to the vertical signal line. A signal from the N signal storage units provided is supplied to any one of the N horizontal signal lines through the second switch corresponding to the N signal storage units. Each is supplied to a line.

  The solid-state imaging device according to a seventh aspect of the present invention is the solid-state imaging device according to the fourth or fifth aspect, wherein the vertical signal lines provided corresponding to the columns of the plurality of pixels are (i) a plurality of groups. (Ii) N horizontal signal lines are provided for each group of the vertical signal lines in correspondence with the group, and (iii) each vertical signal belonging to the group is provided for each group. With respect to the line, signals from the N signal storage units provided corresponding to the vertical signal lines correspond to the group via the second switches respectively corresponding to the N signal storage units. Are supplied to any one of the N horizontal signal lines provided.

  A solid-state imaging device according to an eighth aspect of the present invention provides a solid-state imaging device according to any one of the first to seventh aspects, wherein k is an integer from 1 to N−1, And signal processing means for obtaining signals corresponding to the difference between the signal No. 1 and the signal from the k + 1-th signal storage unit.

  According to the present invention, the present invention provides a solid-state imaging device capable of speeding up a signal reading operation even though a difference between a light output signal and a dark output signal can be substantially obtained. can do.

  Hereinafter, a solid-state imaging device according to the present invention will be described with reference to the drawings.

  [First Embodiment]

  FIG. 1 is a schematic block diagram showing a solid-state imaging device according to the first embodiment of the present invention. As shown in FIG. 1, the solid-state imaging device according to the present embodiment includes an image sensor (solid-state imaging device) 1 and a so-called timing generator (not shown), and a vertical scanning circuit 12 of the image sensor 1 (see FIG. 2). And an external control unit 2 that controls the image sensor 1 by supplying drive pulses and the like to the horizontal scanning circuit 13 (see FIG. 2), and an external signal processing unit 3 that processes a signal obtained from the image sensor 1 to obtain an image signal. And.

  FIG. 2 is a circuit diagram showing the image sensor 1 in FIG. The image sensor 1 is configured as a CMOS solid-state image sensor.

  As shown in FIG. 2, the image sensor 1 has a plurality of unit pixels 11 (in FIG. 2, only 2 × 2 pixels 11 are arranged), like a general CMOS type solid-state imaging device. ), A vertical scanning circuit 12, a horizontal scanning circuit 13, a vertical signal line 14 provided corresponding to each column of the pixels 11, and supplied with an output signal of the pixel 11 in the corresponding column, and each vertical And a constant current source 15 connected to the signal line 14. Needless to say, the number of pixels 11 is not limited.

  Unlike a general CMOS solid-state imaging device, the image sensor 1 corresponds to N (three in the present embodiment) horizontal signal lines 16-1 to 16-3 and each vertical signal line 14. Storage capacitors C1 to C3 serving as signal storage units for storing the supplied signals provided by N (three in the present embodiment) and the first provided corresponding to each of the storage capacitors C1 to C3. Switches TV1 to TV3, second switches TH1 to TH3 provided corresponding to the storage capacitors C1 to C3, and output amplifiers AP1 to AP3 connected to the horizontal signal lines 16-1 to 16-3, respectively. have. In the present embodiment, the first switches TV1 to TV3 and the second switches TH1 to TH3 are all nMOS transistors. Actually, each transistor for resetting the horizontal signal lines 16-1 to 16-3 to a predetermined potential at a predetermined timing is provided, but the illustration of these transistors is omitted.

  The first switches TV1 to TV3 are provided between the vertical signal lines 14 and one ends of the storage capacitors C1 to C3, respectively, and the storage capacitors C1 to C3 are connected to the corresponding storage capacitors C1 to C3 from the vertical signal line 14. The signal supply to C3 is turned on / off. The other ends of the storage capacitors C1 to C3 are grounded. The gates of the first switches TV1 are connected in common and receive a control signal φTV1 from the external control unit 2. The gates of the first switches TV2 are connected in common and receive a control signal φTV2 from the external control unit 2. The gates of the first switches TV3 are connected in common and receive a control signal φTV3 from the external control unit 2.

  The second switches TH1 to TH3 are provided between the one end of the storage capacitors C1 to C3 and the horizontal signal lines 16-1 to 16-3, respectively, and the corresponding storage capacitors C1 to C3 to the horizontal signal line 16-1 are provided. Turn on / off the supply of signals to ˜16-3. The gates of the first switches TH1 to TH3 receive control signals φH1 to φH3 from the horizontal scanning circuit 13, respectively.

  Each pixel 11 has a photodiode PD as a photoelectric conversion unit that generates and accumulates signal charges corresponding to incident light, and receives the signal charges and converts the signal charges into voltage as in a general CMOS solid-state imaging device. A floating diffusion FD serving as a charge-voltage converting unit for converting to a voltage, an amplifying transistor AMP serving as an amplifying unit for outputting a signal corresponding to the potential of the floating diffusion FD, and a charge transferring unit configured to transfer charges from the photodiode PD to the floating diffusion FD Transfer transistor TX, a reset transistor RES as a reset unit for resetting the potential of the floating diffusion FD, and a selection transistor SEL as a selection unit for selecting the pixel 11, as shown in FIG. Connected That. In the present embodiment, the transistors AMP, TX, RES, and SEL of the pixel 11 are all nMOS transistors. In FIG. 2, Vdd is a power supply voltage.

  The gate of the transfer transistor TX is connected to a control line for supplying a control signal φTX for controlling the transfer transistor TX from the vertical scanning circuit 12 to the transfer transistor TX for each row. The gate of the reset transistor RES is connected to a control line for supplying a control signal φRES for controlling the reset transistor RES from the vertical scanning circuit 12 to the reset transistor RES for each row. The gate of the selection transistor SEL is connected to a control line for supplying the control signal φSEL for controlling the selection transistor SEL from the vertical scanning circuit 12 to the selection transistor SEL for each row.

  The photodiode PD generates a signal charge according to the amount of incident light (subject light). The transfer transistor TX is turned on during the high level period of the transfer pulse (control signal) φTX, and transfers the signal charge accumulated in the photodiode PD to the floating diffusion FD. The reset transistor RES is turned on during a high level period of the reset pulse (control signal) φRES to reset the floating diffusion FD.

  The amplification transistor AMP has a drain connected to the power supply voltage Vdd, a gate connected to the floating diffusion FD, a source connected to the drain of the selection transistor SEL, and a force follower circuit having the constant current source 15 as a load. is doing. The amplification transistor AMP outputs a read current to the vertical signal line 14 via the selection transistor SEL according to the voltage value of the floating diffusion FD. The selection transistor SEL is turned on during the high level period of the selection pulse (control signal) φSEL, and connects the source of the amplification transistor AMP to the vertical signal line 14.

  The vertical scanning circuit 12 receives a drive pulse (not shown) from the external control unit 2 and outputs a selection pulse φSEL, a reset pulse φRES, and a transfer pulse φTX for each row of the pixels 11. The horizontal scanning circuit 13 receives a drive pulse (not shown) from the external control unit 2 and outputs control signals φH1 to φH3. Further, as described above, the external control unit 2 outputs the control signals φTV1 to φTV3. Therefore, in the present embodiment, the external control unit 2, the vertical scanning circuit 12, and the horizontal scanning circuit 13 constitute control means for controlling the pixel 11, the first switches TV1 to TV3, and the second switches TH1 to TH3. ing.

  In this embodiment, the external control unit 2, the vertical scanning circuit 12, and the horizontal scanning circuit 13 are provided for each vertical signal line 14 corresponding to the vertical signal line 14 (this embodiment). The three storage capacitors C1 to C3 are numbered from 1 to N (3 in the present embodiment) in an arbitrary order, and among the pixels 11 in the column corresponding to the vertical signal line 14 N-1 (two in the present embodiment) of selected pixels 11 are numbered from 1 to N-1 (2 in the present embodiment) in an arbitrary order, and m is When it is an integer from 2 to N-1 (2 in this embodiment), the first storage capacity is from 1 to N-1 (2 in this embodiment). A signal corresponding to the signal on which the dark output signal of the pixel 11 is superimposed is accumulated, and the m-th accumulation capacitor is stored. According to the signal in which the dark output signals of the pixels 11 from No. 1 to m−1 and the light output signals of the pixels 11 from No. m to N−1 (No. 2 in this embodiment) are superimposed. The light output signals of the pixels 11 from No. 1 to No. N-1 (No. 2 in this embodiment) are stored in the No. N (No. 3 in this embodiment) storage capacitor. Each pixel 11 and the first switches TV1 to TV3 are controlled so that a signal corresponding to the signal superimposed with is accumulated. Further, in the present embodiment, the external control unit 2, the vertical scanning circuit 12, and the horizontal scanning circuit 13 simultaneously turn on and off the second switches TH1 to TH3 for each corresponding to each vertical signal line 14, and N In this embodiment, the second switches TH1 to TH3 are controlled so that signals are simultaneously supplied from the three storage capacitors C1 to C3 to the horizontal signal lines 16-1 to 16-3. Thus, although N = 3 is an example in the present embodiment, the present invention is not limited to this, and N may be 4 or more.

  FIG. 3 is a timing chart showing an example of the reading operation of the solid-state imaging device according to the present embodiment.

  In this embodiment, after a mechanical shutter (not shown) is opened for a predetermined exposure period and charges are accumulated in the charge accumulation layer of the photodiode PD of each pixel 11, N−1 rows (in this embodiment) In the embodiment, two rows are selected sequentially, and the same operation is sequentially performed for each N−1 row (two rows in this embodiment). FIG. 4 mainly shows the operation when the pixels 11 in the n-th and n + 1-th rows are selected and the pixels 11 in the n + 2-th and n + 3-th rows are subsequently selected.

  The period T1 is a horizontal scanning period of the output of the pixels 11 in the (n-2) th row and the (n-1) th row, and corresponds to a period T3 described later.

  In the period T2 after the period T1, the pixels in the nth and n + 1th rows are selected by the vertical scanning circuit 12, and the reset pulses φRES (n) and φRES (n + 1) in the nth and n + 1th rows change to the low level. Then, the reset transistors RES in the nth row and the (n + 1) th row are turned off. Further, in the period T2, the selection pulses φSEL (n) and φSEL (n + 1) in the nth row and the n + 1th row are changed to a high level, and the selection transistors SEL in the nth row and the n + 1th row are turned on. When the selection transistors SEL in the n-th and n + 1-th rows are turned on, the sources of the amplification transistors AMP in the n-th and n + 1-th rows are connected to the vertical signal line 14. The amplification transistors AMP in the n-th row and the (n + 1) -th row operate as a source follower circuit by the constant current source 15.

In the period from the start of the period T2 to the start of the period T12, the selection transistors SEL in the n-th and n + 1-th rows are turned on, and simultaneously the reset transistors RES in the n-th and n + 1-th rows are turned off. The gate voltages of the amplification transistors AMP of the pixels 11 in the n-th and n + 1-th rows are in a floating state, and the reset level of the pixels 11 in the n-th and n + 1-th rows appears on the vertical signal line 14. At this time, in the period T11 after the period T2 starts, the sampling pulse (control signal) φTV1 changes to the high level, and the first switch TV1 is turned on. As a result, the dark output signal VD _n of the pixel 11 in the n-th row (a signal that does not include optical information and here corresponds to the reset state) VD _n and the dark output signal VD _{n + 1} of the pixel 11 in the n + 1-th row The signal VD _n + VD _{n + 1} on which is superimposed is stored in the storage capacitor C1. This operation is executed simultaneously in parallel for the pixels 11 in each column of the nth row and the (n + 1) th row.

Next, in the period T12 in the period T2, the transfer pulse φTX (n) in the nth row changes to a high level, and the transfer transistor TX in the nth row is turned on. When the transfer transistor TX in the n-th row is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PD of the pixel 11 in the n-th row is transferred to the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode of the amplification transistor AMP. As a result, the level including the optical information of the pixel 11 in the nth row and the reset level of the pixel 11 in the (n + 1) th row appear on the vertical signal line 14. At this time, in the period T13 after the period T12, the sampling pulse (control signal) φTV2 changes to the high level, and the first switch TV2 is turned on. As a result, the optical output signal of the pixel 11 in the n-th row (a pixel output signal including optical information photoelectrically converted by the photodiode FD, and the original optical information signal VL _n and the dark output signal VD _n are superimposed) It is the signal _{VL n} + VD n) and the dark output signal _{VD n + 1} and the signal _{VL n + VD n + VD n} + 1 obtained by superposing the pixel of row n + 1 11, accumulated in the storage capacitor C2. This operation is executed simultaneously in parallel for the pixels 11 in each column of the nth row and the (n + 1) th row.

Thereafter, in the period T14 in the period T2, the transfer pulse φTX (n + 1) in the (n + 1) th row changes to a high level, and the transfer transistor TX in the (n + 1) th row is turned on. When the transfer transistor TX in the (n + 1) th row is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PD of the pixel 11 in the (n + 1) th row is transferred to the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode of the amplification transistor AMP. As a result, the level including the optical information of the pixel 11 in the (n + 1) th row and the level including the optical information of the pixel 11 in the (n + 1) th row appear on the vertical signal line 14. At this time, in the period T15 after the period T14, the sampling pulse (control signal) φTV3 changes to the high level, and the first switch TV3 is turned on. As a result, the light output signal VL _n + VD _n of the pixel 11 in the n-th row and the light output signal of the pixel 11 in the n + 1-th row (a pixel output signal including light information photoelectrically converted by the photodiode FD, of the optical information signal _{VL n + 1} and the dark output signal _{VD n + 1} and the signal is superimposed _{VL n + 1 + VD n +} 1) and the signal is superimposed _{VL n + VD n + VL n} + 1 + VD n + 1 is stored in the storage capacitor C3. This operation is executed simultaneously in parallel for the pixels 11 in each column of the nth row and the (n + 1) th row.

In this manner, in the period T2, the output signals of the pixels 11 in the n-th row and the (n + 1) -th row are sampled. For each column, (i) the storage capacitor C1 has the darkness of the pixel 11 in the n-th row. signal _VD n + _{VD n + 1} where the dark output signal _{VD n + 1} is superimposed in the output signal VD _n and n + 1 th row of pixels 11 are accumulated, (ii) the storage capacitor C2, the optical output signal of the pixel of row n 11 A signal VL _n + VD _n + VD _{n + 1 obtained} by superimposing the VL _n + VD _n and the dark output signal VD _{n + 1} of the pixel 11 in the ( _{n + 1} ) th row is accumulated, and (iii) the light of the pixel 11 in the nth row is stored in the storage capacitor C3. output signal _VL n + VD _n and n + 1 optical output signal of the row of pixels 11 _VL n + 1 + _{VD n + 1} and the signal is superimposed _{VL n + VD n + VL n} + 1 + VD n + 1 are accumulated.

  A period T3 after the period T2 is a horizontal scanning period of the output of the pixels 11 in the n-th row and the (n + 1) -th row. In the period T3, the second switches TH1 to TH3 are sequentially turned on for each of the vertical signal lines 14 by horizontal scanning using the control signals φH1 to φH3 from the horizontal scanning circuit 13, and stored in the storage capacitors C1 to C3, respectively. 1 is sequentially read out to the horizontal signal lines 16-1 to 16-3 for each of the signals corresponding to the vertical signal lines 14, and the external signal processing unit 3 in FIG. Is output. At this time, the second switches TH1 to TH3 corresponding to the same vertical signal line 14 are simultaneously turned on and off.

Although not shown in the drawing, the external signal processing unit 3 obtains a difference between outputs of the output amplifiers AP1 and AP2 by a differential amplifier or the like. In the period T3, this difference signal is the difference between the signal VD _n + VD _{n + 1} stored in the storage capacitor C1 and the signal VL _n + VD _n + VD _{n + 1} stored in the storage capacitor C2 (that is, the pixel 11 in the n-th row). Of the original optical information signal VL _n ). The external signal processing unit 3 obtains a difference between the outputs of the output amplifiers AP2 and AP3 using a differential amplifier or the like. In the period T3, the difference signal is a difference between the signal VL _n + VD _n + VD _{n + 1} stored in the storage capacitor C2 and the signal VL _n + VD _n + VL _{n + 1} + VD _{n + 1} stored in the storage capacitor C3 (that is, n + 1 rows). The signal corresponds to the original optical information signal VL _{n + 1} ) of the eye pixel 11. In this way, optical information signals VL _n and VL _{n + 1 from} which noise components (VD _n and VD _{n + 1} ) have been removed are obtained, which is equivalent to the case of conventional correlated double sampling.

  Next, in the periods T4 and T5, operations similar to those performed in the periods T2 and T3 with respect to the nth row and the n + 1th row are performed for the n + 2th row and the n + 3th row, and the same operation is performed thereafter. repeat.

  Here, a solid-state imaging device according to a comparative example compared with the solid-state imaging device according to the present embodiment will be described. This comparative example corresponds to the above-described prior art. FIG. 4 is a circuit diagram showing the image sensor 101 used in the solid-state imaging device according to this comparative example. 4, elements that are the same as or correspond to those in FIG. 2 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The solid-state imaging device according to this comparative example is different from the solid-state imaging device according to the present embodiment only in the points described below. In this comparative example, in the image sensor 101, the storage capacitor C3, the first switch TV3, the second switch TH3, the horizontal signal line 16-3, and the output amplifier AP3 are removed. In this comparative example, the external control unit 2, the vertical scanning circuit 12, and the horizontal scanning circuit 13 are associated with one storage capacitor C 1 provided corresponding to the vertical signal line 14 for each vertical signal line 14. The dark output signals of the pixels 11 in the column are accumulated, and the light output signals of the pixels 11 in the column are accumulated in the other storage capacitor C2 provided corresponding to the vertical signal line 14. The first switches TV1 and TV2 are controlled.

  Accordingly, in this comparative example, a read operation is performed according to the timing chart shown in FIG. FIG. 5 is a timing chart showing the read operation of the solid-state imaging device according to this comparative example.

  In this comparative example, after a mechanical shutter (not shown) is opened for a predetermined exposure period and charges are accumulated in the charge accumulation layer of the photodiode PD of each pixel 11, the lines are sequentially selected one by one. The same operation is performed sequentially. FIG. 5 mainly shows the operation when the pixel 11 in the nth row is selected and the pixel 11 in the (n + 1) th row is subsequently selected.

  The period T21 is a horizontal scanning period of the output of the pixel 11 in the (n−1) th row and corresponds to a period T23 described later.

  In the period T22 after the period T21, the vertical scanning circuit 12 selects the pixel 11 in the n-th row, the n-th row reset pulse φRES (n) changes to a low level, and the n-th row reset transistor RES is turned off. . In the period T22, the selection pulse φSEL (n) in the nth row changes to a high level, and the selection transistor SEL in the nth row is turned on. When the selection transistor SEL in the nth row is turned on, the source of the amplification transistor AMP in the nth row is connected to the vertical signal line 14. The amplification transistor AMP in the n-th row operates as a source follower circuit by the constant current source 15.

In the period from the start of the period T22 to the start of the period T32, the n-th row selection transistor SEL is turned on, and at the same time, the n-th row reset transistor RES is turned off. The gate voltage of the amplification transistor AMP enters a floating state, and the reset level of the pixel 11 in the nth row appears on the vertical signal line 14. At this time, in the period T31 after the period T22 starts, the sampling pulse (control signal) φTV1 changes to the high level, and the first switch TV1 is turned on. Thus, the dark output signal VD _n in the n-th row of pixels 11 is accumulated in the storage capacitor C1. This operation is performed simultaneously in parallel on the pixels 11 in each column of the nth row.

Next, in the period T32 in the period T22, the transfer pulse φTX (n) in the nth row changes to a high level, and the transfer transistor TX in the nth row is turned on. When the transfer transistor TX in the n-th row is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PD of the pixel 11 in the n-th row is transferred to the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode of the amplification transistor AMP. As a result, a level including optical information of the pixels 11 in the nth row appears on the vertical signal line 14. At this time, in the period T33 after the period T32, the sampling pulse (control signal) φTV2 changes to the high level, and the first switch TV2 is turned on. As a result, the light output signal VL _n + VD _n of the pixel 11 in the n-th row is accumulated in the storage capacitor C2. This operation is performed simultaneously in parallel on the pixels 11 in each column of the nth row.

In this way, in the period T22, the output signal of the pixel 11 in the n-th row is sampled. For each column, (i) the dark output signal VD _n of the pixel 11 in the n-th row is stored in the storage capacitor C1. (Ii) The light output signal VL _n + VD _n of the pixel 11 in the n-th row is stored in the storage capacitor C2.

  A period T23 after the period T22 is a horizontal scanning period of the output of the pixels 11 in the n-th row. In the period T23, the second switches TH1 and TH2 are sequentially turned on for each of the vertical signal lines 14 by horizontal scanning using the control signals φH1 and φH2 from the horizontal scanning circuit 13, and stored in the storage capacitors C1 and C2, respectively. The signals that correspond to the vertical signal lines 14 are sequentially read out to the horizontal signal lines 16-1 and 16-2 and output to the external signal processing unit 3 through the output amplifiers AP1 and AP2, respectively. .

Although not shown in the drawing, in this comparative example, the external signal processing unit 3 obtains the difference between the outputs of the output amplifiers AP1 and AP2 by a differential amplifier or the like. In the period T23, the difference signal is output from the dark output signal VD _n of the pixel 11 in the n-th row stored in the storage capacitor C1 and the light output signal VL _n of the pixel 11 in the n-th row stored in the storage capacitor C2. The signal corresponds to the difference from + VD _n (that is, the original optical information signal VL _n of the pixel 11 in the n-th row). In this way, an optical information signal VL _n from which noise (VD _n ) has been removed is obtained in accordance with correlated double sampling.

  Next, in the periods T24 and T25, operations similar to those performed in the periods T22 and T23 for the nth row are performed for the (n + 1) th row, and the same operations are repeated thereafter.

  As apparent from the comparison between FIG. 3 according to the present embodiment and FIG. 5 according to the comparative example, according to the present embodiment, the signal sampling time and the horizontal scanning period are shortened as compared with the comparative example. Thus, the signal reading operation can be speeded up.

  That is, in the comparative example, a total of four sampling periods T31, T33, T34, and T36 are required for signal readout of the pixels 11 in the nth row and the (n + 1) th row, whereas in the present embodiment, the nth row. For the signal readout of the pixel 11 and the pixel 11 in the (n + 1) th row, a total of three sampling periods T11, T13, and T15 are sufficient. Therefore, according to the present embodiment, the sampling time can be shortened as compared with the comparative example, and as a result, the signal readout can be speeded up.

  In the comparative example, two horizontal scanning periods T23 and T25 are required for signal readout of the pixels 11 in the n-th and n + 1-th rows, whereas in this embodiment, the n-th and n + 1-th rows are required. Only one horizontal scanning period T3 is required for signal readout of the pixel 11. Therefore, according to the present embodiment, it is possible to shorten the horizontal scanning period as compared with the comparative example, and also from this point, it is possible to speed up signal readout.

  [Second Embodiment]

  FIG. 6 is a circuit diagram showing the image sensor 21 used in the solid-state imaging device according to the second embodiment of the present invention, and corresponds to FIG. 6, elements that are the same as or correspond to those in FIG. 2 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The present embodiment is different from the first embodiment only in the points described below. In the present embodiment, in the image sensor 21, instead of the output amplifiers AP1 to AP3, a differential amplifier DAP1 that obtains a difference between the signal of the horizontal signal line 16-1 and the signal of the horizontal signal line 16-2, and the horizontal A differential amplifier DAP2 for obtaining a difference between the signal on the signal line 16-2 and the signal on the horizontal signal line 16-3 is provided.

In the present embodiment, a signal corresponding to the original optical information signal VL _n of the pixel 11 in the n-th row is obtained from the differential amplifier DAP1, and the original optical information signal of the pixel 11 in the n + 1-th row is obtained from the differential amplifier DAP2. A signal corresponding to VL _{n + 1} is obtained. Therefore, in the present embodiment, the external signal processing unit 3 in FIG. 1 is not necessary.

  Also in this embodiment, the same advantages as those in the first embodiment can be obtained.

  [Third Embodiment]

  FIG. 7 is a circuit diagram showing an image sensor 31 used in the solid-state imaging device according to the third embodiment of the present invention, and corresponds to FIG. In FIG. 7, the same or corresponding elements as those in FIG. 2 are denoted by the same reference numerals, and redundant description thereof is omitted.

  The present embodiment is different from the first embodiment only in the points described below. In the present embodiment, in the image sensor 31, horizontal signal lines 16-11 to 16-13 and output amplifiers AP11 to AP13 respectively corresponding to the horizontal signal lines 16-1 to 16-3 and the output amplifiers AP1 to AP3 are added. Has been. In this embodiment, the vertical signal lines 14 provided corresponding to the columns of the pixels 11 are divided into two groups. The signals from the storage capacitors C1 to C3 corresponding to the vertical signal line 14 of one group correspond to the group via the second switches TH1 to TH3 corresponding to the storage capacitors C1 to C3, respectively. It is wired so as to be respectively supplied to the provided horizontal signal lines 16-1 to 16-3. The signals from the storage capacitors C1 to C3 corresponding to the vertical signal line 14 of the other group correspond to the group via the second switches TH1 to TH3 corresponding to the storage capacitors C1 to C3, respectively. It is wired so as to be respectively supplied to the provided horizontal signal lines 16-11 to 16-13. As the output amplifiers AP11 to AP13 are added, the external signal processing unit 3 not only outputs the difference between the outputs of the output amplifiers AP1 and AP2 and the difference between the outputs of the output amplifiers AP2 and AP3, but also the output amplifier AP11. , AP12 and a difference between outputs of the output amplifiers AP12, AP13.

  According to the present embodiment, the signal readout can be speeded up as in the first embodiment. In addition, according to the present embodiment, the signal transfer from the storage capacitors C1 to C3 of one group to the horizontal signal lines 16-1 to 16-3 and the horizontal signal line from the storage capacitors C1 to C3 of the other group are performed. Since signal transfer to 16-11 to 16-13 can be performed at the same time, the horizontal scanning period can be shortened to half compared to the first embodiment, and signal readout can be performed at higher speed. can do.

  In this embodiment, the vertical signal lines 14 are divided into two groups and two sets of horizontal signal lines are provided. However, in the present invention, the vertical signal lines 14 are divided into three or more groups and horizontally. Three or more signal lines may be provided.

  [Fourth Embodiment]

  FIG. 8 is a circuit diagram showing an image sensor 41 used in the solid-state imaging device according to the fourth embodiment of the present invention, and corresponds to FIG. FIG. 2 shows 2 × 2 pixels 11, whereas FIG. 8 shows 4 × 2 pixels 11 (2 × 2 pixel blocks 111). In FIG. 8, the same or corresponding elements as those in FIG. 2 are denoted by the same reference numerals, and redundant description thereof is omitted.

  The present embodiment is different from the first embodiment only in the points described below. In the present embodiment, in the image sensor 41, for every two pixels 11 adjacent in the column direction, the two pixels 11 share a set of floating diffusion FD, amplification transistor AMP, reset transistor RES, and selection transistor SEL. ing. In FIG. 8, two pixels 11 sharing one set of floating diffusion FD, amplification transistor AMP, reset transistor RES, and selection transistor SEL are shown as a pixel block 111. In FIG. 8, the photodiode PD and the transfer transistor TX of the upper pixel 11 in the pixel block 111 are indicated by symbols PDA and TXA, respectively, and the photodiode PD and the transfer transistor TX of the lower pixel 11 in the pixel block 111 are illustrated. Are indicated by symbols PDB and TXB, respectively, to distinguish them. Further, the control signal supplied to the gate electrode of the transfer transistor TXA is φTXA, and the control signal supplied to the gate electrode of the transfer transistor TXB is φTXB to distinguish them. In FIG. 1, n indicates a pixel row, but in FIG. 8, n indicates a row of the pixel block 111. In FIG. 8, for convenience of drawing notation, the photodiodes PDA and PDB in the same pixel block 111 are described as if they are shifted in the row direction (lateral direction in the drawing). These photodiodes PDA and PDB are arranged in the column direction.

  Therefore, the image sensor 41 used in the solid-state imaging device according to the present embodiment is different from a general CMOS solid-state imaging device, and has N (three in the present embodiment) horizontal signal lines 16-1 to 16-16. −3, N (3 in the present embodiment) corresponding to each vertical signal line 14, and storage capacitors C1 to C3 as signal storage units for storing the supplied signals, and each storage capacitor First switches TV1 to TV3 provided corresponding to C1 to C3, second switches TH1 to TH3 provided corresponding to the storage capacitors C1 to C3, and horizontal signal lines 16-1 to 16- 3 are connected to output amplifiers AP1 to AP3, respectively. In this embodiment, a pixel block 111 is formed for each of N−1 (two in this embodiment) pixels 11 in which photodiodes PD (PDA, PDB) are sequentially arranged in the column direction. For every 111, N−1 (two in the present embodiment) pixels 11 belonging to the pixel block 111 share a set of floating diffusion FD, amplification transistor AMP, reset transistor RES, and selection transistor SEL. Yes.

  In this embodiment, the external control unit 2, the vertical scanning circuit 12, and the horizontal scanning circuit 13 are provided for each vertical signal line 14 corresponding to the vertical signal line 14 (this embodiment). The three storage capacitors C1 to C3 are numbered from 1 to N (3 in the present embodiment) in an arbitrary order, and among the pixels 11 in the column corresponding to the vertical signal line 14 N-1 (two in the present embodiment) of the selected pixel block 111 are numbered from 1 to N-1 (2 in the present embodiment) in any order. When m is an integer from 2 to N-1 (2 in the present embodiment), the first storage capacity includes 1st to N-1 (in this embodiment, Signal charge of the pixel 11 up to the second) is the float of the pixel block 111 A signal corresponding to the output signal of the pixel block 111 in a state not transferred to the diffusion FD is accumulated, and the signal charges of the pixels 11 from No. 1 to m−1 are stored in the m-th storage capacitor. In the state in which the signal charges of the pixels 11 from the m-th to the N−1-th (in this embodiment, No. 2) are not transferred to the floating diffusion FD 111 and transferred to the floating diffusion FD of the pixel block 111. A signal corresponding to the output signal of the pixel block 111 is accumulated, and the N-th (in this embodiment, No. 3) storage capacitor has No. 1 through N-1 (in this embodiment, 2). No.) in the state where the signal charges of the pixel 11 are transferred to the floating diffusion FD of the pixel block 111. So that the signal corresponding to the output signal of the unit blocks 111 are accumulated to control the pixels 11 and the first switch TV1～TV3. Further, in the present embodiment, the external control unit 2, the vertical scanning circuit 12, and the horizontal scanning circuit 13 simultaneously turn on and off the second switches TH1 to TH3 for each corresponding to each vertical signal line 14, and N In this embodiment, the second switches TH1 to TH3 are controlled so that signals are simultaneously supplied from the three storage capacitors C1 to C3 to the horizontal signal lines 16-1 to 16-3. Thus, although N = 3 is an example in the present embodiment, the present invention is not limited to this, and N may be 4 or more.

  FIG. 9 is a timing chart showing an example of the reading operation of the solid-state imaging device according to the present embodiment, and corresponds to FIG.

  In the present embodiment, after a mechanical shutter (not shown) is opened for a predetermined exposure period and charges are accumulated in the charge accumulation layers of the photodiodes PDA and PDB of each pixel 11 of each pixel block 111, the pixel block 111 rows (that is, two pixel rows) are sequentially selected, and the same operation is sequentially performed for each row. FIG. 9 mainly shows the operation when the pixel block 111 in the nth row is selected and the pixel block 111 in the (n + 1) th row is subsequently selected.

  The period T41 is a horizontal scanning period of the output of the pixel block 111 in the (n-1) th row (that is, the output of the upper pixel 11 and the lower pixel 11 of the (n-1) th pixel block 111). This corresponds to the period T43.

  In the period T42 after the period T41, the vertical scanning circuit 12 selects the pixel block 111 in the nth row (that is, the upper pixel 11 and the lower pixel 11 in the nth pixel block 111), and the nth row. The reset pulse φRES (n) changes to the low level, and the reset transistor RES of the pixel block 111 in the nth row is turned off. In the period T42, the selection pulse φSEL (n) in the nth row changes to a high level, and the selection transistor SEL in the pixel block 111 in the nth row is turned on. When the selection transistor SEL of the pixel block 111 in the n-th row is turned on, the source of the amplification transistor AMP in the pixel block 111 in the n-th row is connected to the vertical signal line 14. The amplification transistor AMP of the pixel block 111 in the n-th row operates as a source follower circuit by the constant current source 15.

  In the period from the start of the period T42 to the start of the period T52, the selection transistor SEL of the n-th pixel block 111 is turned on, and at the same time, the reset transistor RES of the n-th pixel block 111 is turned off. The gate voltage of the amplification transistor AMP of the pixel block 111 in the n-th row is in a floating state, and the reset levels of the upper pixel 11 and the lower pixel 11 in the n-th pixel block 111 appear on the vertical signal line 14. In this state, the signal charge of the upper pixel 11 and the signal charge of the lower pixel 11 of the pixel block 111 in the n-th row are not transferred to the floating diffusion FD of the pixel block 111 in the n-th row (hereinafter, "Dark state"). At this time, in the period T51 after the period T42 starts, the sampling pulse (control signal) φTV1 changes to the high level, and the first switch TV1 is turned on. Thereby, the dark output signal (output signal of the pixel block 111 in the dark state) VD of the pixel block 111 in the n-th row is stored in the storage capacitor C1. This operation is executed simultaneously in parallel for the pixel blocks 111 in each column of the nth row.

  Next, in the period T52 in the period T42, the transfer pulse φTXB (n) in the n-th row changes to a high level, and the transfer transistor TXB of the pixel 11 on the lower side of the pixel block 111 in the n-th row is turned on. When the transfer transistor TXB is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PDB of the pixel 11 on the lower side of the pixel block 111 in the n-th row is transferred to the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode of the amplification transistor AMP. As a result, a level including the optical information of the pixel 11 below the pixel block 111 in the nth row appears on the vertical signal line 14. At this time, in the period T53 after the period T52, the sampling pulse (control signal) φTV2 changes to the high level, and the first switch TV2 is turned on. As a result, the signal charge of the pixel 11 on the upper side of the pixel block 111 in the n-th row is not transferred to the floating diffusion FD, and the signal charge of the pixel 11 on the lower side of the pixel block 111 in the n-th row is transferred to the floating diffusion FD. In this state, the output signal VLB + VD of the pixel block 111 is stored in the storage capacitor C2. This operation is executed simultaneously in parallel for the pixel blocks 111 in each column of the nth row. The output signal VLB + VD corresponds to a signal in which the dark output signal VD and the original optical information signal VLB of the lower pixel 11 are superimposed.

  Thereafter, in the period T54 in the period T42, the transfer pulse φTXA (n) in the n-th row changes to a high level, and the transfer transistor TXA of the pixel 11 on the upper side of the pixel block 111 in the n-th row is turned on. When the transfer transistor TXA is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PDA of the upper pixel 11 of the pixel block 111 in the n-th row is transferred to the corresponding floating diffusion FD. As a result, both the signal charge of the upper pixel 11 and the signal charge of the lower pixel 11 of the pixel block 111 in the n-th row are transferred to the floating diffusion FD in the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the amount of charge obtained by adding both transferred signal charges, and this voltage is applied to the gate electrode of the amplification transistor AMP. As a result, a level including the light information of the upper pixel 11 and the light information of the lower pixel 11 in the n-th row appears on the vertical signal line 14. At this time, in the period T55 after the period T54, the sampling pulse (control signal) φTV3 changes to the high level, and the first switch TV3 is turned on. Accordingly, the output signal VLA + VLB + VD of the pixel block 111 in a state where the signal charge of the upper pixel 11 and the signal charge of the lower pixel 11 of the pixel block 111 in the n-th row are transferred to the floating diffusion FD is stored in the storage capacitor C3. Accumulated. This operation is executed simultaneously in parallel for the pixel blocks 111 in each column of the nth row. The output signal VLA + VLB + VD corresponds to a signal in which the dark output signal VD, the original optical information signal VLA of the upper pixel 11 and the original optical information signal VLB of the lower pixel 11 are superimposed.

  In this way, in the period T42, the output signal of the pixel block 111 in the n-th row is sampled. For each column, (i) the dark output signal of the pixel block 111 in the n-th row is stored in the storage capacitor C1. The VD is stored, (ii) the storage capacitor C2 stores the signal VLB + VD in which the dark output signal VD and the original optical information signal VLB of the lower pixel 11 are superimposed, and (iii) the storage capacitor C3. Then, a signal VLA + VLB + VD in which the dark output signal VD, the original optical information signal VLA of the upper pixel 11 and the original optical information signal VLB of the lower pixel 11 are superimposed is accumulated.

  A period T43 after the period T42 is a horizontal scanning period of the output of the pixel block 111 in the n-th row (that is, the output of the upper pixel 11 and the lower pixel 11 of the n-th pixel block 111). In the period T43, the second switches TH1 to TH3 are sequentially turned on for each of the vertical signal lines 14 by horizontal scanning using the control signals φH1 to φH3 from the horizontal scanning circuit 13, and are stored in the storage capacitors C1 to C3, respectively. The signals that have been processed are sequentially read out to the horizontal signal lines 16-1 to 16-3 for each of the signals corresponding to the vertical signal lines 14, and output to the external signal processing unit 3 through the output amplifiers AP1 to AP3, respectively. . At this time, the second switches TH1 to TH3 corresponding to the same vertical signal line 14 are simultaneously turned on and off.

  Although not shown in the drawing, the external signal processing unit 3 obtains a difference between outputs of the output amplifiers AP1 and AP2 by a differential amplifier or the like. In the period T43, this difference signal is the difference between the signal VD stored in the storage capacitor C1 and the signal VLB + VD stored in the storage capacitor C2 (that is, the pixel 11 below the pixel block 111 in the n-th row). It becomes a signal according to the original optical information signal VLB). The external signal processing unit 3 obtains a difference between the outputs of the output amplifiers AP2 and AP3 using a differential amplifier or the like. In the period T43, this difference signal is the difference between the signal VLB + VD stored in the storage capacitor C2 and the signal VLA + VLB + VD stored in the storage capacitor C3 (that is, the original pixel 11 on the upper side of the pixel block 111 in the n-th row). Of the optical information signal VLA). In this way, optical information signals VLA and VLB from which noise (VD) has been removed are obtained, which is equivalent to the case of conventional correlated double sampling.

  Next, in the periods T44 and T45, the same operation as that performed in the periods T42 and T43 for the pixel block 111 in the n-th row is performed for the pixel block 111 in the n + 1-th row, and the same operation is performed thereafter. repeat.

  Here, a solid-state imaging device according to a comparative example compared with the solid-state imaging device according to the present embodiment will be described. FIG. 10 is a circuit diagram showing an image sensor 141 used in the solid-state imaging device according to this comparative example. 10, elements that are the same as or correspond to those in FIG. 8 are given the same reference numerals, and redundant descriptions thereof are omitted.

  The solid-state imaging device according to this comparative example is different from the solid-state imaging device according to the present embodiment only in the points described below. In this comparative example, in the image sensor 141, the storage capacitor C3, the first switch TV3, the second switch TH3, the horizontal signal line 16-3, and the output amplifier AP3 are removed. In this comparative example, the external control unit 2, the vertical scanning circuit 12, and the horizontal scanning circuit 13 are associated with one storage capacitor C 1 provided corresponding to the vertical signal line 14 for each vertical signal line 14. The dark output signals of the pixels 11 in the column are accumulated, and the light output signals of the pixels 11 in the column are accumulated in the other storage capacitor C2 provided corresponding to the vertical signal line 14. And controls the first switches TV1 and TV2.

  Accordingly, in this comparative example, the read operation is performed according to the timing chart shown in FIG. FIG. 11 is a timing chart showing the reading operation of the solid-state imaging device according to this comparative example.

  In this comparative example, after a mechanical shutter (not shown) is opened for a predetermined exposure period and charges are accumulated in the charge accumulation layers of the photodiodes PDA and PDB of each pixel 11 of each pixel block 111, each row has two. The selection is sequentially performed once, and the same operation is sequentially performed for each row. FIG. 11 mainly shows an operation when the pixel block 111 in the n-th row is selected.

  The period T61 is a horizontal scanning period of the output of the pixel 11 on the upper side of the pixel block 111 in the (n−1) th row, and corresponds to a period T65 described later.

  In a period T62 after the period T61, the vertical scanning circuit 12 selects the n-th pixel block 111, the n-th row reset pulse φRES (n) changes to a low level, and the n-th row pixel block 111 is reset. The transistor RES is turned off. Further, in the period T62, the selection pulse φSEL (n) in the nth row changes to a high level, and the selection transistor SEL in the pixel block 111 in the nth row is turned on. When the selection transistor SEL of the pixel block 111 in the n-th row is turned on, the source of the amplification transistor AMP in the n-th row is connected to the vertical signal line 14. The amplification transistor AMP of the pixel block 111 in the n-th row operates as a source follower circuit by the constant current source 15.

  In the period from the start of the period T62 to the start of the period T72, the selection transistor SEL of the n-th pixel block 111 is turned on, and at the same time, the reset transistor RES of the n-th pixel block 111 is turned off. The gate voltage of the amplification transistor AMP of the pixel block 111 in the n-th row is in a floating state, and the reset level of the pixel 11 below the pixel block 111 in the n-th row appears on the vertical signal line 14. At this time, in the period T71 after the period T62 starts, the sampling pulse (control signal) φTV1 changes to the high level, and the first switch TV1 is turned on. As a result, the dark output signal VD of the pixel block 111 in the n-th row is stored in the storage capacitor C1. This operation is executed simultaneously in parallel for the pixel blocks 111 in each column of the nth row.

  Next, in a period T72 in the period T62, the transfer pulse φTXB (n) in the n-th row changes to a high level, and the transfer transistor TXB of the pixel 11 below the pixel block 111 in the n-th row is turned on. When the transfer transistor TXB is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PDB of the pixel 11 on the lower side of the pixel block 111 in the n-th row is transferred to the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode of the amplification transistor AMP. As a result, a level including the optical information of the pixel 11 below the pixel block 111 in the nth row appears on the vertical signal line 14. At this time, in the period T73 after the period T72, the sampling pulse (control signal) φTV2 changes to the high level, and the first switch TV2 is turned on. As a result, the signal charge of the pixel 11 on the upper side of the pixel block 111 in the n-th row is not transferred to the floating diffusion FD, and the signal charge of the pixel 11 on the lower side of the pixel block 111 in the n-th row is transferred to the floating diffusion FD. In this state, the output signal of the pixel block 111 (that is, the light output signal of the lower pixel 11) VL + BVD is stored in the storage capacitor C2. This operation is executed simultaneously in parallel for the pixel blocks 111 in each column of the nth row. The optical output signal VLB + VD corresponds to a signal in which the dark output signal VD and the original optical information signal VLB of the lower pixel 11 are superimposed.

  In this way, in the period T62, the output signal of the pixel 11 on the lower side of the pixel block 111 in the n-th row is sampled. For each column, (i) the pixel in the n-th row is stored in the storage capacitor C1. The dark output signal VD of the lower pixel 11 of the block 111 is accumulated, and (ii) the light output signal VLB + VD of the lower pixel 11 of the nth pixel block 111 is accumulated in the storage capacitor C2.

  A period T63 after the period T62 is a horizontal scanning period of the output of the pixel 11 on the lower side of the pixel block 111 in the n-th row. In the period T63, the second switches TH1 and TH2 are sequentially turned on for each of the vertical signal lines 14 by horizontal scanning using the control signals φH1 and φH2 from the horizontal scanning circuit 13, and stored in the storage capacitors C1 and C2, respectively. The signals that correspond to the vertical signal lines 14 are sequentially read out to the horizontal signal lines 16-1 and 16-2 and output to the external signal processing unit 3 through the output amplifiers AP1 and AP2, respectively. .

  Although not shown in the drawing, in this comparative example, the external signal processing unit 3 obtains the difference between the outputs of the output amplifiers AP1 and AP2 by a differential amplifier or the like. In the period T63, the difference signal is supplied to the dark output signal VD of the pixel 11 on the lower side of the pixel block 111 stored in the storage capacitor C1 and the pixel block in the nth row stored in the storage capacitor C2. 111 is a signal corresponding to a difference from the light output signal VLB + VD of the lower pixel 11 of 111 (that is, the original optical information signal VLB of the lower pixel 11 of the pixel block 111 in the n-th row). In this way, the optical information signal VLB from which noise (VD) has been removed is obtained according to correlated double sampling.

  Next, in the period T64, the pixel block 111 in the n-th row is selected again by the vertical scanning circuit 12, and the reset pulse φRES (n) in the n-th row changes to the low level. The reset transistor RES is turned off. In the period T64, the selection pulse φSEL (n) in the nth row changes to a high level, and the selection transistor SEL in the pixel block 111 in the nth row is turned on. When the selection transistor SEL of the pixel block 111 in the n-th row is turned on, the source of the amplification transistor AMP in the n-th row is connected to the vertical signal line 14. The amplification transistor AMP of the pixel block 111 in the n-th row operates as a source follower circuit by the constant current source 15.

  In the period from the start of the period T64 to the start of the period T75, the selection transistor SEL of the n-th pixel block 111 is turned on, and at the same time, the reset transistor RES of the n-th pixel block 111 is turned off. The gate voltage of the amplification transistor AMP in the pixel block 111 in the n-th row becomes a floating state, and the reset level of the pixel 11 on the upper side of the pixel block 111 in the n-th row appears on the vertical signal line 14. At this time, in the period T74 after the period T64 starts, the sampling pulse (control signal) φTV1 changes to the high level, and the first switch TV1 is turned on. As a result, the dark output signal VD of the pixel block 111 in the n-th row is stored in the storage capacitor C1. This operation is executed simultaneously in parallel for the pixel blocks 111 in each column of the nth row.

  Next, in the period T75 in the period T64, the transfer pulse φTXA (n) in the nth row changes to a high level, and the transfer transistor TXA of the pixel 11 on the upper side of the pixel block 111 in the nth row is turned on. When the transfer transistor TXA is turned on, the signal charge photoelectrically converted and accumulated by the photodiode PDA of the upper pixel 11 of the pixel block 111 in the n-th row is transferred to the corresponding floating diffusion FD. As a result, the voltage of the floating diffusion FD becomes a voltage corresponding to the transferred charge amount, and this voltage is applied to the gate electrode of the amplification transistor AMP. As a result, a level including the optical information of the pixel 11 on the upper side of the pixel block 111 in the n-th row appears on the vertical signal line 14. At this time, in the period T76 after the period T75, the sampling pulse (control signal) φTV2 changes to the high level, and the first switch TV2 is turned on. Thereby, the signal charge of the lower pixel 11 of the pixel block 111 in the n-th row is not transferred to the floating diffusion FD, and the signal charge of the upper pixel 11 of the pixel block 111 in the n-th row is transferred to the floating diffusion FD. In this state, the output signal of the pixel block 111 (that is, the light output signal of the upper pixel 11) VLA + VD is stored in the storage capacitor C2. This operation is executed simultaneously in parallel for the pixel blocks 111 in each column of the nth row. The light output signal VLA + VD corresponds to a signal in which the dark output signal VD and the original light information signal VLA of the upper pixel 11 are superimposed.

  In this way, in the period T64, the output signal of the pixel 11 on the upper side of the pixel block 111 in the n-th row is sampled. For each column, (i) the pixel block in the n-th row is stored in the storage capacitor C1. The dark output signal VD of the upper pixel 11 of 111 is accumulated. (Ii) The light output signal VLA + VD of the upper pixel 11 of the pixel block 111 in the n-th row is accumulated in the storage capacitor C2.

  A period T65 after the period T64 is a horizontal scanning period of the output of the pixel 11 on the upper side of the pixel block 111 in the n-th row. In the period T65, the second switches TH1 and TH2 are sequentially turned on for each of the vertical signal lines 14 by horizontal scanning using the control signals φH1 and φH2 from the horizontal scanning circuit 13, and stored in the storage capacitors C1 and C2, respectively. The signals that correspond to the vertical signal lines 14 are sequentially read out to the horizontal signal lines 16-1 and 16-2 and output to the external signal processing unit 3 through the output amplifiers AP1 and AP2, respectively. .

  The difference signal between the outputs of the output amplifiers AP1 and AP2 obtained in the external signal processing unit 3 in the period T65 is the dark output signal VD of the pixel 11 on the upper side of the pixel block 111 in the n-th row stored in the storage capacitor C1. The difference from the light output signal VLA + VD of the pixel 11 on the upper side of the pixel block 111 in the n-th row accumulated in the storage capacitor C2 (that is, the original optical information signal VLA of the pixel 11 on the upper side of the pixel block 111 in the n-th row) ). In this way, an optical information signal VLA from which noise (VD) has been removed is obtained according to correlated double sampling.

  Thereafter, the same operation as that performed in the period T62 to T65 with respect to the pixel block 111 in the nth row is performed for the pixel block 111 in the (n + 1) th row, and the same operation is repeated thereafter.

  As is clear from the comparison between FIG. 9 according to the present embodiment and FIG. 11 according to the comparative example, according to the present embodiment, the signal sampling time and the horizontal scanning period are reduced as compared with the comparative example. Thus, the signal reading operation can be speeded up.

  That is, in the comparative example, a total of four sampling periods T71, T73, T74, and T76 are required for signal readout of the upper pixel 11 and the lower pixel 11 of the pixel block 111 in the n-th row. In the embodiment, a total of three sampling periods T51, T53, and T55 are required for signal readout of the upper pixel 11 and the lower pixel 11 of the pixel block 111 in the n-th row. Therefore, according to the present embodiment, the sampling time can be shortened as compared with the comparative example, and as a result, the signal readout can be speeded up.

  In the comparative example, two horizontal scanning periods T63 and T65 are required for signal readout of the upper pixel 11 and the lower pixel 11 of the pixel block 111 in the n-th row. In the present embodiment, Only one horizontal scanning period T43 is required for signal readout of the upper pixel 11 and the lower pixel 11 of the pixel block 111 in the n-th row. Therefore, according to the present embodiment, it is possible to shorten the horizontal scanning period as compared with the comparative example, and also from this point, it is possible to speed up signal readout.

  As mentioned above, although each embodiment of this invention and its modification were demonstrated, this invention is not limited to these.

  For example, in the present invention, the same modification as that obtained in the second and third embodiments by modifying the first embodiment may be applied to the fourth embodiment. Good.

  In each of the embodiments described above, an amplifier (so-called column amplifier) may be provided for each vertical signal line 14, and the signal of the vertical signal line 14 may be amplified by the column amplifier and then stored in the storage capacitors C1 to C3. .

1 is a schematic block diagram showing a solid-state imaging device according to a first embodiment of the present invention. It is a circuit diagram which shows the image sensor in FIG. 3 is a timing chart illustrating an example of a read operation of the solid-state imaging device according to the first embodiment of the present invention. It is a circuit diagram which shows the image sensor used with the solid-state imaging device by the comparative example compared with the 1st Embodiment of this invention. It is a timing chart which shows the read-out operation | movement of the solid-state imaging device by the comparative example compared with the 1st Embodiment of this invention. It is a circuit diagram which shows the image sensor used with the solid-state imaging device by the 2nd Embodiment of this invention. It is a circuit diagram which shows the image sensor used with the solid-state imaging device by the 3rd Embodiment of this invention. It is a circuit diagram which shows the image sensor 41 used with the solid-state imaging device by the 4th Embodiment of this invention. It is a timing chart which shows an example of the read-out operation | movement of the solid-state imaging device by the 4th Embodiment of this invention. It is a circuit diagram which shows the image sensor used with the solid-state imaging device by the comparative example compared with the 4th Embodiment of this invention. It is a timing chart which shows the read-out operation | movement of the solid-state imaging device by the comparative example compared with the 4th Embodiment of this invention.

Explanation of symbols

1, 21, 31, 41 Image sensor (solid-state imaging device)
11 pixels 12 vertical scanning circuits 13 horizontal scanning circuits 14 horizontal signal lines 111 pixel blocks PD photodiodes AMP amplification transistors RES reset transistors TX transfer transistors SEL selection transistors FD floating diffusions C1 to C3 storage capacitors (signal storage units)
TV1 to TV3 first switch TH1 to TH3 second switch 16-1 to 16-3 horizontal signal line

Claims (8)

A plurality of pixels that are two-dimensionally arranged to photoelectrically convert incident light;
A vertical signal line provided corresponding to each column of the plurality of pixels and supplied with an output signal of the pixel in the corresponding column;
A signal accumulating unit for accumulating the supplied signals provided for each N (N is an integer of 3 or more) corresponding to each vertical signal line;
A first switch provided corresponding to each of the signal storage units, the first switch for turning on / off the supply of a signal from the vertical signal line corresponding to the corresponding signal storage unit to the signal storage unit; ,
A second switch provided corresponding to each of the signal storage units, the second switch for turning on and off the signal supply from the corresponding signal storage unit to a predetermined horizontal signal line;
Control means for controlling the plurality of pixels and the first and second switches;
With
For each of the vertical signal lines, the control unit assigns a number from 1 to N in an arbitrary order to each of the N signal storage units provided corresponding to the vertical signal lines, and the vertical signal lines N-1 pixels selected from the pixels in the column corresponding to are numbered from 1 to N-1 in any order, and m is an integer from 2 to N-1. In some cases, a signal corresponding to a signal on which dark output signals of pixels Nos. 1 to N−1 are superimposed is stored in the first signal storage unit, and the first signal storage unit stores the first signal storage unit. A signal corresponding to a signal obtained by superimposing a dark output signal of pixels No. 1 to m−1 and a light output signal of pixels No. m to No. N−1 is accumulated, and the No. N signal accumulation unit A signal corresponding to a signal in which the light output signals of pixels No. 1 to N−1 are superimposed is accumulated. Controls the plurality of pixels and said first switch,
A solid-state imaging device.   Each of the pixels includes a photoelectric conversion unit that generates and accumulates signal charges according to incident light, a charge-voltage conversion unit that receives the signal charges and converts the signal charges into a voltage, and a voltage according to the potential of the charge-voltage conversion unit An amplification unit that outputs a signal; a charge transfer unit that transfers charges from the photoelectric conversion unit to the charge-voltage conversion unit; a reset unit that resets the potential of the charge-voltage conversion unit; and a selection unit that selects the pixel The solid-state imaging device according to claim 1. A plurality of pixels that are two-dimensionally arranged to photoelectrically convert incident light;
A vertical signal line provided corresponding to each column of the plurality of pixels and supplied with an output signal of the pixel in the corresponding column;
A signal accumulating unit for accumulating the supplied signals provided for each N (N is an integer of 3 or more) corresponding to each vertical signal line;
A first switch provided corresponding to each of the signal storage units, the first switch for turning on / off the supply of a signal from the vertical signal line corresponding to the corresponding signal storage unit to the signal storage unit; ,
A second switch provided corresponding to each of the signal storage units, the second switch for turning on and off the signal supply from the corresponding signal storage unit to a predetermined horizontal signal line;
Control means for controlling the plurality of pixels and the first and second switches;
With
Each of the pixels includes a photoelectric conversion unit that generates and accumulates signal charges according to incident light, a charge-voltage conversion unit that receives the signal charges and converts the signal charges into a voltage, and a voltage according to the potential of the charge-voltage conversion unit An amplification unit that outputs a signal; a charge transfer unit that transfers charges from the photoelectric conversion unit to the charge voltage conversion unit; a reset unit that resets the potential of the charge voltage conversion unit; and a selection unit that selects the pixel. And
The plurality of pixels form a pixel block for every N−1 pixels in which the photoelectric conversion units are sequentially arranged in a column direction,
For each pixel block, the N-1 pixels belonging to the pixel block share a set of the charge voltage conversion unit, the amplification unit, the reset unit, and the selection unit,
For each of the vertical signal lines, the control unit assigns a number from 1 to N in an arbitrary order to each of the N signal storage units provided corresponding to the vertical signal line, and the vertical signal line N-1 pixels of the selected pixel block among the pixels in the column corresponding to are numbered from 1 to N-1 in any order, and m is an integer from 2 to N-1 In the first signal storage unit, the signal charges of the pixel blocks 1 to N−1 are not transferred to the charge-voltage conversion unit of the pixel block. A signal corresponding to the output signal is accumulated, and the signal charge of the pixels from No. 1 to m−1 is not transferred to the charge voltage conversion unit of the pixel block in the m-th signal accumulation unit and the m-th signal accumulation unit. To N-1 pixel signal charges A signal corresponding to the output signal of the pixel block in a state transferred to the charge-voltage conversion unit of the pixel block is accumulated, and the Nth signal accumulation unit stores pixels Nos. 1 to N−1. Controlling the plurality of pixels and the first switch so that a signal corresponding to an output signal of the pixel block in a state where the signal charge of the pixel block is transferred to the charge-voltage conversion unit of the pixel block is accumulated.
A solid-state imaging device.   With respect to each of the vertical signal lines, signals from the N signal storage units provided corresponding to the vertical signal lines pass through the second switches respectively corresponding to the N signal storage units. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is supplied to different horizontal signal lines.   5. The solid-state imaging according to claim 4, wherein the control unit controls the second switch so that signals are simultaneously supplied from the N signal storage units to the different horizontal signal lines. 6. apparatus. The number of the horizontal signal lines is N,
For each of the vertical signal lines, signals from the N signal storage units provided corresponding to the vertical signal lines are passed through the second switches respectively corresponding to the N signal storage units. 6. The solid-state imaging device according to claim 4, wherein the solid-state imaging device is supplied to any one of the N horizontal signal lines. The vertical signal lines provided corresponding to the columns of the plurality of pixels are divided into a plurality of groups.
The horizontal signal line is provided for each group of the vertical signal lines by N lines corresponding to the group,
For each of the vertical signal lines belonging to the group, the signals from the N signal storage units provided corresponding to the vertical signal lines correspond to the N signal storage units, respectively. 6. The signal is supplied to any one of the N horizontal signal lines provided corresponding to the group via the second switch. The solid-state imaging device described.   Signal processing for obtaining signals corresponding to the difference between the signal from the k-th signal storage unit and the signal from the k + 1-th signal storage unit, where k is an integer from 1 to N−1 The solid-state imaging device according to claim 1, further comprising means.

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