JP2009033100A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which does not use Sn-Pb based solder and which has less warpages. <P>SOLUTION: The semiconductor device 1 includes a circuit board 2, electronic component 3, and a lead-free soldered jointing member 4. The circuit board 2 has a circuit board side electrode 5. The electronic component 3 is mounted on the circuit board 2. The lead-free soldered jointing member 4 consists of metal other than lead, and connects the circuit board side electrode 5 of the circuit board 2 and the electronic component 3. A thermal expansion suppressing member 6 for suppressing the thermal expansion of the circuit board 2 is provided in the circuit board 2. Moreover, a stress-relaxing member 7 for relaxing the stresses generated in the circuit board side electrode 5 of the circuit board 2 is provided at the circuit board side electrode 5. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a structure of a semiconductor device composed of a circuit board and an electronic component.

The semiconductor device is composed of a circuit board and an electronic component placed on the circuit board, and the circuit board and the electronic component are joined by solder. The circuit board and the electronic component connected to the solder are thermally expanded by the heat supplied to the solder. Usually, an electronic component contains silicon as a substrate, and the circuit substrate has a thermal expansion coefficient (15 × 10 ⁻⁶ [/ ° C.]) larger than that of silicon (3 × 10 ⁻⁶ [/ ° C.]). Many resin materials are used. When members having different thermal expansion coefficients are joined together and a temperature change is given to the joined materials, the members warp. The greater the difference in thermal expansion coefficient between members and the greater the amount of temperature change, the greater the amount of warping of the member. A semiconductor device is used by connecting an electronic component and a circuit board with solder and then cooling to room temperature. For this reason, the semiconductor device is warped due to a difference in thermal expansion coefficient between the circuit board and the electronic component.

  In order to eliminate this warpage, it is widely practiced to suitably relieve the stress generated in the circuit board and the electronic component by using Sn-Pb solder that is easily deformed (that is, stress is easily relieved) as a bonding material. I have been.

For example, the semiconductor device disclosed in Patent Document 1 (see FIG. 4) includes a semiconductor element 101 bonded to the disk 102 by the Sn—Pb solder 105 and an insulation bonded to the disk 102 by the Sn—Pb solder 105. And a substrate 103. A Cu—C material is used for the disk 102, and the thermal expansion coefficient is brought close to that of the semiconductor element 101 or the insulating substrate 103 by changing the content of carbon fiber. Further, Cu plating having a function of relieving stress generated inside the disk 102 is applied to the surface of the disk 102. By configuring the semiconductor device as described above, it is possible to eliminate the warpage of the entire semiconductor device that occurs based on the difference in thermal expansion coefficient between the semiconductor element 101 and the insulating substrate 103.
Japanese Patent Laid-Open No. 57-130441

  However, the semiconductor device disclosed in Patent Document 1 has the following problems. That is, there is a problem that Sn—Pb solder cannot be used as a bonding material. The reason is that Pb (lead) is harmful to the human body, and in recent years, regulations are severe in the European Union, China, etc., and the use is restricted in Japan.

  Due to the above circumstances, lead-free solder that does not contain lead is used for the joining of a conventional typical semiconductor device having an electronic component and a circuit board on which the electronic component is placed.

  However, lead-free solder is usually harder than Sn—Pb solder, and is not easily deformed even when subjected to a force (ie, stress relaxation is difficult). The heat supplied to the solder from an external heat source is conducted to the circuit board and the electronic component, so that the circuit board and the electronic component are thermally expanded. However, since the thermal expansion coefficient of the circuit board (for example, the constituent material is resin) is larger than that of the electronic component (for example, the constituent material is silicon), the thermal expansion amount of the circuit board is larger than the thermal expansion amount of the electronic component. Also grows. That is, a difference in thermal expansion occurs between the circuit board and the electronic component. In addition, if there is no non-uniformity in the amount of heat supplied to a part of the circuit board on the side where the electronic component is placed and the other part of the circuit board on the opposite side, the circuit board expands uniformly, Try to transform. However, deformation accompanying thermal expansion of a part of the circuit board on the side where the electronic board is placed is restrained by the lead-free solder that is difficult to deform. For this reason, a part of the circuit board has a smaller amount of thermal expansion than the other part of the circuit board on the opposite side. Therefore, a difference in thermal expansion occurs in the circuit board. Furthermore, since deformation due to thermal expansion of the circuit board and the electronic component is restrained by lead-free solder that is difficult to deform, the difference in thermal expansion amount between the circuit board and the electronic component is not reduced. Therefore, the circuit board is warped to be bent toward the electronic component due to the difference in thermal expansion between the circuit board and the electronic component and the difference in thermal expansion within the circuit board.

  In addition, lead-free solder usually has a melting point about 40 ° C. higher than that of Sn—Pb solder. Thus, in order to melt the lead-free solder, it is necessary to increase the amount of heat supplied from the external heat source to the lead-free solder as compared with the case of Sn—Pb solder. Therefore, when a part of this heat is conducted to the circuit board connected to the lead-free solder, the internal temperature of the circuit board rises in proportion to the amount of heat conduction. This temperature rise in the circuit board causes the circuit board to thermally expand. Therefore, this thermal expansion of the circuit board further increases the warp previously generated on the circuit board. When this curved circuit board is cooled to room temperature, since the circuit board is an elastic body, a restoring force is exerted on the circuit board to return to the original shape (a shape without warping). However, since lead-free solder has a property that it is difficult to deform, the deformation of the circuit board is restrained by the lead-free solder, and the circuit board cannot return to its original shape. Thereby, the curvature of a circuit board will be maintained. As a result, the entire semiconductor device including the circuit board is greatly warped even at room temperature. A semiconductor device having a large warp causes a connection failure when it is provided with electrodes and further connected to other components such as a circuit board with solder or the like.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device in which Sn—Pb solder is not used and warping is small.

  A semiconductor device of one embodiment of the present invention includes a circuit board having electrodes, an electronic component placed on the circuit board, and a metal other than lead, and connects the electrode of the circuit board and the electronic component. A thermal expansion suppressing means for suppressing thermal expansion of the circuit board is provided in the circuit board, and a stress relaxation means for relaxing stress generated in the electrode of the circuit board is provided on the electrode. Is provided.

  According to the present invention, since the thermal expansion suppressing means is provided in the circuit board, the warp of the semiconductor device due to the difference in the thermal expansion amount in the circuit board is reduced. Furthermore, since the stress relaxation means is provided on the electrode of the circuit board, the warp of the semiconductor device due to the difference in thermal expansion between the circuit board and the electronic component is reduced. Therefore, the Sn—Pb solder is not used by the connecting means made of a metal other than lead, the thermal expansion suppressing means, and the stress relaxing means, and a semiconductor device with little warpage can be provided.

  The best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention. The semiconductor device 1 includes a circuit board 2, an electronic component 3, and a lead-free solder connecting member 4 made of a metal other than lead.

  The circuit board 2 has a first surface 21 on which the electronic component 3 is placed and a second surface 22 located on the opposite side of the first surface 21. Since the second surface 21 and the second surface 22 are parallel, the circuit board 2 has a thin plate shape. Further, the circuit board 2 includes a board-side electrode 5 and a thermal expansion suppressing member 6 that functions as a thermal expansion suppressing unit that suppresses thermal expansion of the circuit board 2.

  The electronic component 3 includes an electronic circuit element including a semiconductor element 8 that functions as an active element such as a transistor, a field effect transistor, a thyristor, a diode, and a light emitting diode, and a component electrode 9. The electronic component 3 is placed on the circuit board 2. The component electrode 9 of the electronic component 3 is joined to the board-side electrode 5 of the circuit board 2 by a lead-free solder connection member 4. Furthermore, electric power is supplied to the semiconductor element 8 from an external power source (not shown) via the substrate-side electrode 5 of the circuit board 2 and the component electrode 9 of the electronic component 3. Silicon is used for the semiconductor element 8. On the other hand, a resin material having a thermal expansion coefficient larger than that of silicon is used for the circuit board 2.

  The substrate-side electrode 5 has a recess having an inner space that opens toward the lead-free solder connection member 4. This recess is formed by a substantially U-shaped surface 51 of the substrate-side electrode 5. The opened inner space is filled with a stress relaxation member 7 that functions as a stress relaxation means for relaxing the stress generated in the substrate-side electrode 5. The board-side electrode 5 is provided on the first surface 21 of the circuit board 2 and is electrically connected to the component electrode 9 of the electronic component 3 through the lead-free solder connection member 4.

  The stress relaxation member 7 has conductivity and is a filling member that is electrically connected to the lead-free solder connection member 4. Further, the Young's modulus of the stress relaxation member 7 is lower than the Young's modulus of the substrate side electrode 5. Therefore, the stress relaxation member 7 is more easily deformed than the substrate side electrode 5. The stress relaxation member 7 is preferably made of a solder material such as Sn—In, Sn—Cu, Sn—Zn, or Sn—Bi, whose melting point is as low as that of Sn—Pb solder. Alternatively, the stress relaxation member 7 is preferably made of a viscoelastic polymer (that is, elastomer) material that exhibits conductivity when a metal is mixed therein. The lead-free solder connection member 4 is thermally expanded by heat supplied from an external heat source. Along with the thermal expansion of the lead-free solder connection member 4, stress is generated in the substrate-side electrode 5 connected to the lead-free solder connection member 4 so as to resist the thermal expansion. However, since the stress relaxation member 7 has a Young's modulus lower than that of the substrate-side electrode 5, it is more likely to be deformed than the substrate-side electrode 5. Since the stress relaxation member 7 deforms more easily than the substrate side electrode 5, the conventional stress relaxation member 7 is not provided, and the thermal expansion of the lead-free solder connection member 4 directly deforms the substrate side electrode 5. The stress generated in the substrate-side electrode 5 is relieved compared to the case where prompting is promoted. Therefore, the amount of deformation of the substrate side electrode 5 is reduced by relaxing the stress generated in the substrate side electrode 5. Therefore, the deformation amount of the circuit board 2 on the electronic component 3 side having the board-side electrode 5 is also reduced. Therefore, the difference in deformation amount between the circuit board 2 on the electronic component 3 side and the electronic component 3 is reduced as compared with the prior art. Therefore, the warp of the semiconductor device 1 in a heated state can be reduced. When the hot semiconductor device 1 is cooled to room temperature, the circuit board 2 is an elastic body, so that the circuit board 2 has a restoring force to return to the original shape (a shape without warping). Since the stress relaxation member 7 has the property of being easily deformed even at room temperature, it can accept deformation due to the restoring force of the substrate-side electrode 5 in the circuit substrate 2. Therefore, the circuit board 2 can be restored to its original shape, and the warpage of the circuit board 2 at room temperature due to the difference in thermal expansion between the circuit board 2 and the electronic component 3 can be reduced.

  The thermal expansion suppressing member 6 has a thermal expansion coefficient lower than the thermal expansion coefficient of the circuit board 2 and, for example, silicon can be suitably used. The thermal expansion suppressing member 6 is provided as a plate-like member in the circuit board 2 in a direction orthogonal to the thickness direction of the circuit board 2. The thermal expansion suppressing member 6 is disposed in the circuit board 2 at a position closer to the second surface 22 than the first surface 21. Furthermore, the thermal expansion suppressing member 6 is not limited to a single-layer plate, and may be a plate-like member composed of a plurality of layers of plates in which another plate is placed on one plate. A material having a Young's modulus higher than the Young's modulus of the circuit board 2 may be used at the position of the thermal expansion suppressing member 6 regardless of the thermal expansion coefficient. In this case, high stress is generated in the stress relaxation member 7 in an attempt to increase the warp of the semiconductor device 1 due to the difference in thermal expansion coefficient between the electronic component 3 and the circuit board 2. However, since stress relaxation generally tends to occur as the stress increases, an increase in warpage of the circuit board 2 can be suppressed. Further, the amount of warpage of the semiconductor device 1 can be adjusted by changing the thickness of the plate-like member or by shifting the position of the plate-like member in the thickness direction (see the shift amount 10 in FIG. 1). it can. When the electronic component 3 is placed on the circuit board 2 and the circuit board 2 and the electronic component 3 are joined by the lead-free solder connection member 4, the circuit board is heated by heat supplied to the lead-free solder connection member 4 from an external heat source. 2 expands. However, the thermal expansion suppressing member 6 having a thermal expansion coefficient smaller than that of the circuit board 2 is provided at a position closer to the second surface 22 than the first surface 21 in the circuit board 2. Thereby, under the same temperature difference, the thermal expansion amount of the thermal expansion suppressing member 6 is smaller than the thermal expansion amount of the circuit board 2. Furthermore, the deformation of the circuit board 2 on the second surface 22 side, which has a large amount of thermal expansion, is restrained by the thermal expansion suppressing member 6. Therefore, the thermal expansion amount of the circuit board 2 on the second surface 22 side is reduced as compared with the case where the conventional thermal expansion suppressing member 6 is not provided. Therefore, the difference in the amount of thermal expansion between a part of the circuit board 2 on the first surface 21 side and the other part of the circuit board 2 on the second surface 22 side is reduced. The warp that curves toward the electronic component 3 is reduced. Therefore, it is possible to reduce the warp of the semiconductor device 1 due to the difference in the amount of thermal expansion in the circuit board 2 during the hot time.

  The lead-free solder connection member 4 functions as a connection means for connecting the substrate-side electrode 5 of the circuit board 2 and the component electrode 9 of the electronic component 3. For the lead-free solder connecting member 4, a solder of Sn-3Ag-0.5Cu composition that is generally widely used is used. The solder having this composition is harder than the Sn—Pb solder, and is not easily deformed even when a force is applied (that is, it is difficult to relax the stress).

FIG. 2 is a stress relaxation test comparing the ease of solder deformation due to external force applied to a conventional representative Sn-37Pb solder and that of Sn-3Ag-0.5Cu lead-free solder defined in the embodiment of the present invention. Is the result of In the stress relaxation test, the tensile test was performed until the strain reached 1.5% at room temperature under a strain rate of 10 ⁻³ [1 / sec], and then the crosshead was stopped to measure the stress. Here, the strain is a ratio obtained by dividing the elongation amount by the original length, and the stress is a ratio obtained by dividing the load by the cross-sectional area. The stress after 6 hours is 5 [MPa] for Sn-37Pb solder, while 15 [MPa] for Sn-3Ag-0.5Cu lead-free solder, 3 times higher stress remains. Recognize. For this reason, when the electronic component 3 and the circuit board 2 are connected by the lead-free solder connecting member 4 using Sn-3Ag-0.5Cu lead-free solder, the solder is not easily deformed by force. For this reason, the semiconductor device 1 is more likely to be warped than the conventional semiconductor device.

  In order to solve this problem, in the semiconductor device 1 according to the embodiment of the present invention, Sn—In, Sn—Cu, Sn—Zn, Sn—Bi solder or the like is used as the stress relaxation member 7. Yes. By performing the stress relaxation test, a stress relaxation material having a characteristic of low residual stress is selected. By doing so, the semiconductor device 1 is warped due to the difference in thermal expansion between the electronic component 3 and the circuit board 2. However, since the stress relaxation member 7 is deformed by receiving a force, the warp of the semiconductor device 1 is remarkably reduced as compared with the related art. In order to generate the stress relaxation most efficiently in the stress relaxation member 7, the neutral surface of the warp of the semiconductor device 1 can be adjusted so as to be within the height range of the lead-free solder member 9. did.

The state of warpage or neutral surface of the semiconductor device 1 was examined by thermal stress analysis using general-purpose finite element method analysis software or the like.
(Examples 1 and 2)
Next, the structure of the embodiment of the present invention will be described using specific examples.

An example in which the semiconductor element 18 is silicon and the lead-free solder connecting member 14 is Sn-Ag-Cu solder is shown in FIG. An Sn—In solder was used for the stress relaxation member 17, and bare silicon was used for the thermal expansion suppression member 16. Using the general-purpose finite element method analysis software ANSYS, the warpage of the semiconductor device 11 was calculated when the electronic component 13 and the circuit board 12 were connected at a melting point of 220 ° C. of Sn—Ag—Cu solder and cooled to room temperature. . The shift amount 20 was adjusted so that this warpage was minimized. Note that the finite element method analysis software used for the stress simulation of the thermal stress analysis is not limited to ANSYS. That is, I-DEAS, N
Finite element analysis software such as astran, ABAQUS, MARC, Pro / ENGINEER may be used.

  FIG. 5 is an analysis model for finite element calculation. It is divided into about 6000 by a minute area called an element. The width of the thermal expansion suppressing member 16 is the same as that of the semiconductor element 18, and the thickness is 1/5 of the semiconductor element 18. The center point of the lower surface of the circuit board 12 was set as a warp reference point 21 and restrained so as not to move in the vertical direction.

  FIG. 6 shows an example in which the warpage of the semiconductor device 11 that occurs when the temperature of the entire semiconductor device 11 is lowered from the melting point of the solder to room temperature is calculated using general-purpose finite element method analysis software ANSYS. A modified diagram 22 showing the amount of warpage in a contour map is shown by superposing an outline diagram 23 before the deformation. In order to make it easy to understand, the amount of deformation was displayed five times the actual amount. The warp of the circuit board 12 is as small as about 60 μm.

  For comparison, the amount of warpage in the conventional case in which neither the stress relaxation member 17 nor the thermal expansion suppressing member 16 is used is shown in FIG. Similar to FIG. 6, the amount of warpage of the semiconductor device 11 that occurs when the temperature of the entire semiconductor device 11 is lowered from the melting point of the solder to room temperature is shown by a contour map. The amount of deformation is displayed 5 times the actual amount. The circuit board 12 warps convexly, and the end of the circuit board 12 has the largest warpage, which is about 460 μm.

  FIG. 8 is an explanatory diagram of Embodiment 2 of the present invention. As in the first embodiment (FIG. 6), Sn—In solder is used for the stress relaxation member 17 and bare silicon is used for the thermal expansion suppressing member 16, but the thermal expansion suppressing member 16 is attached to the circuit board 12. It is an example in the case of providing in the thickness center. Similar to FIG. 6, the amount of warpage of the semiconductor device 11 that occurs when the temperature of the entire semiconductor device 11 is lowered from the melting point of the solder to room temperature is shown by a contour map. The amount of deformation is displayed 5 times the actual amount. The circuit board 12 is warped convexly as in the prior art (FIG. 7). At the end of the circuit board 12 with the largest warpage, the warpage amount was about 280 μm. Compared to the prior art (FIG. 7), the warpage of the circuit board 12 is reduced by 40%. It can be seen that warpage of the circuit board 12 can be reduced by using Sn—In solder for the stress relaxation member 17 and bare silicon for the thermal expansion suppressing member 16. The warp of the circuit board 12 varies depending on the position in the thickness direction where the thermal expansion suppressing member 16 is provided. In Example 1 (FIGS. 5 and 6), the shift amount 20 is adjusted so that the warpage is minimized. In the first embodiment, as shown in FIG. 5, the circuit board 12 is shifted by 30 μm downward from the thickness center. This corresponds to 1/3 of the thickness of the circuit board 12. By doing so, the warpage amount of the circuit board 12 is reduced to 1/8 in the first embodiment as compared with the conventional example.

As described above, the stress relaxation means is provided on the electrode, and the thermal expansion suppressing means is provided at an appropriate position in the circuit board, whereby the warpage of the circuit board can be greatly reduced.
(Examples 3 and 4)
Next, the structure of the embodiment of the present invention will be described using another example.

FIG. 9 shows a semiconductor device in which a rubber-based resin is used for the stress relaxation member 24 and Si ₃ N ₄ having a small thermal expansion coefficient is used for the thermal expansion suppressing member 25. This is an analysis model for finite element calculation when a reinforcing resin called fill is filled. It is divided into about 7000 elements. The width of the thermal expansion suppressing member 25 is substantially the same as that of the electronic component 13, and the thickness is 1/5 of the semiconductor element 18. The reinforcing resin 26 is filled up to the end of the electronic component 13 and forms a fillet shape with the circuit board 12 at the end due to wettability.

  FIG. 10 shows an example in which the warpage of the semiconductor device 11 that occurs when the temperature of the entire semiconductor device 11 is lowered from the melting point of the solder to room temperature is calculated. The deformation diagram 22 in which the amount of warpage is shown in a contour map is superimposed on the outline diagram 23 before the deformation, and the deformation amount is displayed five times the actual amount. The semiconductor device 11 is generally warped convexly, and the warp of the circuit board 12 is the largest at the end, and is about 90 μm.

  For comparison, in Example 3 (FIGS. 9 and 10), the amount of warpage in the conventional case in which neither the stress relaxation member 24 nor the thermal expansion suppression member 25 is used is shown in FIG. The amount of warpage of the semiconductor device 11 that occurs when the temperature of the entire semiconductor device 11 is lowered from the melting point of the solder to room temperature is shown by a contour map, and the amount of deformation is shown five times the actual amount. The circuit board 12 warps in a convex manner, and the end of the circuit board 12 has the largest warpage, which is about 350 μm.

  FIG. 12 is an explanatory diagram of Embodiment 4 of the present invention. In Example 3 (FIG. 9, FIG. 10), it is an analysis model for finite element calculation when the width | variety of the thermal expansion suppression member 25 is made the same not with the electronic component 13 but with the semiconductor element 18. FIG.

FIG. 13 is an example of calculating the warpage of the semiconductor device 11 that occurs when the temperature of the entire semiconductor device 11 is lowered from the melting point of the solder to room temperature in the case of the fourth embodiment of the present invention. The deformation diagram 22 in which the amount of warpage is shown in a contour map is superimposed on the outline diagram 23 before the deformation, and the deformation amount is displayed five times the actual amount. The semiconductor device 11 is generally warped convexly, and the warp of the circuit board 12 is the largest at the end, being about 140 μm. Compared to the conventional case (FIG. 11), the warp of the circuit board 12 is reduced to less than half. Even when the lead-free solder connecting member 14 is filled with a reinforcing resin by using a rubber-based resin for the stress relaxation member 24 and Si ₃ N ₄ for the thermal expansion suppressing member 25, the circuit It can be seen that the warpage of the substrate 12 can be reduced. The warp of the circuit board 12 varies depending on the width at which the thermal expansion suppressing member 25 is provided.

  In Example 3 (FIGS. 9 and 10), the width of the thermal expansion suppressing member 25 is adjusted so that the warpage is minimized. In Example 3, as shown in FIG. 9, the width of the thermal expansion suppressing member 25 is made substantially the same as that of the electronic component 13. By doing so, the warpage amount of the circuit board 12 is reduced to 1/3 or less in the third embodiment as compared with the conventional example (FIG. 11).

  As described above, the stress relaxation means is provided on the electrode, and the thermal expansion suppressing means is provided at an appropriate position in the circuit board, whereby the warpage of the circuit board can be greatly reduced.

It is sectional drawing which shows the semiconductor device which concerns on one Embodiment of this invention. It is a figure explaining the material test result of the stress relaxation member of the semiconductor device which concerns on one Embodiment of this invention. It is sectional drawing which shows the semiconductor device which concerns on one Example of this invention. It is sectional drawing which shows the principal part of the conventional semiconductor device. It is explanatory drawing of the finite element method calculation of the semiconductor device which concerns on Example 1 of this invention. It is explanatory drawing of the finite element method calculation of the semiconductor device which concerns on Example 1 of this invention. It is explanatory drawing of the finite element method calculation of the conventional semiconductor device. It is explanatory drawing of the finite element method calculation of the semiconductor device which concerns on Example 2 of this invention. It is explanatory drawing of the finite element method calculation of the semiconductor device which concerns on Example 3 of this invention. It is explanatory drawing of the finite element method calculation of the semiconductor device which concerns on Example 3 of this invention. It is explanatory drawing of the finite element method calculation of the conventional semiconductor device. It is explanatory drawing of the finite element method calculation of the semiconductor device which concerns on Example 4 of this invention. It is explanatory drawing of the finite element method calculation of the semiconductor device which concerns on Example 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 11 Semiconductor device 2, 12 Circuit board 3, 13 Electronic component 4, 14 Lead-free solder connection member 5, 15 Substrate side electrode 6 Thermal expansion suppression member 7 Stress relaxation member 21 Warp reference point 22 Deformation figure 23 Before deformation Outline diagram 24 Rubber resin 25 Si ₃ N ₄
26 Resin for reinforcement

Claims (7)

A circuit board having electrodes;
An electronic component mounted on the circuit board;
A connection means comprising a metal other than lead, and connecting the electrode of the circuit board and the electronic component;
Have
Thermal expansion suppression means for suppressing thermal expansion of the circuit board is provided in the circuit board, and stress relaxation means for relaxing stress generated in the electrode is provided in the electrode.
Semiconductor device. The thermal expansion suppression means is a plate-like member provided in a direction orthogonal to the thickness direction of the circuit board,
The plate-like member has a thermal expansion coefficient lower than the thermal expansion coefficient of the circuit board, and is disposed at a position close to the surface on the opposite side of the surface on which the electronic component is placed in the circuit board. Being
The semiconductor device according to claim 1.   The semiconductor device according to claim 2, wherein the plate member is made of a material having a Young's modulus higher than that of the circuit board.   The semiconductor device according to claim 2, wherein the plate-like member includes a single layer or a plurality of layers. The electrode has a recess having an inner space opened toward the connection means,
The stress relaxation means is a conductive filling member filled in the inner space,
The filling member is electrically connected to the connecting means and has a Young's modulus lower than that of the electrode.
The semiconductor device according to claim 1.   The semiconductor device according to claim 5, wherein the filling member is made of a Sn—In based, Sn—Cu based, Sn—Zn based or Sn—Bi based solder material.   The semiconductor device according to claim 5, wherein the filling member is made of a viscoelastic polymer material.