JP2009032930A - Wafer carrier and wafer-backside inspection method using this - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To eliminate such troubles as defects in wafer on its handling, particle adhesion, contamination and the like when the wafers are inspected and analyzed on the quality of their backsides, and further to reduce time and labor required for the inspection and the analysis on the back of the wafer. <P>SOLUTION: The upper part of FOUP 11 has the same configuration as that of the bottom of FOUP to be installed and fitted to the production equipment of a semiconductor. The wafer can be made inside out only by setting the FOUP 11 upside down because the FOUP 11 is symmetrically structured up and down, when the wafer is required to set inside out during its processing step. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wafer carrier used for transporting and storing semiconductor wafers, and more particularly to a hermetic wafer carrier called FOUP. “FOUP” is an abbreviation for Front Open Unified Pod (front open integrated pod), and refers to a wafer carrier for 300 mm wafers conforming to the SEMI (Semiconductor Equipment and Materials Institute) standard. Furthermore, the present invention relates to a wafer back surface inspection method for inspecting a surface opposite to a surface to be processed of a wafer.

  In the semiconductor device manufacturing process, defects such as foreign matter are directly related to the yield on the wafer surface that forms the integrated circuit, so the wafer surface defect inspection system is used to inspect the integrated circuit part defects frequently. ing. However, an inspection apparatus that directly inspects the back surface of a wafer having an integrated circuit formed on the front surface is not widely used. Therefore, in order to diagnose yield problems due to backside defects, prepare a silicon wafer with a mirror-finished front and back surface as an evaluation wafer, and turn the evaluation wafer manually and turn it over to the wafer carrier. Load it. Then, after processing the evaluation wafer in a semiconductor production facility suspected of causing the defect, a technique is generally used in which the front and back sides of the evaluation wafer are manually returned again and inspected and analyzed by a wafer inspection apparatus. It has been.

  Also, wafer backside inspection and metal contamination analysis by the above methods are mainly used when there is a possibility of foreign matter contamination or metal contamination from the semiconductor production equipment side to the wafer backside, such as when starting up production equipment or immediately after maintenance. Has been done.

  On the other hand, the semiconductor device manufacturing process proceeds in a clean room with high cleanliness, and an open-type wafer carrier has been widely used for storing and transporting wafers. However, in recent clean rooms, high cleanliness is maintained only inside the process equipment and some equipment related to the process equipment in order to reduce cleanroom maintenance costs, and relatively low cleanliness is maintained in other areas. ing. In areas where such low cleanliness is maintained, hermetic wafer carriers are used to protect the wafers from atmospheric contaminants and chemical contamination. As a typical example of such a sealed wafer carrier, there is one called FOUP (Patent Documents 1, 2, etc.).

  A conventional wafer backside inspection and backside analysis method in a mini-environment semiconductor production line using FOUP will be described below.

  FIG. 10 shows a work flow of wafer back surface inspection / analysis, and FIGS. 11 to 14 show details of main operations of FIG.

  First, the operator carries the FOUP 12 loaded with the silicon wafer 1 whose front and back surfaces are mirror-finished to a wafer transferable area in the clean room (step S1 in FIG. 10). The “wafer transferable area” as used herein refers to an area in which a part of the clean room is maintained at the same level of cleanliness as the inside of the FOUP. That is, since the inside of the FOUP has a higher cleanliness than the atmosphere in the clean room, in order to transfer a wafer from the FOUP, it is necessary to perform a transfer operation in an environment having the same degree of cleanliness as that inside the FOUP. For this reason, a wafer transferable area is provided in the clean room.

  Next, as shown in FIG. 11, an operator takes out the wafer 1 from the FOUP 12 with a wafer handling jig such as vacuum tweezers, inverts the front and back of the wafer 1, and loads the FOUP 12 again. (Step S2 in FIG. 10). That is, the wafer 1 is loaded into the FOUP 12 with the wafer back surface 1a facing upward as shown in FIG. Next, the operator transports the FOUP 12 from the wafer transferable area to the inspection target semiconductor production facility (step S3 in FIG. 10).

  Then, as shown in FIG. 12, the surface to be processed (wafer back surface 1a) of the wafer 1 is processed in the semiconductor production facility to be inspected (step S4 in FIG. 10), and then the operator transfers the FOUP 12 to the wafer again. Transport to the possible area (step S5 in FIG. 10). Next, in the wafer transferable area, the operator takes out the wafer 1 from the FOUP 12 with a wafer handling jig such as vacuum tweezers as shown in FIG. 13, puts the front and back back into the FOUP 12 (FIG. 10). Step S6). That is, the wafer 1 is loaded into the FOUP 12 with the wafer surface 1b facing upward as shown in FIG.

Next, the operator transports the FOUP 12 from the wafer transferable area to the wafer surface evaluation inspection / analysis apparatus, and as shown in FIG. The opposite surface (wafer surface 1b) is evaluated (step S7 in FIG. 10). As described above, it is possible to investigate the influence of contamination transfer to the wafer back surface (surface opposite to the surface to be processed) by the inspection target semiconductor production facility and the occurrence of defects on the wafer back surface.
Japanese Unexamined Patent Publication No. 2005-150706 Japanese Patent Laid-Open No. 2001-085507

  However, since the conventional wafer backside inspection / analysis method requires the wafer for evaluation to be turned upside down manually using vacuum tweezers, the wafer can be dropped and destroyed during wafer handling, or the wafer can be FOUPed. Problems such as excessive particles adhering to the wafer before evaluation due to contact with the outer wall and damage to the wafer are likely to occur. Such a defect tends to increase as the wafer size becomes larger because it becomes difficult to manually handle the wafer such as vacuum tweezers.

  Also, in semiconductor production lines that employ FOUP as a wafer carrier, the above-mentioned manual wafer handling is limited to a specific wafer transferable area that is maintained and managed at the same level of air cleanliness as in FOUP. End up. Therefore, it is indispensable to transport the FOUP between the semiconductor production equipment and wafer inspection / analysis equipment to be inspected and the wafer transferable area, and to manually reverse the front and back of the wafer. There was a problem that the analysis work took time and labor.

  Therefore, the present invention is to solve at least one of the problems of the background art. That is, one of the objects of the present invention is to eliminate problems such as wafer breakage, particle adhesion, and contamination during wafer handling during wafer backside inspection and backside analysis. A further object is to reduce the time and labor required for back surface inspection and analysis.

  The present invention relates to a wafer carrier called FOUP, which is a wafer carrier that horizontally accommodates semiconductor wafers and has a structure that is installed and fixed in a semiconductor production facility, and is symmetrical with the structure of the bottom surface on the upper surface of the wafer carrier. It has a structure.

  Further, the present invention uses a semiconductor production facility and a wafer inspection apparatus that use a wafer carrier called FOUP that horizontally accommodates semiconductor wafers, and a processing surface of a semiconductor wafer processed in the semiconductor production facility to be inspected. A wafer back surface inspection method in which the opposite surface is inspected by the wafer inspection apparatus, wherein the inspection is performed as follows.

  That is, as the wafer carrier, a wafer carrier having a structure that is installed and fixed on a semiconductor production facility on the bottom surface and a structure that is vertically symmetrical with the structure of the bottom surface is prepared. Next, the wafer carrier containing the semiconductor wafer is turned upside down. Further, a semiconductor wafer is introduced from the inverted wafer carrier into a semiconductor production facility to be inspected without changing the front and back sides, and the surface to be processed of the semiconductor wafer is processed in the semiconductor production facility. Further, the processed semiconductor wafer is accommodated in an inverted wafer carrier without changing the front and back of the semiconductor wafer, and the wafer carrier is then turned upside down. Thereafter, the semiconductor wafer is introduced into the wafer inspection apparatus from the wafer carrier whose upper and lower sides are returned to the original state without changing the front and back surfaces, and the surface opposite to the surface to be processed of the semiconductor wafer is inspected by the wafer inspection apparatus.

  As described above, in the present invention, the same structure as that of the bottom surface of the FOUP that is installed and fixed in the semiconductor production facility is provided on the top surface of the FOUP to form a vertically symmetrical FOUP. Sometimes, the front and back of the wafer can be reversed simply by reversing the top and bottom of the FOUP. Therefore, manual wafer reversing work using vacuum tweezers is not necessary, and problems such as wafer breakage, particle adhesion, and contamination during wafer handling are solved. In addition, frequent reciprocal transportation between the wafer transfer area and the semiconductor production equipment and wafer surface inspection / analysis equipment can be eliminated, reducing the time and labor required for backside inspection / analysis. .

  As described above, according to the present invention, in wafer backside inspection and backside analysis, in wafer backside inspection and backside analysis, problems such as wafer breakage, particle adhesion, and contamination during wafer handling can be solved. Furthermore, the time and labor required for the backside inspection and analysis work can be reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  1, 2, 3, and 4 are external views showing an embodiment of the wafer carrier of the present invention. FIG. 1 is a front view, FIG. 2 is a side view, FIG. 3 is a top view, and FIG. Is shown. FIG. 5 is an explanatory diagram of the uppermost and lowermost wafer loading positions in the wafer carrier of this embodiment.

  In this embodiment, a φ300 mm wafer FOUP 11 is illustrated. The FOUP 11 has a container for horizontally storing wafers and a front door 2 provided on the front surface of the container. The bottom surface of the FOUP 11 can be installed in a load port provided in a semiconductor production facility for processing wafers, and the front door 2 of the FOUP 11 can be fitted with a port door (not shown) of the load port. . Therefore, a door open key slot (Door Open Key Slots) 3 and a door interface hall (Door Interface Halls) 4 are formed in the front door 2. The load port is provided with a coupling pin for installing and positioning the FOUP 11, and a groove (Kinematic Coupling Grooves) for fitting the coupling pin on the bottom surface of the FOUP 11 as shown in FIG. 5 is formed.

  The door open key slot 3, the door interface hole 4 and the groove 5 comply with the SEMI standard. Further, the wafer loading position in the FOUP 11 is also provided at a position complying with the SEMI standard. In particular, as shown in FIG. 5, the loading position of the lowermost wafer 21 is set to a height of 44 mm from the bottom surface of the FOUP 11. The SEMI standard here mainly refers to SEMI-E1.9, SEMI-E15.1, SEMI-E47.1, SEMI-E57, and SEMI-E62. Therefore, if the FOUP 11 is manually installed in the load port of the semiconductor production facility, automatic wafer transfer into the semiconductor production facility and wafer processing are possible.

  As can be seen from FIGS. 3 and 4, the top surface of the FOUP 11 has a vertically symmetrical structure with the bottom surface of the FOUP 11, and fits with the coupling pin provided in the load port. Kinematic Coupling Grooves) 5.

  Further, as shown in FIG. 5, the loading position of the uppermost wafer 22 is set to a height of 44 mm from the upper surface of the FOUP, and the structure from the lower surface of the FOUP 11 to the loading position of the lowermost wafer 21 shown in range B of FIG. The structure from the upper surface of the FOUP 11 shown in range A in FIG. 5 to the loading position of the uppermost wafer 22 is just vertically symmetrical. That is, not only the external structure of the FOUP 11 but also the internal structure of the FOUP 11 is vertically symmetric.

  As shown in FIG. 2, a curve 6 is provided on the back surface of the FOUP 11, and the work of turning the FOUP 11 upside down by the curve 6 can be easily performed. Therefore, the curve 6 on the back surface of the FOUP 11 has a shape that protrudes toward the outside of the FOUP 11 and is bent so as to draw an arc in the vertical direction of the FOUP 11.

  Next, a method for wafer backside inspection and backside analysis using the FOUP 11 will be described. FIG. 6 shows a work flow of backside inspection / analysis using the FOUP 11 of the present embodiment, and FIGS. 7 to 9 show details of the main work of FIG.

  First, the operator flips the FOUP 11 upside down with respect to the FOUP 11 in which the silicon wafer 1 whose front and back surfaces are mirror-finished is loaded in advance using an automatic wafer transfer machine (step S11 in FIG. 6). As for the upside down operation of the FOUP 11, as shown in FIG. 7, the FOUP 11 is moved so as to roll using the curve 6 provided on the back surface of the FOUP 11, and the FOUP 11 is turned upside down. As a result, the wafer back surface 1a of the wafer 1 loaded in the FOUP 11 faces upward.

  Then, in the state where the FOUP 11 is turned upside down as described above, it is installed in the load port of the semiconductor production facility to be inspected as shown in FIG. 1a) is processed (step S12 in FIG. 6). That is, after the wafer transfer robot arm 23 transfers the wafer 1 from the FOUP 11 to the process area with the back surface 1a facing up, the processed wafer 1 is left with the back surface 1a facing up. Return to FOUP11.

  Next, the worker performs the upside down operation of the FOUP 11 as in step S11 to return the FOUP 11 upside down (step S13 in FIG. 6). Thus, the operator installs the FOUP 11 with the surface 1b of the wafer 1 facing upward in the inspection / analysis apparatus for wafer surface evaluation (step S14 in FIG. 6). Thereafter, as shown in FIG. 9, the wafer 1 is transferred from the FOUP 11 by the wafer transfer robot arm 24 to the inspection / analysis area with the surface 1b facing upward and evaluated. As a result, the effects of contamination transfer to the wafer back surface (surface opposite to the surface to be processed) by the inspection target semiconductor production facility and the occurrence of defects on the wafer back surface are investigated.

  As described above, according to the wafer back surface inspection method using the FOUP 11 of this embodiment, the wafer backside operation using vacuum tweezers or the like is not required in the wafer back surface inspection / analysis operation. Therefore, the problem of dropping and destroying the wafer 1 when handling the wafer with vacuum tweezers or the like, and the problem of contaminating the wafer 1 before evaluation by bringing the wafer 1 into contact with the outer wall of the FOUP 11 are solved. Further, since it is not necessary to transport the FOUP 11 to the specified wafer transferable area in the clean room, the time and labor for the backside inspection / analysis preparation work can be reduced.

  In addition, although FOUP was demonstrated as an example as a wafer carrier of a present Example, the technical idea of this invention can also be applied to FOSB (Front Opening Shipping Box).

The front view of FOUP which is an Example of this invention. The side view of FOUP which is an Example of this invention. The top view of FOUP which is an Example of this invention. The bottom view of FOUP which is an Example of this invention. Explanatory drawing about the wafer loading position of the uppermost stage and the lowest stage in FOUP which is an Example of this invention. The flowchart of the inspection and analysis work of the wafer back surface using FOUP which is an Example of this invention. FIG. 3 is an explanatory diagram regarding the upside down operation of the FOUP in the wafer backside inspection / analysis work flow using the FOUP according to the embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an explanatory diagram related to an operation of processing a wafer in an evaluation target semiconductor production facility in a flow of wafer backside inspection / analysis operation using a FOUP according to an embodiment of the present invention. Explanatory drawing regarding the operation | work which test | inspects and analyzes a wafer back surface in the flow of the inspection / analysis operation | work of a wafer back surface using FOUP which is an Example of this invention. The flowchart of the inspection and analysis work of the wafer back surface which is a prior art. Explanatory drawing regarding the wafer front-back inversion work in the inspection / analysis work flow of the wafer back surface, which is a conventional technique. Explanatory drawing regarding the process which processes a wafer in the semiconductor production equipment of evaluation object among the inspection and analysis work flows of the wafer back surface which is a prior art. Explanatory drawing regarding the wafer front-back inversion work in the inspection / analysis work flow of the wafer back surface, which is a conventional technique. Explanatory drawing regarding the operation | work which test | inspects and analyzes a wafer back surface among the inspection / analysis work flows of a wafer back surface which is a prior art.

Explanation of symbols

1 Silicon wafer 2 FOUP front door 3 Door Open Key Slots
4 Door Interface Halls
5 Kinematic Coupling Grooves for mating with FOUP installation positioning coupling pins on the semiconductor production facility side
6 FOUP upside down curve 11 FOUP
21 Lowermost wafer loaded in FOUP 22 Uppermost wafer loaded in FOUP

Claims (3)

In a wafer carrier called FOUP, which is a wafer carrier that horizontally accommodates semiconductor wafers and has a structure that is installed and fixed in a semiconductor production facility on the bottom surface,
A wafer carrier characterized in that a top surface of the wafer carrier is vertically symmetrical with the bottom surface structure.   2. The wafer carrier according to claim 1, wherein a back surface of the wafer carrier has a portion that protrudes toward the outside of the wafer carrier and is bent so as to form an arc in the vertical direction of the wafer carrier. . Using a semiconductor production facility using a wafer carrier called FOUP that horizontally accommodates semiconductor wafers and a wafer inspection apparatus, the surface opposite to the surface to be processed of the semiconductor wafer processed in the semiconductor production facility to be inspected A wafer back surface inspection method for inspecting with the wafer inspection apparatus,
As the wafer carrier, having a structure on the bottom surface that is installed and fixed to the semiconductor production facility, and preparing a wafer carrier having a structure that is vertically symmetrical with the bottom surface structure on the top surface;
Reversing the wafer carrier containing the semiconductor wafer upside down;
Introducing the semiconductor wafer from the inverted wafer carrier into the semiconductor production facility to be inspected without changing the front and back, and processing the surface to be processed of the semiconductor wafer in the semiconductor production facility;
The process of storing the processed semiconductor wafer in the wafer carrier in an inverted state without changing the front and back of the semiconductor wafer, and then returning the wafer carrier upside down;
The semiconductor wafer is introduced into the wafer inspection apparatus from the wafer carrier that has been turned upside down without changing the front and back surfaces, and the wafer inspection apparatus inspects the surface opposite to the surface to be processed. And a wafer back surface inspection method.

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