JP2009032142A - Real time clock - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a real time clock which can function both as a system monitor and as a clock source while reducing a spatial loss and an electrical loss. <P>SOLUTION: The real time clock includes; an oscillation circuit 12; a frequency dividing part 20 which frequency-divides the clock signals outputted from the oscillation circuit 12; a watchdog timer circuit 28 to which the clock signals frequency-divided by the frequency dividing part 20 are input; an inner watch 24 which generates watch data on the basis of the clock signals which are frequency-divided, up to 1 Hz one second, by the frequency dividing part 20; a power input terminal 18; and a backup power source. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a real-time clock, and more particularly to a real-time clock having a function of monitoring the operation of a system equipped with a real-time clock.

  A watchdog timer is known as a circuit having a function of monitoring the operation of the system. In recent years, many systems have been equipped with a watchdog timer. An example of the role of the watchdog timer in such a system is to monitor the operation of the CPU. The watchdog timer is provided with at least a timer that determines a limit value of the monitoring time, and counts a clock signal input from the outside is added or subtracted from the count value determined by the timer. The operation of the CPU is monitored until the built-in timer reaches 0 or a predetermined value, and the operation of resetting the timer is detected when an output signal from the CPU is detected. When the timer reaches 0 or a predetermined value, an interrupt signal or a reset signal is output to the CPU to prevent the CPU from running away.

A watchdog timer having such a function is disclosed in Patent Document 1.
JP 2002-229817 A

  In recent years, electronic devices including the above-described systems are required to be small and thin and highly integrated, and this tendency is particularly remarkable for mobile devices. If the above system is reviewed in consideration of such circumstances, the CPU is connected to a clock source (for example, a real-time clock) for controlling an original operation, and the watchdog timer has its own clock source. It is in. For this reason, a plurality of clock sources are provided in order to configure one system, resulting in a large space and power loss.

  Therefore, an object of the present invention is to provide a real-time clock that can function as both a system monitor and a clock source while reducing the above-described space and power losses.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

Application Example 1 An oscillation circuit that outputs a clock signal, a plurality of frequency dividers, a frequency divider that divides the clock signal and generates a plurality of frequency-divided signals having different periods, and a counter A watchdog timer circuit, which counts up or counts down a counter value based on any one of a plurality of the divided signals, and when the counter value overflows or underflows, sends an interrupt signal to the outside A real-time clock comprising: a watchdog timer circuit for outputting; and an internal clock for generating clock data based on any one of the plurality of divided signals.
With such a configuration, it is possible to provide a system monitoring function after reducing the number of clocks of the system to one, and it is possible to reduce space and power loss.

Application Example 2 The real-time clock according to Application Example 1, wherein a clock selection unit that selects and outputs any one of the plurality of divided signals is provided, and the clock selection is performed for the watchdog timer circuit. A real-time clock characterized by being configured to input the output signal of the unit.
With such a configuration, it is possible to selectively input a plurality of types of clock signals having different periods to the watchdog timer circuit without having a plurality of clock sources. For this reason, it is possible to arbitrarily and accurately determine the time management until timeout of the watchdog timer circuit.

Application Example 3 In the real-time clock according to Application Example 2, the clock selection unit selects a frequency dividing circuit that extracts a signal from the clock selection unit based on a clock selection signal input from the outside. A real-time clock characterized by connecting a register setting unit that outputs a selection signal.
With such a configuration, it is possible to set the time until the timeout of the watchdog timer circuit and the like only by inputting an electric signal to the external terminal in the real-time clock.

Application Example 4 A real-time clock according to any one of Application Examples 1 to 3, further comprising a main power supply terminal and a backup power supply.
With such a configuration, there are two power supply paths, and it is possible to more reliably extract signals from the oscillation circuit.

Hereinafter, embodiments of the present invention relating to a real-time clock will be described in detail with reference to the drawings.
First, a first embodiment according to the real-time clock of the present invention will be described with reference to FIG. The real-time clock 10 according to the present embodiment is configured based on an oscillation circuit 12, a frequency divider 20, an internal clock 24, and a watchdog timer circuit 28.

  A power input terminal (main power terminal) 18 that is an external terminal of the real-time clock 10 is connected to the oscillation circuit 12. The oscillation circuit 12 includes a piezoelectric vibrator 14 and an oscillation circuit 16. The piezoelectric vibrator 14 vibrates at a constant cycle (for example, about 32 kHz) based on an electric signal input from the power input terminal 18 via the oscillation circuit 16 and outputs the vibration to the oscillation circuit 16. The configuration of the piezoelectric vibrator 14 is not particularly limited, but in the case of exciting the 32 kHz vibration mentioned as an example, it is preferable to use a tuning fork type piezoelectric vibrating piece made of quartz. This is because by adopting a piezoelectric vibrating piece made of quartz, it is possible to maintain good frequency temperature characteristics. The oscillation circuit 16 amplifies the signal output from the piezoelectric vibrator 14 and outputs the amplified signal to the frequency divider 20 described later. Note that a secondary battery or the like (backup power supply) (not shown) is connected to the oscillation circuit 12 so that it can oscillate even when no electric signal is input from the power input terminal 18.

  The frequency divider 20 is connected to the output side of the oscillation circuit 12 and includes a plurality of ½ frequency dividers 22. The frequency dividing circuit 22 is connected in multiple stages, and can divide the source clock (32 kHz) in half in steps to generate a 1-second signal of 1 Hz. Each of the individual signals divided by the respective frequency dividing circuits 22 can be called a divided signal.

In addition to the oscillation circuit 12 described above, the frequency divider 20 is connected to an internal clock 24 and a watchdog timer circuit 28 as time measuring means. The details of the 1 second signal generated by the frequency divider 20 are as follows. It is output to both a watchdog timer circuit 28 and an internal clock 24 described later. The internal clock 24 generates the clock data by counting the year, month, day, hour, minute and second based on the input 1 second signal, and serves as a clock source inside the system having a CPU (not shown). Fulfill. Therefore, a clock data output terminal 26 as an external terminal of the real time clock 10 is connected to the internal clock 24.

  The watchdog timer circuit 28 includes a counter 30 having a counter value and a postscaler 32. The counter 30 counts the one-second signal output from the frequency divider 20 and counts up or down the counter value by a predetermined number of clocks. (Hereinafter, an example in the case of counting down will be given in the present embodiment). When the counter value underflows (overflow in the case of counting up), for stopping or resetting the program to the system CPU. Output interrupt signal and reset signal. The counter 30 is reset when an operation signal is input from the CPU before the counter value underflows. The postscaler 32 is used when extending the underflow time of the counter 30. The watchdog timer circuit 28 having such a configuration is connected to an operation signal input terminal 34 for inputting an operation signal of the CPU to the counter 30. A reset signal output terminal 36 for outputting a reset signal (interrupt signal) is connected to the postscaler 32.

  Next, the operation of the real time clock 10 configured as described above will be described. In the real time clock 10 according to the present embodiment, the oscillation circuit 12 receives a signal from the power input terminal 18 and outputs a signal having a predetermined frequency. The signal output from the oscillation circuit 12 is input to the frequency divider 20 to generate a 1 second signal. The 1-second signal generated by the frequency divider 20 is output to the internal clock 24 and also to the watchdog timer circuit 28.

  The 1-second signal input to the internal clock 24 is counted by an internal clock register (not shown), and constitutes clock data such as year, month, day, hour, minute, and second. The clock data constituted by the internal clock 24 is output to the outside from the clock data output terminal 26.

  On the other hand, the 1-second signal input to the watchdog timer circuit 28 is input to the counter 30 (FIG. 2: S10). When a 1-second signal is input to the counter 30, a countdown of a predetermined counter value is started (S20).

  In the watchdog timer circuit 28, during the countdown by the counter 30, it is determined whether or not an operation signal is input from the CPU, and this is fed back (S30). At this time, when an operation signal is input to the counter 30 of the watchdog counter circuit 28 (in the case of Yes), the counter 30 is reset, and the countdown of the counter 30 is started again (S40).

  On the other hand, when the input of the operation signal cannot be confirmed in S30 (in the case of No), it is confirmed whether the counter value is underflowed, that is, whether the counter value is “0” (S50). Here, when the counter value is underflowing (in the case of Yes), it is determined that the CPU and the operation program are out of control, and a reset signal is output to the CPU (S60). On the other hand, when the counter value does not underflow in S50 (in the case of No), the process returns to the previous stage of S20 in order to subtract the counter value again.

According to the real-time clock 10 having such a configuration, the watch dog timer circuit 28 is provided in the real-time clock 10 and the clock source is shared with the internal clock 24 for generating clock data. One oscillator can be provided, and an advantage can be obtained in terms of space and power when an electronic device including a system is configured. Since the watchdog timer circuit 28 is provided for the real-time clock 10, the oscillation circuit 12 can be oscillated by receiving power from a backup power source (not shown). For this reason, even if the system of the electronic device including the CPU is on standby, a reset signal or the like can be output.

  Next, a second embodiment according to the real-time clock of this embodiment will be described with reference to FIG. Note that most of the configuration of the real-time clock according to the present embodiment is the same as that of the real-time clock 10 according to the first embodiment described above. Accordingly, parts having the same function are denoted by reference numerals obtained by adding 100 to the reference numerals shown in FIG. 1, and detailed description thereof will be omitted.

  The real-time clock 110 according to the present embodiment is that a clock selection circuit 140 is provided between the frequency divider 120 and the watchdog timer circuit 128.

  In each frequency dividing circuit 122 in the frequency dividing unit 120, a stepwise 1/2 frequency-divided signal is generated. Therefore, the frequency-divided signals having different periods are output to the clock selection circuit 140 as a clock signal. Of course, it is also possible to output a 1-second signal as a clock signal to be output to the clock selection circuit 140.

  The clock selection circuit 140 includes a clock selection unit 142 and an internal register setting unit 144. The clock selection unit 142 is a switching connection unit that performs switching based on the switching signal output from the internal register setting unit 144 and outputs the clock signal output from the connected frequency dividing circuit 122 to the watchdog timer circuit 128. is there. The internal register setting unit 144 outputs an address corresponding to each of the plurality of frequency dividing circuits 122 provided in the frequency dividing unit 120 and a switching signal to the frequency dividing circuit 122 corresponding to the address. A clock selection signal is recorded. Then, a switching signal to the frequency dividing circuit 122 corresponding to the clock selection signal input from the clock selection signal input terminal 146 that is an external terminal of the real time clock 110 is output to the clock selection unit 142.

  According to the real-time clock 110 having such a configuration, it is possible to accurately control the time management until the time-out of the watchdog timer circuit 128 and the output time of an interrupt signal or the like at an arbitrary timing. For this reason, it is possible to set an optimum monitoring timing according to the operation status of individual systems and electronic devices without having a plurality of clock oscillation sources.

It is a block diagram which shows the structure of the real-time clock which concerns on 1st Embodiment. It is a flowchart which shows operation | movement of a watchdog timer circuit. It is a block diagram which shows the structure of the real-time clock which concerns on 2nd Embodiment.

Explanation of symbols

  10 ......... Real time clock, 12 ......... Oscillator, 14 ......... Piezoelectric vibrator, 16 ......... Oscillator circuit, 20 ......... Division part, 22 ......... Division circuit, 24 ......... Internal clock 28 ......... Watchdog timer circuit, 30 ... Counter, 32 ... Post-scaler.

Claims (4)

An oscillation circuit that outputs a clock signal;
A frequency divider that divides the clock signal and generates a plurality of frequency-divided signals having different periods from each other;
A watchdog timer circuit having a counter, which counts up or counts down a counter value based on any one of a plurality of the divided signals, and interrupts when the counter value overflows or underflows A watchdog timer circuit for outputting a signal to the outside;
An internal clock that generates clock data based on any one of the plurality of divided signals;
Real-time clock characterized by comprising. The real-time clock according to claim 1,
A clock selection unit that selects and outputs any one of the plurality of the divided signals is provided,
A real-time clock characterized in that an output signal of the clock selector is input to the watchdog timer circuit. The real-time clock according to claim 2,
The clock selection unit is connected to a register setting unit that outputs a selection signal for selecting a frequency dividing circuit for extracting a signal from the clock selection unit based on a clock selection signal input from the outside. Real time clock. The real-time clock according to any one of claims 1 to 3,
A real-time clock characterized by further comprising a main power supply terminal and a backup power supply.

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