JP2007064867A - Real-time clock unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a real-time clock unit capable of detecting the abnormality of a data input without preparing specially a data for check. <P>SOLUTION: This real-time clock unit 10 has an oscillation circuit part 12 for outputting a prescribed frequency of clock signal, a frequency dividing circuit part 14 for dividing the clock signal output from the oscillation circuit part 12 into a plurality of stages, and for outputting a signal for a timepiece, a timepiece/calendar circuit part 16 formed to allow rewriting and for counting the signals for the timepiece output from the frequency dividing circuit part to output a signal in a current date and time, and a date and time data abnormality detecting part 18 for detecting the abnormality of the date and time data input into the timepiece/calendar circuit part 16, and for outputting an abnormal data detection signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a real-time clock device that outputs a current time.

  The real-time clock device has a calendar function and a function for displaying time, and is mounted on many electronic devices, so that a user of the electronic device can easily know the current date and time. The real-time clock device is indispensable for a reservation function of the electronic device that operates or stops the electronic device at a predetermined time or time. However, when the user activates the electronic device and sets the time of the real-time clock device to the actual time, the user may not be aware of the wrong date and time due to an incorrect button press. For example, if the date of March 32 and the date that cannot be on the calendar is input, the calendar of the real-time clock device counts as March 33, March 34,... Cause.

By the way, as a method of detecting whether or not there is an abnormality in data, there are Patent Document 1 and Patent Document 2. The abnormal data detection method described in Patent Document 1 prepares two mirror data for checking that are the same as the control data, compares the control data with the two mirror data, and compares the abnormal data by the majority method. Is determined. In addition, in the data abnormality detection method of Patent Document 2, when data is input (written), check data for the write data is created, and the check data and the write data are compared with each other, and the write data is abnormal. It is determined whether or not there is.
JP-A-8-95868 JP-A-6-89235

  In the data abnormality detection methods described in Patent Document 1 and Patent Document 2, check data corresponding to the input data must be created and held, a dedicated special circuit is required, and the circuit configuration Is complicated. Moreover, the abnormal data detection methods described in Patent Documents 1 and 2 require a complicated data check circuit.

  An object of the present invention is to provide a real-time clock device capable of detecting an abnormality of input date / time data without specially creating check data as described above.

  In order to achieve the above object, a real-time clock device according to the present invention includes an oscillation circuit unit that outputs a signal of a predetermined frequency, a clock signal output from the oscillation circuit unit divided into a plurality of stages, and a clock signal. The clock / calendar circuit unit that outputs the current date and time by counting the clock signal output from the frequency divider circuit unit, and the clock / calendar circuit unit And a date / time data abnormality detection unit that detects an abnormality of the date / time data input to and outputs an abnormality data detection signal.

  In the present invention thus configured, it is detected that the input date and time data is data that is impossible in reality, such as March 32, 24:60:60, and an abnormal data detection signal is output. Therefore, it is not necessary to create special check data corresponding to the input data, and the circuit configuration can be simplified. In addition, since it is only necessary to detect data that cannot actually exist, a complicated detection circuit is not required.

  The date / time data abnormality detection unit may be configured to monitor whether there is an abnormality in the current date / time data output from the clock / calendar circuit unit. Portable electronic devices such as mobile phones and portable visual / audio devices (AV devices) are operated by batteries. An IC used in a mobile phone or a portable AV device requires a certain operating voltage, and may malfunction if the voltage falls below that. The same applies to a real-time clock device, and if the voltage of a portable electronic device equipped with the real-time clock device is reduced due to battery consumption, it may malfunction. Therefore, the date / time data abnormality detection unit monitors the current date / time data output by the clock / calendar circuit unit, and outputs an abnormality data detection signal when an abnormality occurs. Thereby, the user (user) of the electronic device can know that the real-time clock device is not normal, and can correct malfunction of the electronic device by correcting the current date and time.

  A preferred embodiment of a real-time clock device according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram of a main part of the real-time clock device according to the embodiment. In FIG. 1, the real-time clock device 10 includes an oscillation circuit unit 12, a frequency dividing circuit unit 14, a clock / calendar circuit unit 16, a date / time data abnormality detection unit 18, and an interface circuit 20. The oscillation circuit unit 12 includes an oscillator 22 including, for example, a tuning-fork type crystal vibrating piece, and an oscillation circuit 24 that excites the oscillator 22, and outputs a clock signal of a predetermined frequency of 32768 Hz.

  The frequency dividing circuit unit 14 is provided on the output side of the oscillation circuit unit 12. The frequency dividing circuit unit 14 is configured by connecting a plurality of ½ frequency dividers (not shown) in multiple stages. Each 1/2 divider of the divider circuit unit 14 sequentially divides the 32768 Hz clock signal output from the oscillation circuit unit 12 into 1/2 and connects the clock signal, that is, the 1 Hz 1 second signal to the output side. Is output to the watch / calendar circuit unit 16. The clock / calendar circuit unit 16 includes a plurality of counters (not shown), counts the 1-second signal output from the frequency-dividing circuit unit 14, and outputs current date / time data of year / month / hour / minute / second. It is like that. The current date and time data output from the clock / calendar circuit unit 16 is output to the outside of the real-time clock device 10 via the interface circuit 20. The clock / calendar circuit unit 16 can rewrite date / time data from the outside, as will be described later.

  The date / time data abnormality detection unit 18 includes an abnormal data detection circuit 26 and an abnormal data warning flag 28. The abnormal data detection circuit 26 is connected to the timepiece / calendar circuit unit 16 and the interface circuit 20. As will be described in detail later, the abnormal data detection circuit 26 detects abnormal data when the date / time data input via the interface circuit 20 is impossible in reality. When the date / time data input from the interface circuit 20 is abnormal data, the abnormal data detection circuit 26 sets a flag of the abnormal data warning flag 28. In other words, the abnormal data detection circuit 26 rewrites the bit of the abnormal data warning flag 28 from “0” to “1” when the input date and time data is data that cannot actually exist. The abnormal data warning flag 28 outputs “0” when the date / time data is normal, and outputs “1” as the abnormal data detection signal when the date / time data is abnormal. The output of the abnormal data warning flag 28 is output to the outside via the interface circuit 20.

  The real-time clock device 10 is mounted on an electronic device, and the interface circuit 20 is connected to an MPU (Micro Processing Unit) 32 provided in the electronic device via a bus 30. The MPU 32 reads the current date and time data output from the clock / calendar circuit unit 16 via the bus 30 and the interface circuit 20. Further, when the user of the electronic device operates the input unit such as a keyboard of the electronic device and receives a write command, the MPU 32 writes the date / time data in the clock / calendar circuit unit 16.

  As shown in FIG. 2, the abnormal data detection circuit 26 includes a calendar data abnormality detection unit 34, a time data abnormality detection unit 36, and an OR circuit 38. The calendar data abnormality detection unit 34 includes a year data abnormality detection circuit 40 that detects year data abnormality, a month data abnormality detection circuit 42 that detects month data abnormality, a day data abnormality detection circuit 44 that detects day data abnormality, A date / time data abnormality detection circuit 46 for detecting an abnormality in date / time data and an OR circuit 48 having an input terminal connected to the output side of these detection circuits.

  The time data abnormality detection unit 36 includes an hour data abnormality detection circuit 50 that detects abnormality of hour data, a minute data abnormality detection circuit 52 that detects abnormality of minute data, a second data abnormality detection circuit 54 that detects abnormality of second data, The OR circuit 56 has an input terminal connected to the output side of these detection circuits. The output terminals of the OR circuit 48 of the calendar data abnormality detection unit 34 and the OR circuit 56 of the time data abnormality detection unit 36 are connected to the input terminal of the OR circuit 38. The output terminal of the OR circuit 38 is connected to the abnormal data warning flag 28, and when any of the detection circuits of the calendar data abnormality detecting unit 34 and the time data abnormality detecting unit 36 detects a data abnormality, “ 1 "is output, and the bit of the abnormal data warning flag 28 is set to" 1 ".

The operation of the embodiment thus configured is as follows.
When the user inputs date / time data via an input unit (not shown) of the electronic device, the MPU 32 inputs the date / time data to the real-time clock device 10 via the bus 30. That is, the MPU 32 writes the date / time data to the timepiece / calendar circuit unit 16 via the interface circuit 20 and sets it. The date / time data input from the interface circuit 20 is also input to the abnormal data detection circuit 26 of the date / time data abnormality detection unit 18. In other words, the calendar data of the date / time data is input to the calendar data abnormality detection unit 34, and the time data is input to the time data abnormality detection unit 36.

  The year data anomaly detection circuit 40 of the calendar data anomaly detection unit 34 determines that it is normal when the input year data is from 0 to 9999, outputs “0”, and other year names are input. “1” is output as abnormal data. The month data abnormality detection circuit 42 determines that it is normal when the input month data is from January to December, and outputs “0”, and assumes that it is abnormal data when any other month is input. “1” is output. The date data abnormality detection circuit 44 determines that the data is normal when the input date data is from 1st to 31st, and outputs “0”. “1” is output.

  The year / month / day data abnormality detection circuit 46 combines the input year data, month data, and day data, and detects an abnormality of the calendar data that is impossible as a calendar. That is, when the date / year data abnormality detection circuit 46 receives, for example, February, April, June, September, and November 31st, February 30th, and February 29th other than the leap year, “1” is output as abnormal data. The OR circuit 48 of the calendar data abnormality detection unit 34 inputs “1” to the OR circuit 38 when any of the detection circuits 40, 42, 44, 46 outputs “1”.

  The hour data abnormality detection circuit 50 of the time data abnormality detection unit 36 assumes that when the time of the day is set to the 24-hour system, it is normal when the inputted time data is from 0:00 to 23:00. When “0” is output and data other than 0:00 to 23:00 is input, “1” is output as abnormal data. Further, when the time of day is set to a 12-hour system, the hour data abnormality detection circuit 50 is input when the data is AM 12 o'clock, AM 1 o'clock to AM 11 o'clock, PM 12 o'clock, PM 1 o'clock to PM 11 o'clock. In addition, “0” is output as normal, and “1” is output as abnormal data when data is input at other times.

  The minute data abnormality detection circuit 52 outputs “0” as normal when the inputted minute data is 0 minutes to 59 minutes, and is regarded as abnormal data when other minute data is inputted. “1” is output. The second data abnormality detection circuit 54 outputs “0” as normal when the inputted second data is 0 to 59 seconds, and when other second data is inputted, “1” is output as there is. The OR circuit 56 of the time data abnormality detection unit 36 inputs “1” to the OR circuit 38 when any of the detection circuits 50, 52, 54 outputs “1”.

  When one of the OR circuits 48 and 56 outputs “1”, the OR circuit 38 outputs “1” on the assumption that the time data input from the interface circuit 20 is abnormal, and sets the flag of the abnormal data warning flag 28. . The flag set in the abnormal data warning flag 28 is read by the MPU 32 by inputting an interrupt signal to the MPU 32, and notifies the user that abnormal data has been input by a buzzer sound or the like. Thus, the user can know that the abnormal date / time data has been input, and can correct and input the correct date / time data, thereby preventing the real-time clock device 10 and the electronic device from malfunctioning. In addition, in the embodiment, it is not necessary to newly create check data corresponding to input data, and the circuit configuration can be simplified. Further, since only the data that is not in the calendar or the actual time is detected, the configuration of the detection circuit can be simplified.

  In addition, said embodiment is 1 aspect of this invention, Comprising: It is not limited to this. For example, in the above-described embodiment, the case where the abnormality of the input date / time data is detected has been described. However, the abnormality of the current date / time data output from the clock / calendar circuit may be detected. That is, the date / time data abnormality detection unit 18 reads the output of the clock / calendar circuit unit 16 at predetermined time intervals (for example, every second), and the current date / time data output by the clock / calendar circuit unit 16 in the same manner as described above. Detect anomalies. By doing so, the user can easily know that the real-time clock device 10 is not normal.

  For example, when the battery (not shown) of the electronic device is exhausted and the output voltage of the battery becomes lower than the operating voltage of the real time clock device 10, the real time clock device 10 may malfunction. When the voltage returns to the normal state, the abnormal data detection circuit 26 of the date / time data abnormality detection unit 18 detects an abnormality in the current date / time data output from the clock / calendar circuit unit 16 and sets the abnormal data warning flag 28. Set a flag. Accordingly, the user can easily know that the real-time clock device 10 is not operating normally, can be corrected to output the correct current date and time, and can prevent malfunction of the electronic device. Can do. In the embodiment, the case where the flag is set when the abnormal data is input has been described. However, when the abnormal data is input, the output voltage of the terminal of the real-time clock device 10 is changed from “H” to [L You may make it change to.

It is a principal part block diagram of the real-time clock apparatus which concerns on embodiment. It is a detailed block diagram of the abnormal data detection circuit which concerns on embodiment.

Explanation of symbols

  10... Real-time clock device 12... Oscillation circuit section 14... Dividing circuit section 16... Clock / calendar circuit section 18. Data detection circuit 28... Abnormal data warning flag.

Claims (2)

An oscillation circuit unit that outputs a signal of a predetermined frequency;
Dividing the clock signal output from the oscillation circuit section into a plurality of stages, and outputting a clock signal;
A clock / calendar circuit unit that is formed to be rewritable, counts the clock signal output from the frequency divider unit, and outputs a current date / time signal;
A date / time data abnormality detection unit that detects an abnormality in the date / time data input to the clock / calendar circuit unit and outputs an abnormality data detection signal;
A real-time clock device comprising: The real-time clock device according to claim 1,
The real-time clock device, wherein the date / time data abnormality detection unit monitors whether there is an abnormality in the current date / time data output from the clock / calendar circuit unit.

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