JP2009031974A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect the abnormality of a memory without deteriorating processing efficiency or making a designer conscious of it. <P>SOLUTION: This semiconductor integrated circuit is provided with a memory monitor circuit configured of an instruction monitoring part for monitoring an instruction to be sent from a memory interface to a memory; a write-in data storage part for storing data to be sent to the memory so as to be written in the specific address of the memory when an instruction to instruct the write-in of data in the specific address of the memory is detected by the instruction monitoring part; a read-out data storage part for storing the data to be read from the specific address, and to sent to the memory interface when an instruction to instruct the read-out of the data from the specific address of the memory is detected by the instruction monitoring part; and a data comparison section for comparing the data stored by the write-in data storage part with the data stored by the read-out data storage part, and for detecting mismatching. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit that uses a memory via a memory interface, and in particular, includes a memory monitoring circuit that detects that a memory is in an abnormal state, or further initializes the memory in an abnormal state. The present invention relates to a semiconductor integrated circuit.

  In a semiconductor integrated circuit that performs data processing for various purposes, a memory is often required to temporarily store data to be processed. In particular, in order to process a large amount of data such as image data, a memory having a large storage capacity is required. In some cases, the memory is preferably provided on the same semiconductor integrated circuit chip as a circuit that performs data processing using the memory. However, when a large-capacity memory is required, it is often preferable to configure a data processing circuit in combination with a memory of another chip. Therefore, an ASIC vendor that provides an ASIC (application-specific semiconductor integrated circuit) according to customer needs generally provides a memory controller that controls a memory chip as a design asset.

  In the case of a semiconductor integrated circuit that performs data processing using a memory, even when the memory is provided on the same chip or when a memory of another chip is used, normal processing cannot be performed if the memory operation is abnormal. Therefore, in order to detect an abnormality in the memory, a method of comparing data written to a specific address in the memory with data read from the same address is conventionally known.

  For example, Patent Document 1 utilizes the fact that writing / reading of an image recording memory is interrupted during the blanking period, and during that period, data stored in the diagnosis target area is saved and then the memory is stored. It has been proposed to make a normal / abnormal judgment by writing test data into and reading it out and comparing it with the original test data.

Patent Document 2 includes a data latch circuit that holds data to be written to the memory and a read pulse generation circuit that generates a read control signal when writing to the memory is completed. It has been proposed to output stored data, compare it with data from a data latch circuit by a comparison circuit, and output an error signal if they do not match.
JP-A-7-67146 JP-A-7-160586

  The technique of Patent Document 1 requires a circuit or software for detecting various blanking periods and controlling various operations. In the embodiment of Patent Document 1, a blanking period detection circuit and other circuits, and a CPU loaded with a memory diagnosis program control memory diagnosis. However, it is difficult to require a designer who designs a semiconductor integrated circuit for data processing to design a circuit or software for detecting an abnormality in a memory that is not the original data processing. This is particularly difficult in the case of an ASIC that requests a design from a customer. Therefore, it is desirable to detect the abnormality of the memory without being aware of the designer, and more preferably to take countermeasures. The technique of Patent Document 1 cannot cope with such a problem.

  In the technique of Patent Document 2, a memory abnormality can be detected by a data latch circuit, a read pulse generation circuit, or the like without requiring control by a CPU or the like. However, every time writing to the memory is performed, reading for error detection is performed. For this reason, there is a problem that the period of time during which the memory is used for purposes other than the purpose of the original data processing becomes longer, and the efficiency of data processing decreases.

It is an object of the present invention to provide a technology capable of detecting a memory abnormality or taking a countermeasure against the abnormality without lowering the processing efficiency and without the designer being aware of it. .

In order to solve the above problem, a first semiconductor integrated circuit according to the present invention includes an instruction monitoring unit that monitors an instruction sent from a memory interface to a memory;
When the instruction monitoring unit detects an instruction to write to a specific address in the memory, the instruction monitoring unit holds data sent from the memory interface to the memory to write to the specific address, and sets a flag. Write data holding unit to be set;
When the flag is set and the instruction monitoring unit detects an instruction to read from the specific address of the memory, the instruction is read from the specific address and sent to the memory interface. A read data holding unit for holding data;
Memory monitoring comprising a data comparison unit for comparing the data held by the write data holding unit with the data held by the read data holding unit and detecting a mismatch when the read data holding unit holds data A circuit is provided.

  Here, it is preferable that when the data comparison unit detects the mismatch, the data comparison unit outputs a status notification signal requesting initialization of the memory to the memory interface.

  Furthermore, it is more preferable that the state comparison signal is output when the data comparison unit detects a mismatch continuously a predetermined number of times.

In order to solve the above problem, a second semiconductor integrated circuit according to the present invention includes a user logic unit and a memory interface, and a circuit included in the user logic unit is connected to the outside via the memory interface. In a semiconductor integrated circuit that writes data and reads data from the memory,
A command monitoring unit that monitors commands sent from the memory interface to the memory;
When the instruction monitoring unit detects an instruction to write to a specific address of the memory, the instruction monitoring unit holds data sent from the memory interface to the memory to write to the predetermined address, and sets a flag. Write data holding unit to be set;
When the flag is set and the instruction monitoring unit detects an instruction to instruct reading from the specific address of the memory, the instruction is read from the predetermined address and sent to the memory interface. A read data holding unit for holding data;
Memory monitoring comprising a data comparison unit for comparing the data held by the write data holding unit with the data held by the read data holding unit and detecting a mismatch when the read data holding unit holds data A circuit is provided.

  Here, it is preferable that the circuit included in the user logic unit is a circuit designed by a customer, and the memory interface and the memory monitoring circuit are prepared as a macro cell by an ASIC manufacturer.

  In the semiconductor integrated circuit of the present invention, the memory monitoring circuit can monitor the state of the memory without the need for control by other circuits or software by monitoring instructions sent from the memory interface to the memory. . Therefore, it is possible to monitor the state of the memory without being aware of the designer and detect when an abnormal state occurs. In addition, the memory monitoring circuit detects writing to a specific address and subsequent reading from the same address, holds write data and read data, and performs comparison between them. Therefore, it is possible to monitor the state only by performing the write and read operations that are originally necessary. Therefore, the processing efficiency does not decrease.

  FIG. 1 is a circuit diagram showing an example of a first embodiment of a semiconductor integrated circuit according to the present invention.

  The semiconductor integrated circuit 10 shown in FIG. 1 controls a user logic unit 20 provided with various circuits for performing logical operation processing using a memory (SDRAM) 50 provided as a separate chip, and controls the memory 50 and user logic. And a memory interface 30 that controls data exchange between the unit 20 and the memory 50.

  The memory interface 30 and the memory 50 are connected by a data line 32 and a command line 34. The data wiring 32 transmits data (write data W_DATA) to be written to the memory 50 by the circuit of the user logic unit 20 to the memory 50 via the memory interface 30 and also reads data (read data R_DATA) read from the memory 50. ) Is received via the memory interface 30. In the semiconductor integrated circuit 10, the data line 32 is divided into a write data line 32B and a read data line 32C. The data lines in the semiconductor integrated circuit 10 are connected to a common data line 32A between the semiconductor integrated circuit 10 and the memory 50 through an output buffer and an input buffer, respectively.

  The command wiring 34 is a wiring for the circuit of the user logic unit 20 to send various commands COM for controlling the memory to the memory 50 via the memory interface 30. For example, commands such as writing and reading and various commands necessary for initializing the memory 50 are sent to the memory 50 through the command wiring 34. Further, an address signal ADDR for designating an address for writing data or reading data is also sent to the memory 50 through the command wiring. The data line 34 is divided into a data line 34B in the semiconductor integrated circuit 10 and a data line 32A between the semiconductor integrated circuit 10 and the memory 50, which are connected via an output buffer.

  Note that the data wiring 32, the command wiring 34, and the other wirings indicated by double lines have a bit width necessary for sending each data, address, and command.

  Between the semiconductor device integrated circuit 10 and the memory 50, a clock wiring 22 for supplying the clock signal CLK to the memory 50 is provided. The clock wiring 22 is divided into a clock wiring 22B in the semiconductor integrated circuit 10 and a clock wiring 22A between the semiconductor integrated circuit 10 and the memory 50, which are connected via an output buffer. The clock signal CLK is also supplied to the memory interface 30.

  Various circuits provided in the user logic unit 20 of the semiconductor integrated circuit 10 send and receive data by sending various commands and address signals to the memory 50 provided as a separate chip via the memory interface 30. Thus, various data processing using the memory 50 can be performed. However, in the configuration shown in FIG. 1, for example, the clock received by the memory 50 due to the influence of the length and shape of the clock wiring 22A (usually provided on the wiring board) between the semiconductor integrated circuit 10 and the memory 50. It is difficult to strictly control the timing of the signal CLK. For this reason, in particular, when a synchronous memory that writes and reads data in synchronization with the clock signal CLK is used as the memory 50, an operation error occurs when attempting to write or read data, and subsequent data writing , There may be an abnormal state (stack state) in which reading cannot be performed.

  Moreover, an abnormal state may be caused by sudden noise.

  Therefore, in order to monitor the state of the memory 50 and detect that such an abnormal state has occurred, the semiconductor integrated circuit 10 further includes an instruction monitoring unit 42, a write data holding unit 44, and a read data holding unit 46. The memory monitoring circuit 40 including the data comparison unit 48 is included. Each part of the memory monitoring circuit 40 is supplied with the clock signal CLK and operates in synchronization with the clock signal CLK.

  The instruction monitoring unit 42 is connected to the instruction wiring 34B and monitors the instruction COM and the address signal ADDR sent from the memory interface 30 to the memory 50. When it is detected that the command sent to the memory 50 is a write command and the target address is a specific address, the write data holding command W_COM is sent to the write data holding unit 44. When the instruction monitoring unit 42 detects that the instruction sent to the memory 50 is a read instruction and the target address is a specific address, the instruction monitoring unit 42 sends a read data holding instruction R_COM to the read data holding unit 46.

  The write data holding unit 44 is connected to the write data wiring 32 </ b> B and holds the write data sent to the memory 50 when receiving the command W_COM from the command monitoring unit 42. Here, the address signal and the write data are sent to the memory 50 with a specific timing relationship determined by the specifications of the memory 50. The instruction monitoring unit 42 considers this specific timing relationship, and at the timing at which data sent to the memory 50 to be written to a specific address can be held, the instruction monitoring unit 42 holds the hold instruction W_COM in the write data holding unit 44. Send.

  The write data holding unit 44 has a write data hold flag (not shown), and sets the write flag when the write data is held. The value FLG of the write flag can be read from the read data holding unit 46.

  The read data holding unit 46 is connected to the read data wiring 32C. Then, when the holding flag R of the write data holding unit 44 is set, when the holding command R_COM is received from the command monitoring unit 42, the read data read from the memory 50 and sent to the memory interface 30 is held. To do. Also at this time, the instruction monitoring unit 42 sends a holding instruction R_COM to the read data holding unit 46 at a timing at which data read from a specific address can be held. When read data is held, read data holding unit 46 outputs read data holding notification signal R_REG to write data holding unit 44 and data comparison unit 48. When the holding notification signal R_REG is input, the write data holding unit 44 initializes the data holding flag.

  When the holding notification signal R_REG is input, the data comparing unit 48 reads out the write data held in the write data holding unit 44 and the read data held in the read data holding unit 46 and compares them. . Then, a memory state notification signal STA is output according to the comparison result. Here, the read data held in the read data holding unit 46 is data read from a specific address where the write data held in the write data holding unit 44 is written. Therefore, when the memory 50 is in a normal state, the two match. On the contrary, when both are different, it can be determined that the state of the memory 50 is abnormal.

  In the memory monitoring circuit 40 provided in the semiconductor integrated circuit 10 shown in FIG. 1, the instruction COM and the address signal ADDR sent through the instruction wiring 34 when various circuits provided in the user logic unit 20 use the memory 50 are used. The instruction monitoring unit 42 monitors. When the instruction monitoring unit 42 detects a specific instruction and address, it sends holding instructions W_COM and R_COM to the write data holding unit 44 and the read data holding unit 46. The write data holding unit 44 and the read data holding unit 46 that have received an instruction from the instruction monitoring unit 42 use the write data wiring 32B when various circuits provided in the user logic unit 20 use the memory 50. Write data W_DATA sent through and read data R_DATA received through read data wiring 32C are held. Then, the data comparison unit 48 compares the data held in the write data holding unit 44 and the read data holding unit 46 to detect an abnormal operation of the memory 50.

  As described above, the memory monitoring circuit 40 can monitor the state of the memory 50 without requiring an instruction from the user logic unit 20. Therefore, the memory 50 can be monitored without the designer who designs the user logic unit 20 being conscious. The memory monitoring circuit 40 only monitors or holds instructions, addresses, and data sent to use the memory 50 by the circuit of the user logic unit 20, and the memory 50 is monitored to monitor the memory 50. Never use it. Therefore, the efficiency of data processing performed by the circuit of the user logic unit 20 using the memory 50 is not reduced.

  The data comparison unit 48 can immediately output a state notification signal STA indicating a memory abnormality when a mismatch between the write data and the read data is detected. Alternatively, a counter (not shown) may be provided in the data comparison unit 48, and the status notification signal STA may be output when the cumulative mismatch detection count reaches a predetermined count. The output state notification signal STA is supplied to the reset terminal of the memory interface 30 via the AND gate 36. Then, an instruction for initializing the memory 50 is supplied from the memory interface 30 to the memory 50, and the memory 50 is initialized. As a result, the abnormal state (stack state) of the memory 50 is eliminated, and data can be written and read again.

  At this time, only the memory 50 is initialized without initializing the user logic unit 20 of the semiconductor integrated circuit 10. Therefore, data processing using the memory 50 by various circuits provided in the user logic unit 20 of the semiconductor integrated circuit 10 can be resumed immediately after the initialization of the memory 50 is completed. In addition, the intermediate processing result performed in the circuit of the user logic unit 20 before the initialization of the memory 50 is not lost.

  For example, the ASIC manufacturer prepares the memory interface 30 as a macro cell, and the customer designs the circuit of the user logic unit 20 that uses the memory 50 via the memory interface 30 to configure the semiconductor integrated circuit 10 as an ASIC product. It is possible. The ASIC manufacturer prepares a memory monitoring circuit 40 to be used in combination with the memory interface 30 as a macro (soft macro) cell, and at the stage of receiving design data of the user logic unit 20 from a customer, 30 and the memory monitoring circuit 40 can be combined to form the semiconductor integrated circuit 10. In this case, the customer does not need to be aware of even the presence of the memory monitoring circuit 40.

  FIG. 2 is a flowchart showing an outline of the operation of the semiconductor integrated circuit 10 shown in FIG.

  First, power is turned on in step S110. In step S112, the user logic unit 20, the memory interface 30, and the memory monitoring circuit 40 are initialized. Specifically, in the memory monitoring circuit 40, the value of a data holding flag (not shown) of the write data holding unit 44 is set to “0”, and the count value Count of a counter (not shown) of the data comparison unit 48 is set to “0”. . Further, in step S114, the memory 50 is initialized. That is, the user logic unit 20 sends a reset signal RST to the memory interface 30, and the memory interface 30 sends a command necessary for initializing the memory 50 to the memory 50.

  After the initialization is completed, various circuits provided in the user logic unit 20 of the semiconductor integrated circuit 10 perform normal operations. In this operation, when it becomes necessary to write data to the memory 50, a write command and an address signal indicating an address to be written are sent to the memory 50 through the memory interface 30 and the command wiring 34. Further, data to be written is sent to the memory 50 through the memory interface 30 and the data wirings 32B and 32A. Similarly, when it is necessary to read the data written in the memory 50, a read command and an address signal indicating an address to be read are sent to the memory 50 through the memory interface 30 and the command wiring 34. Then, the data read from the memory is received via the data lines 32A and 32C and the memory interface 30.

  The memory monitoring circuit 40 monitors the state of the memory 50 during the period when the circuit of the user logic unit 20 performs such an operation. That is, in step S120, the instruction monitoring unit 42 monitors instructions and address signals sent to the memory 50. When a data write command to a specific address is detected in step S122, the data hold command is sent to the write data holding unit 44. Thereby, in step S124, the data sent to the memory 50 for writing to the specific address is held in the write data holding unit 44. Further, a holding flag (not shown) in the write data holding unit 44 is set to “1”. Thereafter, the process returns to step S120, and the monitoring of the instruction and address signal is continued.

  On the other hand, when a data read command from a specific address is detected in step S 130, a read data holding command is sent to the read data holding unit 46. In this case, in step 132, the value FLG of the holding flag of the write data holding unit 44 is confirmed. If the holding flag is not set (FLG = 0), the process returns to step S120 and monitoring is continued. On the other hand, if the holding flag is set (FLG = 1), the data read from the specific address of the memory 50 and sent to the memory interface 30 is held in the read data holding unit 46 in step S134. The Further, a read notification signal is sent from the read data holding unit 46 to the write data holding unit 44, and the holding flag is initialized to “0”.

  The holding notification signal is also sent from the read data holding unit 46 to the data comparison unit 48. In step S140, the data comparison unit 48 compares the write data held in the write data holding unit 44 with the read data held in the read data holding unit 46. If a match between the two data is detected by the comparison, the count value Count of the counter of the data comparison unit 48 is initialized to “0” in step S142, and the process returns to step S120 to be monitored by the instruction monitoring unit 42. Will continue. If a data mismatch is detected, 1 is added to the count value Count in step S144, and the count value Count is confirmed in step S146. If the count value Count has not reached the predetermined value (N), the process returns to step S120 and monitoring of the memory 50 is continued. On the other hand, if it is detected that the count value has reached the predetermined value, the count value Count is initialized to “0” in step S148, and the data notification unit 48 outputs a state notification signal STA indicating an abnormal state. Is done.

  When the status notification signal STA is input to the memory interface 30 via the AND gate 36, the memory 50 is initialized in step S114. Thereafter, when the data processing using the memory 50 by the user logic unit 20 is resumed, the monitoring of the state of the memory 50 by the memory monitoring circuit 40 is continued again.

  FIG. 3 shows an example of an embodiment of the device 100 including the semiconductor integrated circuit 10 </ b> A including the memory interface 30 and the memory monitoring circuit 40.

  A device 100 illustrated in FIG. 3 is a display device that performs display on the display device 70 based on moving image data MP_DATA input to the semiconductor integrated circuit 10A. The semiconductor integrated circuit 10A outputs display data DSP_DATA generated by performing predetermined processing on the input moving image data MP_DATA to the display device 70. In the user logic unit 20A of the semiconductor integrated circuit 10A, a data processing circuit that performs predetermined processing on moving image data is formed. The processing circuit stores image data for one frame of moving image data in a memory 50 connected via the memory interface 30. Then, while reading the stored data for one frame again, for example, processing such as brightness adjustment and overdrive is performed to generate display data DSP_DATA.

  In the device 100 shown in FIG. 3, the memory 50 is used as a frame memory for storing image data for one frame. In this case, data is written to and read from addresses within a predetermined range for each frame period. Therefore, if the specific address monitored by the memory monitoring circuit 40 is set within this predetermined range, the write data and the read data can be compared for each frame period. Even when the memory 50 is used for other purposes, it is preferable to set a frequently written / read address as a specific address to be monitored.

  If the specific address to be monitored can be determined during the development of the semiconductor integrated circuit 10 of the present invention, the setting is made at the time of development. For example, when the semiconductor integrated circuit 10 is configured as an ASIC product, when the ASIC manufacturer combines the memory interface 30 and the memory monitoring circuit 40 with the user logic unit 20 designed by the customer, the setting of the memory monitoring circuit 40 is performed. I do. For this purpose, a memory monitoring circuit 40 is prepared as a macro capable of setting a specific address to be monitored. On the other hand, if it is difficult to determine a specific address in the development stage, an address setting holding unit (not shown) is prepared in the instruction monitoring unit 42 (see FIG. 1), and after the semiconductor-to-integrated circuit 10 is manufactured. Settings can also be made.

  Rather than designating each address to be written (read) to the memory 50 by an address signal, only the first address is designated, and the first address and subsequent burst length address are written (read), burst write (read) May be performed. In this case, when the instruction monitoring unit 42 detects an address signal indicating a head address at which writing (reading) to a specific address is performed in consideration of the burst length together with the write instruction or the read instruction, the instruction monitoring unit 42 issues a holding instruction. Output. At this time, for example, a counter (not shown) that counts the clock signal CLK is provided in the instruction monitoring unit 42, and the write data holding unit 44 or the read data holding unit 46 is sent at a timing when data written (read) to a specific address is sent. Send a hold command to.

  The write data holding unit 44 and the read data holding unit 46 hold, for example, data of the number of bits for one word that are simultaneously written and read. In step S140 of FIG. 2, for example, if there is a mismatch of 1 bit or more between the multi-bit data held in the write data holding unit 44 and the read data holding unit 46, it is determined as “mismatch”. Can do. Alternatively, it is also possible to determine “mismatch” when there is a mismatch of more than a predetermined number of bits of 2 bits or more, without determining “mismatch” only by mismatch of 1 bit.

  The embodiment of the present invention has been described in detail above. It goes without saying that the present invention is not limited to the specific examples described above, and various modifications and improvements are possible.

  As described above, when the memory 50 is provided as a separate chip from the semiconductor integrated circuit 10 and connected between them by wiring between the chips, the memory 50 is often in an abnormal state, and the usefulness of the present invention is high. In particular, when the semiconductor integrated circuit 10 and the memory 50 stored in different packages are mounted on a wiring board and connected between them by wiring on the wiring board, the memory 50 is likely to be in an abnormal state. The utility of the present invention is high. However, even if the semiconductor integrated circuit 10 and the memory 50 are stored in the same package, the memory 50 may be in an abnormal state, and the present invention is useful. Further, even when the semiconductor integrated circuit 10 is configured as a chip including the memory 50, the capacity and chip size of the memory 50 are increased particularly, and the length of the wiring connecting the memory interface 30 and the memory 50 is increased. If the memory capacity increases, the memory 50 may become abnormal during operation. Even in such a case, the present invention is useful.

1 is a block diagram showing a configuration of an example of a first embodiment of a semiconductor integrated circuit according to the present invention. It is a flowchart which shows an example of embodiment of the memory monitoring in the semiconductor integrated circuit of this invention. It is a block diagram which shows the structure of an example of the apparatus using the semiconductor integrated circuit of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 20 User logic part 30 Memory interface 40 Memory monitoring circuit 50 Memory 70 Display apparatus

Claims (6)

A command monitoring unit that monitors commands sent from the memory interface to the memory;
When the instruction monitoring unit detects an instruction to write to a specific address in the memory, the instruction monitoring unit holds data sent from the memory interface to the memory to write to the specific address, and sets a flag. Write data holding unit to be set;
When the flag is set and the instruction monitoring unit detects an instruction to read from the specific address of the memory, the instruction is read from the specific address and sent to the memory interface. A read data holding unit for holding data;
Memory monitoring comprising a data comparison unit for comparing the data held by the write data holding unit with the data held by the read data holding unit and detecting a mismatch when the read data holding unit holds data A semiconductor integrated circuit comprising a circuit.   2. The semiconductor integrated circuit according to claim 1, wherein the data comparison unit outputs a status notification signal requesting initialization of the memory to the memory interface when the mismatch is detected.   3. The semiconductor integrated circuit according to claim 2, wherein the state comparison signal is output when the data comparison unit detects a mismatch continuously a predetermined number of times. In a semiconductor integrated circuit comprising a user logic unit and a memory interface, and a circuit included in the user logic unit writes data to a memory connected to the outside via the memory interface, and reads data from the memory ,
A command monitoring unit that monitors commands sent from the memory interface to the memory;
When the instruction monitoring unit detects an instruction to write to a specific address of the memory, the instruction monitoring unit holds data sent from the memory interface to the memory to write to the predetermined address, and sets a flag. Write data holding unit to be set;
When the flag is set and the instruction monitoring unit detects an instruction to instruct reading from the specific address of the memory, the instruction is read from the predetermined address and sent to the memory interface. A read data holding unit for holding data;
Memory monitoring comprising a data comparison unit for comparing the data held by the write data holding unit with the data held by the read data holding unit and detecting a mismatch when the read data holding unit holds data A semiconductor integrated circuit comprising a circuit.   5. The semiconductor integrated circuit according to claim 4, wherein the circuit included in the user logic unit is a circuit designed by a customer, and the memory interface and the memory monitoring circuit are prepared as a macro cell by an ASIC manufacturer. circuit.   6. The semiconductor integrated circuit according to claim 4, wherein the data comparison unit outputs a status notification signal for requesting initialization of the memory to the memory interface when the mismatch is detected. .

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