JP2009025677A - Drive control circuit of liquid crystal panel and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive control circuit of a liquid crystal panel, capable of improving display disturbance or flicker due to noncoincidence in synchronization between data rewriting timing and a frame frequency, and reducing power consumption. <P>SOLUTION: An output signal fr synchronized with a frame frequency output from a common output drive circuit 14 is divided as a clock source by a frequency division selection circuit 17; and its output signal 29 is read by a control register 13 and used as a flag. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a drive control circuit for a liquid crystal panel, and more particularly to a drive control circuit for a liquid crystal display (LCD) panel that controls display using a common signal and a segment signal.

  In a liquid crystal display (LCD) panel that controls display using common signals and segment signals, the frame frequency for the entire panel display is generally set to 60 Hz to 120 Hz so that flicker does not occur on the display screen. ing. In accordance with this, the drive control circuit for controlling the display of the liquid crystal panel (hereinafter referred to as the LCD drive control circuit) corresponds to the LCD panel having a different number of common terminals. Frequency division is performed to generate a clock for liquid crystal panel drive control, and the frame frequency is appropriately adjusted.

  For example, Patent Document 1 discloses a technique for extracting a sampling clock by dividing a synchronization period of a horizontal synchronization signal in order to cope with a difference in sampling frequency and a phase shift.

JP 10-39838 A

  On the other hand, data displayed on the LCD panel is generally rewritten periodically using a timer circuit separately from the LCD drive control circuit. For example, when a 16-bit timer is used, the source clock Is 32.768 kHz, for example, a rewrite cycle of 0.5 sec can be made with the count FFFF.

  Here, assuming that the frame frequency is set in a range of 60 Hz to 120 Hz when there are three common terminals, if the source clock is, for example, 32.768 kHz, 256 Hz is obtained by dividing this by 128. obtain. Since there are three common terminals, the frequency is 85.33 Hz (infinite decimal) per one. However, since the rewriting cycle by the timer circuit is 0.5 sec, the frame frequency is in the middle of the 43rd pulse signal. As a result, a rewriting signal is given by the timer circuit, and the data rewriting and the frame frequency cannot be synchronized, resulting in display disturbance and flicker. That is, to be exact, the 42.66th pulse is rounded to the 43rd pulse having an integer value.

  In order to reduce power consumption, there is a case in which control is performed such that only the LCD control circuit is operated while a CPU (Central Processing Unit) that controls the LCD drive control circuit is stopped. For example, an interrupt signal from a timer is generated every second, and the CPU is activated to rewrite data displayed on the LCD panel. However, since it is necessary to operate the timer during the CPU stop period, there is a problem that power consumption occurs for that amount.

  The present invention has been made to solve the above-described problems, and can improve display disturbance and flicker due to inconsistency in synchronization between the data rewrite timing and the frame frequency, and reduce power consumption. It is an object to provide a drive control circuit for a liquid crystal panel.

  In one embodiment of the present invention, the clock source synchronized with the frame frequency is divided by the frequency division selection circuit, and the output signal is read by the control register and used as a rewrite flag for the LCD display data.

  According to the above embodiment, the timing of rewriting the LCD display data can be synchronized with the frame frequency, and the display on the LCD panel and the LCD display data can be synchronized, resulting in display disturbance and flicker. Can be prevented.

  In addition, since the rewrite timing is set by the frequency-divided signal obtained by dividing the clock source, it becomes unnecessary to drive the general-purpose timer and start up the CPU for rewriting, and the circuit and logic scale for period measurement are not required. This is effective in reducing power consumption.

<A. Embodiment 1>
<A-1. Device configuration>
A configuration of LCD drive control circuit 100 according to the first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 1, the LCD drive control circuit 100 is built in the microcomputer 1, and the display operation of the LCD panel 2 is controlled by the microcomputer 1.

  The microcomputer 1 operates based on a clock 4 supplied from an external oscillator 3 and includes modules such as a CPU 5, a memory 6, a timer 7, and an interrupt control circuit 8 in addition to the LCD drive control circuit 100. Are connected to each other via a bus 10.

  An output of the oscillator 3 provided outside is connected to clock terminals 91 and 92, and an inverter 93 is connected between the clock terminals 91 and 92 in the microcomputer 1. The outputs of the clock terminal 91 and the inverter 93 are given to each component in the microcomputer 1 as the clock 4 through the buffer 94.

  Further, the microcomputer 1 initializes each internal module by a RESET signal given to the reset terminal 9.

  The LCD drive control circuit 100 includes a frequency divider 12 that divides the clock 4 and outputs it as an LCD clock CLK, and a register circuit (hereinafter referred to as a control register) 13 that is connected to the CPU 5 via the bus 10. Various settings such as the operation start of the LCD drive circuit and the frequency division setting of the frequency divider 12 are performed by the register 13, but illustration is omitted except for a characteristic signal (control start signal START_TRG).

  The LCD drive control circuit 100 receives the output of the display data memory 14 and the display data memory 14 connected to the CPU 5 via the bus 10 and outputs a segment signal to each segment of the LCD panel 2. A drive circuit 15 and a common output drive circuit 16 for providing a common signal to each segment are provided. The segment output drive circuit 15 is connected to the LCD clock CLK output from the frequency divider 12, the bias potential terminals VL3, VL2, VL1 and the reference potential terminal VSS to which the segment drive bias potential is supplied.

  The display data memory 14 outputs LCD panel display data SEG0DAT [j: 0] to SEGiDAT [j: 0].

  Further, bias voltages VL3, VL2, VL1 for common driving and a reference voltage VSS are supplied to the common output driving circuit 16 and the segment output driving circuit 15 from the bias potential terminals VL3, VL2, VL1 and the reference potential terminal VSS. The LCD clock CLK output from the peripheral 12 is also supplied to the segment output drive circuit 15 and the common output drive circuit 16.

  Then, the output signal fr of the common output drive circuit 16 is given to the frequency division selection circuit 17 constituted by a frequency divider and a selector, and the output signal 29 of the frequency division selection circuit 17 is given to the control register 13. ing.

  The LCD panel 2 includes common terminals COM0 to COMj (which output LCD panel drive waveforms COM0 to COMj) which are also output terminals of the common output drive circuit, and segment terminals which are also output terminals of the segment output drive circuit 15. SEG0 to SEGi (from which LCD panel drive waveforms SEG0 to SEGi are output) are connected.

  The drive control of the LCD panel 2 in the microcomputer 1 shown in FIG. 1 is performed by the CPU 5 controlling the control register 13 and the display data memory 14 of the LCD drive control circuit 100, and the clock 4 is divided by the frequency divider 12. LCD clock CLK obtained by frequency division is applied to segment output drive circuit 15 and common output drive circuit 16, and LCD panel drive waveforms SEG0 to SEGi and COM0 to COMj are output in synchronization with LCD clock CLK, respectively. The

  FIG. 2 shows details of the common output drive circuit 16 and the frequency division selection circuit 17 of the LCD drive control circuit 100 shown in FIG.

  In FIG. 2, the segment terminals of the segment output drive circuit 15 shown in FIG. 1 are i = 3, that is, SEG0 to SEG3, and the common terminals of the common output drive circuit 16 are j = 2, that is, COM0 to COM2. An example is shown. In this case, LCD panel display data SEG0DAT [2: 0] to SEG3DAT [2: 0] are output from the display data memory 14.

  As shown in FIG. 2, the frequency division selection circuit 17 includes AND circuits G1 to G3 and flip-flops F1 to F3, a frequency divider that divides the signal fr synchronized with the frame frequency, and a selector 28. Therefore, the output of the selector 28 becomes the output signal 29 of the frequency division selection circuit 17.

  The AND circuit G1 receives the LCD clock CLK output from the frequency divider 12 and the output signal fr from the common output drive circuit 16, and the output signal 24 from the AND circuit G1 is applied to the inverted clock input terminal of the flip-flop F1. At the same time, it is also given to the input of the AND circuit G2. The frequency-divided signal 25 output from the Q output terminal of the flip-flop F1 is applied to the inverting D input terminal of the flip-flop F1, the input of the AND circuit G2, and the input of the selector 28.

  The output signal 30 of the AND circuit G2 is supplied to the inverted clock input terminal of the flip-flop F2 and also to the input of the AND circuit G3. The frequency-divided signal 26 output from the Q output terminal of the flip-flop F2 is applied to the inverting D input terminal of the flip-flop F2, the input of the AND circuit G3, and the input of the selector 28.

  The output signal 31 of the AND circuit G3 is given to the inverted clock input terminal of the flip-flop F3. The frequency-divided signal 27 output from the Q output terminal of the flip-flop F3 is applied to the inverting D input terminal of the flip-flop F3 and the input of the selector 28.

  Note that the reset terminal (not shown) of the flip-flops F1 to F3 is supplied with a RESET signal from the reset terminal 9 (FIG. 1).

  Under the control of the control register 13, the selector 28 outputs the ground connection signal as the output signal 29 when the divided waveform of the divided signals 25 to 27 or the divided waveform is not used.

  As described above, by generating a plurality of frequency-divided signals having different frequency-dividing ratios and selecting the frequency-divided signals using the selector 28, signals having various periods can be obtained as the output signal 29. It is possible to deal with various LCD panels having different numbers of common terminals.

  In the frequency division selection circuit 17 described above, the number of stages of the flip-flops of the frequency divider is 3, and the signal up to the frequency division by 8 can be selected by the selector 28. The number of stages is larger, and the division ratio is set to be larger. For example, when the frame frequency is set to 60 Hz by the setting of the frequency divider 12 with respect to the frequency of the clock 4 and the number of common terminals to be used (three in this embodiment), the frequency dividing selection circuit 17 sets the frequency to 32. If the frequency-divided signal is selected by the selector 28, the output signal 29 having a period of 0.533 seconds can be taken out.

  As shown in FIG. 2, the common output driving circuit 16 receives a shift register composed of an OR circuit G5 and flip-flops F4 to F6, and outputs from the shift register, and receives bias voltages VL3, VL2, VL1, and And a bias control circuit 230 that converts the level to VSS and outputs the result.

  The OR circuit G5 receives the control start signal START_TRG and the output signal fr output from the control register 13, and the output signal 20 of the OR circuit G5 is applied to the D input terminal of the flip-flop F4. The LCD clock CLK output from the frequency divider 12 is applied to the inverted clock input terminal of the flip-flop F4.

  The output signal 21 of the flip-flop output from the Q output terminal of the flip-flop F4 is supplied to the D input terminal of the flip-flop F5, and is also supplied to the buffer B1 constituting the bias control circuit 230, via the buffer B1. After level conversion, the signal is applied to the common terminal COM0. Further, the LCD clock CLK output from the frequency divider 12 is applied to the inverted clock input terminal of the flip-flop F5.

  The output signal 22 of the flip-flop output from the Q output terminal of the flip-flop F5 is supplied to the D input terminal of the flip-flop F6, and is also supplied to the buffer B2 constituting the bias control circuit 230, via the buffer B2. After level conversion, the signal is applied to the common terminal COM1. Further, the LCD clock CLK output from the frequency divider 12 is applied to the inverted clock input terminal of the flip-flop F6.

  An output signal fr is output from the Q output terminal of the flip-flop F5. The output signal fr is supplied to the OR circuit G5 and the frequency division selection circuit 17, and is also supplied to the buffer B3 constituting the bias control circuit 230. After level conversion via B3, it is applied to the common terminal COM2. The output signals 21, 22 and fr are also given to the segment output drive circuit 15.

  A reset signal (not shown) of the flip-flops F4 to F6 is supplied with a RESET signal from the reset terminal 9 (FIG. 1).

<A-2. Device operation>
Next, the operation of the LCD drive control circuit 100 will be described using the timing chart shown in FIG. 5 with reference to FIGS. In the following, the case where the frequency division signal 25 is used as the output signal 29 of the frequency division selection path 17 is shown.

  The LCD drive control circuit 100 shown in FIG. 2 starts its operation in response to the LCD control start signal START_TRG output from the control register 13.

  When the LCD control start signal START_TRG becomes “H” level, the common output drive circuit 16 shifts the “H” level in the order of the output signals 21, 22 and fr of the flip-flop at the falling timing of the LCD clock CLK. The output signal fr of the flip-flop at the stage is fed back to become the output signal 20 of the OR circuit G5.

  These signals 21, 22, fr are level-converted into bias voltages VL 3, VL 2, VL 1 and VSS by the bias control circuit 230, and are output as LCD panel drive waveforms COM 0, COM 1 and COM 2.

  Similarly, these signals 21, 22, fr are also supplied to the segment output drive circuit 15, and the LCD panel display data SEG0DAT [2: 0] to SEG3DAT [2: 0] are supplied to the segment output drive circuit based on this signal. 15 is level-converted to bias voltages VL3, VL2, VL1 and VSS by a bias control circuit (see FIG. 3 for the configuration) and output as LCD panel drive waveforms SEG0 to SEG3. This operation will be further described based on FIG. 3 showing the configuration of the segment output drive circuit 15.

  That is, as shown in FIG. 3, the segment output drive circuit 15 receives the LCD panel display data SEG0DAT [2: 0] to SEG3DAT [2: 0], and based on the signals 21, 22, fr (COM selection signal). Selector 151 for selecting and outputting, and bias control circuit for converting the level of LCD panel display data SEG0DAT [2: 0] to SEG3DAT [2: 0] selected by selector 151 into bias voltages VL3, VL2, VL1 and VSS 152. In the bias control circuit 152, the output from the selector 151 is given to each of the buffers B11, B12, B13, and B14.

  When the LCD panel display data SEG0DAT [2: 0] to SEG3DAT [2: 0] is input to the selector 151, the SEG0DAT is generated based on the COM selection signals 21, 22 and fr generated by the common output drive circuit 16. [2: 0] to SEG3DAT [2: 0] Each bit is selected. That is, if the signal 21 is “H”, SEG0DAT [0] to SEG3DAT [0] are selected, and if the signal 22 is “H”, SEG0DAT [1] to SEG3DAT [1] are selected and the signal fr is selected. Is “H”, SEG0DAT [2] to SEG3DAT [2] are selected, supplied to the buffers B11 to B14 constituting the bias control circuit 152, respectively, and after level conversion via the buffers B11 to B14, It is given to segment terminals SEG0 to SEG3.

  The configuration and operation of the display data memory 14 will be described with reference to FIG. As shown in FIG. 4, the display data memory 14 has memory bits 141 for holding data for each segment.

  FIG. 4 shows an example in which SEG0 data is stored at address 00h, SEG1 data is stored at address 01h, SEG2 data is stored at address 02h, and SEG3 data is stored at address 03h. Data to be displayed when COM1 and COM2 are selected is held. The contents of these memory bits 141 are: SEG0 display data is SEG0DAT [2: 0], SEG1 display-data is SEG1DAT [2: 0], SEG2 display data is SEG2DAT [2: 0], SEG3 display data Are output as SEG3DAT [2: 0].

  Returning to the description of FIG. The range of the LCD clock CLK indicated as f (FR) in FIG. 5 indicates a period required for one cycle of the COM0, COM1, and COM2 output from the common output drive circuit 16, and is generally one frame of the liquid crystal panel. It is called a frame frequency defined by the reciprocal of the time spent for displaying minutes, and is set using a frequency divider or the like so as to be in the range of 60 Hz to 120 Hz in normal LCD panel control.

  In FIG. 2, the common terminal of the common output driving circuit 16 is shown as three common terminals COM0 to COM2. However, in order to correspond to various LCD panels in practice, as shown by COMj in FIG. If the number is larger than that, for example, it may be eight. In general, only four terminals are used by setting the control register 13 while having eight common terminals.

  The segment output drive circuit 15 uses the LCD panel display data SEG0DAT [2: 0], SEG1DAT [2: 0], SEG2DAT [2: 0] and SEG3DAT [2: 0] supplied from the display data memory 14, for example, As shown in the SEG0 waveform of FIG. 5, signals corresponding to COM0, COM1, and COM2 are output.

  That is, SEG0DAT [2: 0] corresponds to SEG0, SEG0DAT [0] corresponds to COM0, SEG0DAT [1] corresponds to COM1, SEG0DAT [2] corresponds to COM2, and the potential difference between SEG0 and one of COM0 to COM2 The segment connected to the combination with the maximum potential difference lights up.

  In the example of FIG. 5, in the first LCD panel drive waveform COM0, the potential difference from the SEG0 waveform has the maximum amplitude (VL3), and the segment connected to the common terminal COM0 and the segment terminal SEG0 is lit (“1”). The subsequent potential difference between the LCD panel drive waveform COM1 and the SEG0 waveform does not have the maximum amplitude, and the segment connected to the common terminal COM0 and the segment terminal SEG0 is turned off ("0").

  Similarly, SEG1DAT [2: 0] is display data corresponding to SEG1, and SEG2DAT [2: 0] is display data corresponding to SEG2.

  In general, the number of segments is the same as the number of common terminals, and can be a number corresponding to the LCD panel, for example, 32 or 40.

  In the example of FIG. 5, SEG0DAT [2: 0] is rewritten for each frame frequency, but actually, at least a time interval that can be visually recognized by human eyes, that is, 0.5 seconds or 1 The display data of SEG0DAT [2: 0], SEG1DAT [2: 0], SEG2DAT [2: 0], and SEG3DAT [2: 0] is rewritten at intervals of seconds by a built-in CPU or DMA (Direct Memory Access) controller. .

  The frequency division selection circuit 17 divides the output signal fr of the flip-flop that is output from the common output drive circuit 16 and is synchronized with the frame frequency as a clock source, thereby dividing the frequency suitable for the timing of rewriting the LCD display data. Signals 25, 26 and 27 can be output.

  That is, as shown in FIG. 5, when any one of the divided signals 25, 26, and 27 is selected, the divided signal rises at the timing between the COM2 waveform and the subsequent COM0 waveform. By rewriting 2: 0], data rewriting can be synchronized with the frame frequency, and display disturbance and flicker can be prevented.

  Further, since the frequency divider 12 divides the clock 4 having a high frequency to a low frequency suitable for generating the frame frequency, the power consumption in the LCD drive control circuit 100 can be kept low. Further, since the frequency divider 12 divides the frequency to a low frequency in advance, the frequency division in the frequency division selection circuit 17 which is the next stage can be reduced, and a simple control circuit can be used. The circuit size of the circumference selection circuit 17 can be reduced, and the power consumption can be reduced.

<A-3. Effect>
As described above, in the LCD drive control circuit 100 according to the first embodiment, the frequency selection circuit 17 divides the output signal fr synchronized with the frame frequency as the clock source, and the output signal 29 is controlled by the control register 13. By reading and using it as a flag, the timing of rewriting the LCD display data can be synchronized with the frame frequency. Thereby, the display on the LCD panel 2 and the LCD display data can be synchronized, and display disturbance and flickering can be prevented.

  Conventionally, a general-purpose timer is used to measure the timing of rewriting display data. However, in this embodiment, the signal generated by the LCD drive control circuit 100, that is, the output signal fr synchronized with the frame frequency is clocked. Since the rewriting timing is set by the frequency-divided signal as the source, it is not necessary to drive a general-purpose timer, and the circuit and logic scale for period measurement are reduced, thereby reducing power consumption.

  In FIG. 2, the segment terminals of the segment output drive circuit 15 shown in FIG. 1 are i = 3, that is, SEG0 to SEG3, and the common terminals of the common output drive circuit 16 are j = 2, that is, COM0 to COM2. FIG. 6 shows the display data memory 14, the segment output drive circuit 15, the common output drive circuit 16, and the frequency division selection circuit 17 in accordance with FIG.

  In FIG. 6, the segment terminals of the segment output drive circuit 15 are shown as SEG0 to SEGi, and the common terminals of the common output drive circuit 16 are shown as COM0 to COMj. In this case, LCD panel display data SEG0DAT [k: 0] to SEGiDAT [k: 0] are output from the display data memory 14.

  The frequency divider of the frequency division selection circuit 17 is composed of AND circuits G21 to G2j and flip-flops F1 to Fj, and the AND circuits G21 to G2j output output signals 241 to 24j, respectively. Further, frequency-divided signals 251 to 25j are output from the Q output terminals of the flip-flops F1 to Fj, respectively, and are fed back to the inputs of the AND circuits G21 to G2j and input to the selector 28, respectively.

  Under the control of the control register 13, the selector 28 outputs the ground connection signal as the output signal 29 when the divided waveform of the divided signals 251 to 25 j or the divided waveform is not used.

  The common output drive circuit 16 receives a shift register composed of an OR circuit G5 and flip-flops F41 to F4j and the output of the shift register, converts the level into bias voltages VL3, VL2, VL1, and VSS and outputs the result. And a bias control circuit 230.

  The output signal 21 of the flip-flop output from the Q output terminal of the flip-flop F41 is supplied to the D input terminal of the flip-flop F42, and is also supplied to the buffer B1 constituting the bias control circuit 230, via the buffer B1. After level conversion, the signal is applied to the common terminal COM0. Further, the LCD clock CLK output from the frequency divider 12 is applied to the inverted clock input terminal of the flip-flop F42.

  The output signal 22 of the flip-flop output from the Q output terminal of the flip-flop F42 is supplied to the D input terminal of the flip-flop (not shown) at the next stage and also to the buffer B2 constituting the bias control circuit 230. Then, after level conversion via the buffer B2, it is applied to the common terminal COM1.

  The output signal 2j (= fr) is output from the Q output terminal of the flip-flop F4j at the final stage, and the output signal 2j (= fr) is supplied to the OR circuit G5 and the frequency division selection circuit 17 and also the bias control circuit 230. Is also supplied to the buffer Bj, and after level conversion via the buffer Bj, it is supplied to the common terminal COMj.

  The output signals 21 to 2j are also supplied to the selector 151 of the segment output drive circuit 15.

<B. Second Embodiment>
<B-1. Device configuration>
The configuration of the LCD drive control circuit 200 according to the second embodiment of the present invention will be described with reference to FIG. Note that the same components as those of the LCD drive control circuit 100 shown in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.

  The LCD drive control circuit 200 shown in FIG. 7 includes a counter circuit 50 instead of the frequency division selection circuit 17 of the LCD drive control circuit 100 shown in FIG.

  The counter circuit 50 includes a reload register 51 in which a count value is set via the bus 10, a counter 53 to which the count value is transferred via the bus 52, and an underflow signal output when the counter 53 underflows. The flip-flop output signal 54 output from the Q output terminal is applied to the inverted D input terminal, and the flip-flop F10 applied to the control register 13 as the output signal of the counter circuit 50. have. A reset signal (not shown) of the flip-flop F10 is supplied with a RESET signal from the reset terminal 9 (FIG. 1).

  The counter 53 receives the output signal 38 of the AND circuit G10 to which the LCD clock CLK output from the frequency divider 12 and the output signal fr of the common output driving circuit 16 are applied.

<B-2. Device operation>
Next, the operation of the LCD drive control circuit 200 will be described using the timing chart shown in FIG. 8 with reference to FIG.

  Assuming that an arbitrary count value X is set in the reload register 51 from the CPU 5 via the bus 10 to the reload register 51, the AND circuit G10 at the timing when the LCD clock CLK is “H” after the rise of the output signal fr. Output signal 38 rises and the counter 53 counts down. However, since the counter 53 is in the underflow state (00h) at the time when the first output signal 38 rises, the counter 53 outputs the underflow signal 39 and reloads the count value X from the reload register 51. . In the reload register 51, after the count value X is reloaded, the next count value Y is set from the CPU 5 via the bus 10.

  After reloading the count value X, the countdown is performed for each frame frequency f (FR), and the countdown is performed until the underflow state is reached.

  Upon receiving the underflow signal 39, the flip-flop F10 raises the output signal 54 of the flip-flop and outputs it as a count end signal.

  The output signal 54 of the flip-flop is read by the control register 13 and used as a flag, so that the timing for rewriting the LCD display data can be set.

<B-3. Effect>
As described above, in the LCD drive control circuit 200 according to the second embodiment, the counter circuit 50 down-counts the count value arbitrarily set in the counter 53 at the frame frequency interval. The frequency can be counted, and the timing for rewriting the LCD display data can be set more finely.

  For example, when the rewriting timing is set by dividing the frame frequency as the clock source, the frequency dividing intervals are 2, 4, and 8, and the rewriting timing is relatively rough. However, in the LCD drive control circuit 200 of the second embodiment, it is possible to set a finer timing such as two frame frequencies and three frame frequencies.

<C. Embodiment 3>
<C-1. Device configuration>
The configuration of LCD drive control circuit 300 according to the third embodiment of the present invention will be described with reference to FIG. Note that the same components as those of the LCD drive control circuit 100 shown in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.

  The LCD drive control circuit 300 shown in FIG. 9 includes a frequency division selection circuit 17A instead of the frequency division selection circuit 17 of the LCD drive control circuit 100 shown in FIG.

  As shown in FIG. 9, in addition to the AND circuits G1 to G3, the frequency division selection circuit 17A receives the Q output of the flip-flop F3 and the output signal 31 of the AND circuit G3, and outputs an output signal 32. G4, and further receives the output signals 24, 30, 31, and 32 of the AND circuits G1 to G4, selects one based on the control of the control register 13, and outputs it as the output signal 34. A selector 33 is provided.

  In other words, the selector 33 selects and outputs one of the frequency-divided signals 25, 26 and 27 of the frame frequency and the output signal 24 of the AND circuit G1 which is the frame frequency itself.

  The output signal 34 is output to the outside of the LCD drive control circuit 300, and is used as an interrupt signal for requesting rewriting of LCD display data synchronized with the frame frequency by giving it to the CPU 5 shown in FIG. 1 or a DMA controller (not shown). be able to.

<C-2. Device operation>
Next, the operation of the LCD drive control circuit 300 will be described using the timing chart shown in FIG. 10 with reference to FIG. In the following, it is assumed that the frequency division signal 25 is used as the output signal 29 of the frequency division selection path 17A.

  FIG. 10 shows the waveform of the output signal 34 when the output signal 30 is selected by the selector 33. At the timing when the output signal 30 rises after the output signal 30 is selected by the selection operation of the selector 33, 34 will stand up.

<C-3. Effect>
As described above, in the LCD drive control circuit 300 according to the third embodiment, the frequency division selection circuit 17A generates a frame frequency or a signal obtained by dividing the frame frequency, and rewrites the LCD display data. By using it as an interrupt signal to request, it is possible to arbitrarily make a rewrite request for LCD display data in synchronization with the frame frequency to the CPU 5 or DMA controller.

  When the output signal 34 is given to the DMA controller, it is not necessary to start not only the CPU but also a memory for storing the instruction code of the CPU as compared with the case where the CPU 5 is started to rewrite the LCD display data. Thus, power consumption can be reduced.

<C-4. Modification>
Instead of the frequency division selection circuit 17A in the LCD drive control circuit 300, the counter circuit 50 shown in FIG. 7 can be applied.

  The LCD drive control circuit 300A shown in FIG. 11 includes a counter circuit 50 instead of the frequency division selection circuit 17A shown in FIG. The counter circuit 50 is basically the same as that described with reference to FIG. 7, but uses an underflow signal 39 output from the counter 53 as an interrupt signal for requesting rewriting of LCD display data. Yes.

  The operation of the counter circuit 50 is the same as that described with reference to FIG.

  Since an interrupt signal can arbitrarily generate a rewrite request for LCD display data in synchronization with the frame frequency, display data can be updated easily.

<D. Embodiment 4>
<D-1. Device configuration>
The configuration of LCD drive control circuit 400 according to the fourth embodiment of the present invention will be described with reference to FIG. Note that the same components as those of the LCD drive control circuit 100 shown in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.

  In the LCD drive control circuit 400 shown in FIG. 12, LCD panel display data SEG0DAT [2: 0] to SEG3DAT [2: 0] are provided to the segment output drive circuit 15 via the LCD display data control circuit 40, respectively. It has become.

  Each LCD display data control circuit 40 receives display change data M0DAT [2: 0] to M3DAT [2: 0] output from the display change memory 41 in addition to the LCD panel display data.

  That is, the LCD panel display data SEG0DAT [2: 0] and the display change data M0DAT [2: 0] are input to one of the LCD display data control circuits 40 as a set. An output signal 43 is output. Similarly, LCD panel display data SEG1DAT [2: 0] and display change data M1DAT [2: 0] form a pair, and LCD panel display data SEG2DAT [2: 0] and display change data M2DAT [2: 0] Form a pair, and the LCD panel display data SEG3DAT [2: 0] and the display change data M3DAT [2: 0] form a pair and are input to the LCD display data control circuit 40, respectively.

  Here, the configuration of the LCD display data control circuit 40 will be described by taking the LCD display data control circuit 40 to which the LCD panel display data SEG0DAT [2: 0] and the display change data M0DAT [2: 0] are input as an example. To do.

  As shown in FIG. 12, the LCD display data control circuit 40 has 3-input AND circuits G11 and G12, a 2-input ExOR circuit G13, and a 2-input AND circuit G14.

  The display change data M0DAT [2: 0] is input in common to the AND circuits G11 and G12, and the output signal 29 of the frequency division selection circuit 17 and the selection signal 42 output from the control register 13 are AND circuits G11 and G12. Are input in common. In the AND circuit G11, the selection signal 42 is input to the inverting input terminal.

  The output of the AND circuit G11 is input to the inverting input terminal of the AND circuit G14, and the output of the AND circuit G12 is input to the ExOR circuit G13. Further, the LCD panel display data SEG0DAT [2: 0] is input to the ExOR circuit G13, the output of the ExOR circuit G13 is input to the AND circuit G14, and the output of the AND circuit G14 is the output of the LCD display data control circuit 40. Signal 43 is obtained.

  In the LCD display data control circuit 40 having such a configuration, each bit of the display change data M0DAT [2: 0] corresponding to each bit of the LCD panel display data SEG0DAT [2: 0] is “H”. If there is, the value of the LCD panel display data SEG0DAT is forcibly inverted or set to all “0”.

  Here, whether to invert or “0” is determined by the selection signal 42 given from the control register 13, and the period of inversion or “0” is controlled using the output signal 29 of the frequency division selection circuit 17. Can do.

<D-2. Device operation>
Next, the operation of the LCD drive control circuit 400 will be described using the timing chart shown in FIG. 13 with reference to FIG.

  FIG. 13 shows the segment control state by the output signal 43 of the control circuit 40 when the selection signal 42 is “0” or “1”, and the segment control state when SEG0DAT [2: 0] is given as it is. It also shows.

  Note that FIG. 13 shows the case where the frequency-divided signal 25 is used as the output signal 29 of the frequency-division selection circuit 17, and SEG0DAT [2: 0] in the period when the output signal 29 is “H”. Is in a control state different from the control state of the segment in the case where is given as it is.

  That is, when the output signal 29 is “H”, when the selection signal 42 is “1”, the display is inverted, and when the selection signal 42 is “0”, all the segments are turned off. It is controlled to become.

<D-3. Effect>
As described above, in the LCD drive control circuit 400 according to the fourth embodiment, the display on the LCD panel 2 and the LCD display data can be synchronized, and display disturbance and flicker can be prevented. Further, since the LCD display data can be inverted or controlled to be “0” (that is, extinguished) during a period defined based on a signal obtained by dividing the frame frequency as a clock source, It is possible in hardware to blink the display or to repeat the reverse display and the normal display.

<D-4. Modification 1>
Instead of the frequency division selection circuit 17 in the LCD drive control circuit 400, the counter circuit 50 shown in FIG. 7 can be applied.

  The LCD drive control circuit 400A shown in FIG. 14 includes a counter circuit 50 instead of the frequency division selection circuit 17 shown in FIG. The counter circuit 50 is basically the same as the configuration described with reference to FIG. 7, but uses the output signal 54 of the flip-flop to set the timing for rewriting the LCD display data and inverts the value of the LCD panel display data. This configuration is used for control or setting of a period fixed to “0”. The operation of the counter circuit 50 is the same as that described with reference to FIG.

  Further, as described with reference to FIG. 11, it goes without saying that an underflow signal 39 output from the counter 53 may be used as an interrupt signal for requesting rewriting of LCD display data.

<D-5. Modification 2>
Instead of the frequency division selection circuit 17 in the LCD drive control circuit 400, the frequency division selection circuit 17A shown in FIG. 9 can be applied.

  The LCD drive control circuit 400B shown in FIG. 15 includes a frequency division selection circuit 17A instead of the frequency division selection circuit 17 shown in FIG.

  The frequency division selection circuit 17A is basically the same as the configuration described with reference to FIG. 12, but the output signal 29 of the frequency division selection circuit 17A is used for setting the timing for rewriting the LCD display data, and the LCD panel. The display data value is used for inversion control or for setting a period for fixing to “0”. The operation of the frequency division selection circuit 17A is the same as the operation described with reference to FIG.

  By adopting such a configuration, it is possible to synchronize the display on the LCD panel 2 and the LCD display data, and to prevent display disturbance and flickering. Further, the LCD display data can be inverted or controlled to be “0” (that is, turned off) during a period defined based on a signal obtained by dividing the output signal fr synchronized with the frame frequency as a clock source. Therefore, the display on the LCD panel 2 can be blinked, and the reverse display and the normal display can be repeated in hardware.

  Further, the display data can be easily updated by generating an LCD display data rewrite request synchronized with the frame frequency after the data display and its inverted data are displayed by the interrupt signal.

It is a block diagram which shows the structure of the microcomputer incorporating the LCD drive control circuit of Embodiment 1 which concerns on this invention. It is a block diagram which shows the structure of the LCD drive control circuit of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the segment output drive circuit of the LCD drive control circuit of Embodiment 1 which concerns on this invention. It is a figure which shows the structure of the memory for display data of the LCD drive control circuit of Embodiment 1 which concerns on this invention. 5 is a timing chart for explaining the operation of the LCD drive control circuit according to the first embodiment of the present invention. It is a block diagram which shows the structure of the LCD drive control circuit of Embodiment 1 which concerns on this invention. It is a block diagram which shows the structure of the LCD drive control circuit of Embodiment 2 which concerns on this invention. 6 is a timing chart for explaining the operation of the LCD drive control circuit according to the second embodiment of the present invention. It is a block diagram which shows the structure of the LCD drive control circuit of Embodiment 3 which concerns on this invention. It is a timing chart explaining operation | movement of the LCD drive control circuit of Embodiment 3 which concerns on this invention. It is a block diagram which shows the structure of the modification of the LCD drive control circuit of Embodiment 3 which concerns on this invention. It is a block diagram which shows the structure of the LCD drive control circuit of Embodiment 4 which concerns on this invention. It is a timing chart explaining operation | movement of the LCD drive control circuit of Embodiment 4 which concerns on this invention. It is a block diagram which shows the structure of the modification 1 of the LCD drive control circuit of Embodiment 4 which concerns on this invention. It is a block diagram which shows the structure of the modification 2 of the LCD drive control circuit of Embodiment 4 which concerns on this invention.

Explanation of symbols

  fr Clock source, 29-divided signal, 54 count end signal.

Claims (9)

A liquid crystal panel drive control circuit for controlling a plurality of segments constituting the liquid crystal panel with a common signal and a segment signal,
A common output driving circuit for supplying the common signal to the plurality of segments and outputting a clock source synchronized with a frame frequency defined by a reciprocal of time spent for displaying one frame of the liquid crystal panel;
A frequency dividing circuit that receives the clock source, divides and outputs a divided signal;
A drive control circuit for a liquid crystal panel, which sets a rewrite timing of display data of the liquid crystal panel according to the divided signal. A display data control circuit for forcibly changing the display data so that the display state of the plurality of segments of the liquid crystal panel is in an inverted state or an extinguished state;
The liquid crystal panel drive control circuit according to claim 1, wherein a period during which the display data is forcibly changed is set using the divided signal. The divider circuit is
Multiple flip-flops,
3. A first selector that receives signals having different division ratios output from the plurality of flip-flops, selects one of the signals, and outputs the selected signal as the divided signal. 4. LCD panel drive control circuit. The divider circuit is
4. The liquid crystal panel according to claim 3, further comprising: a second selector that receives each of the signals output from the plurality of flip-flops, and outputs one of the signals as an interrupt signal for requesting rewriting of the display data. Drive control circuit. A liquid crystal panel drive control circuit for controlling a plurality of segments constituting the liquid crystal panel with a common signal and a segment signal,
A common output driving circuit for supplying the common signal to the plurality of segments and outputting a clock source synchronized with a frame frequency defined by a reciprocal of time spent for displaying one frame of the liquid crystal panel;
A counter circuit that receives the clock source, counts the frame frequency, and outputs a count end signal when a predetermined count value is reached;
A liquid crystal panel drive control circuit for setting a rewrite timing of display data of the liquid crystal panel according to the count end signal. A display data control circuit for forcibly changing the display data so that the display state of the plurality of segments of the liquid crystal panel is in an inverted state or an extinguished state;
6. The drive control circuit for a liquid crystal panel according to claim 5, wherein a period during which the display data is forcibly changed is set using the count end signal. The counter circuit is
A counter that decrements a preset count value each time the frame frequency is counted;
The liquid crystal panel according to claim 5, further comprising: a flip-flop that receives an underflow signal that is output when the counter underflows and outputs the count end signal in synchronization with the underflow signal. Drive control circuit. The counter circuit is
The liquid crystal panel drive control circuit according to claim 7, wherein the underflow signal is output as an interrupt signal for requesting rewriting of the display data. A semiconductor device incorporating the drive control circuit for a liquid crystal panel according to claim 1,
The drive control circuit of the liquid crystal panel includes a frequency divider that divides an external clock supplied from the outside of the semiconductor device,
The divider circuit is
A semiconductor device that divides the clock source based on a clock divided by the frequency divider.

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