JP2009022125A - Method of controlling switching power supply - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable suppressing variation in output voltage without causing scale-up or cost increase of a switching power supply unit. <P>SOLUTION: The switching power supply unit is provided with an error amplifier 7 for amplifying an error between a DC output and a first reference voltage, and a carrier signal generator 8, wherein a comparator 9 turns on/off the switching elements 1, 2 on the basis of a result of comparison between the output of the error amplifier and the carrier signal to obtain a constant DC output. The switching power supply unit is provided with a comparator 15 and the switching elements are forcibly switched on at a timing at which the output of the error amplifier 7 exceeds a second reference voltage Vt so that a loss time in switching is eliminated and the variation in output voltage is suppressed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a switching power supply device, and more particularly to control of a DC / DC converter that obtains a constant DC output from a DC power supply.

  FIG. 3 shows a general example of a step-down chopper which is a kind of switching power supply device. In the figure, 1 and 2 are MOSFETs (metal oxide field effect transistors) as switching elements, 3 is a DC power supply, 4 is an inductor, 5 is a smoothing capacitor, 6 is a load, 7 is an error amplifier, and 8 is a carrier signal generator. 9 is a comparator, 10 is a flip-flop, 11 and 12 are on-delay circuits, and 13 and 14 are gate drivers.

  The output voltage Vo is obtained by smoothing a rectangular wave voltage generated by turning on / off the MOSFET 1 with a smoothing circuit including the inductor 4 and the smoothing capacitor 5. The MOSFET 2 is a switching element for synchronous rectification that is turned on and off alternately with the MOSFET 1 to reduce conduction loss during the return period. By controlling the on-duty of the MOSFET 1, a constant output voltage is obtained. It is.

The control operation in FIG. 3 will be described with reference to the waveform diagrams of the respective parts in FIG.
The carrier signal generator 8 generates a sawtooth wave signal Vc as a carrier signal and a synchronization signal Vs synchronized with the falling edge of the sawtooth wave. The flip-flop 10 is set (S) by the synchronization signal Vs, and the ON timing of the MOSFET 1 and the OFF timing of the MOSFET 2 are determined.

  The error amplifier 7 compares the magnitude of the signal Vfb obtained by amplifying the error between the output voltage Vo and a reference voltage (set voltage) (not shown) with the sawtooth wave Vc by the comparator 9 and flips the signal when Vc exceeds Vfb. The timing of turning off the MOSFET 1 and the timing of turning on the MOSFET 2 are determined.

  When the output voltage exceeds the set voltage, the error amplification signal Vfb is lowered, the on-duty of the MOSFET 1 is reduced, and the output voltage is lowered. On the other hand, when the output voltage falls below the set voltage, the error amplification signal Vfb increases, and the on-duty of the MOSFET 1 increases to operate so as to increase the output voltage, thereby obtaining a set constant output voltage. The on-delay circuits 11 and 12 prevent the MOSFET 1 and the MOSFET 2 from being simultaneously turned on, and the gate drivers 13 and 14 amplify a logic level signal and drive the MOSFETs 1 and 2.

By the way, the operation speed of a CPU used for a microprocessor or the like has been drastically improved in recent years, and the slew rate (change rate) of a current supplied from a step-down chopper circuit as a power source thereof is several hundred to several thousand A / In such applications, suppression of fluctuations in output voltage is a problem.
Therefore, for example, Patent Literature 1 discloses a technique for suppressing fluctuations in output voltage with respect to a slew rate with a steep current by detecting an inductor current and feeding it back to a control element for control.

Japanese Patent Laid-Open No. 06-233530

  As for the control response time of the switch element that controls the output voltage, the response time exceeding the switching cycle cannot be obtained because the switching cycle becomes a dead time. For this reason, when the switching frequency is increased, the loss increases, and there is a problem that the cooling element of the switch element is enlarged. Further, even if the capacity of the smoothing capacitor is increased, fluctuations in the output voltage can be suppressed, but the size and cost of the apparatus are increased.

  Accordingly, an object of the present invention is to suppress output voltage fluctuations without increasing the size and cost of the switching power supply device.

In order to solve such a problem, the invention of claim 1 comprises error amplifying means for amplifying an error between the DC output voltage and the first reference voltage, and carrier signal generating means, the carrier signal and the error. Based on the comparison result with the output of the amplifying means, the switch element connected to the DC power source is turned on / off to obtain a constant DC output,
The switch element is forcibly turned on at a timing when the output of the error amplifying means exceeds the second reference voltage.

  According to the present invention, since the dead time at the time of switching is eliminated, fluctuations in the output voltage can be suppressed in a small size and at a low cost without increasing the switching frequency or increasing the smoothing capacitor capacity.

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.
The difference from FIG. 3 is that the comparator 15 compares the output signal (error amplified signal) Vfb of the error amplifier 7 with Vt, the timing when Vfb exceeds Vt, or the synchronization signal Vs output from the carrier signal generator 8. The OR circuit 17 for setting the flip-flop 10 is provided at the earlier timing.

  The reference voltage Vt to be compared with Vfb by the comparator 15 is a predetermined value, and is set to a value larger than the error amplification signal Vfb at the time when the output current Io is zero or hardly flowing, that is, at a light load. Further, the value is set smaller than the amplitude of the sawtooth wave signal Vc. In order to react quickly to a sudden change in the output current Io, Vt should be close to the error amplification signal Vfb at light load. However, since the noise superimposed on Vfb exceeds Vt, the flip-flop 10 is erroneously set. In order to prevent this, Vt may be set to about 80 to 90% of the amplitude of the sawtooth wave signal Vc.

FIG. 2 is an explanatory diagram for explaining the operation of FIG.
3 and 4, the carrier signal generator 8 generates a sawtooth wave signal Vc as a carrier signal and a synchronization signal Vs synchronized with the falling edge of the sawtooth wave. Normally, the flip-flop 10 is set (S) by the synchronization signal Vs, and the ON timing of the MOSFET 1 and the OFF timing of the MOSFET 2 are determined.

The error amplifier 7 compares the magnitude of the signal Vfb obtained by amplifying the error between the output voltage Vo and a reference voltage (set voltage) (not shown) with the sawtooth wave Vc by the comparator 9 and flips the signal when Vc exceeds Vfb. 10 is reset, and the timing for turning off the MOSFET 1 and the timing for turning on the MOSFET 2 are determined.
When the output voltage exceeds the set voltage, the error amplification signal Vfb is lowered, the on-duty of the MOSFET 1 is reduced, and the output voltage is lowered. On the other hand, when the output voltage falls below the set voltage, the error amplification signal Vfb increases, and the on-duty of the MOSFET 1 increases to operate so as to increase the output voltage, thereby obtaining a set constant output voltage. The on-delay circuits 11 and 12 prevent the MOSFET 1 and the MOSFET 2 from being simultaneously turned on, and the gate drivers 13 and 14 amplify a logic level signal and drive the MOSFETs 1 and 2.

  If the output current Io rises steeply as shown in the figure, the output voltage Vo starts to decrease and the error amplification signal Vfb increases. When the error amplification signal Vfb exceeds the reference voltage Vt, the flip-flop 10 is set (S) earlier than the timing at which the carrier signal generator 8 outputs the synchronization signal Vs. Then, a gate pulse as shown by hatching in FIG. 2 is added. As a result, control dead time is shortened and fluctuations in the output voltage are suppressed.

Circuit configuration diagram showing an embodiment of the present invention Waveform diagram of each part for explaining the operation of FIG. Circuit configuration diagram showing a conventional example Each part waveform diagram for explaining the operation of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 2 ... MOSFET (metal oxide field effect transistor), 3 ... DC power supply, 4 ... Inductor, 5 ... Smoothing capacitor, 6 ... Load, 7 ... Error amplifier, 8 ... Carrier signal generator, 9, 15 ... Comparator, DESCRIPTION OF SYMBOLS 10 ... Flip-flop, 11, 12 ... On-delay circuit, 13, 14 ... Gate driver, 17 ... OR circuit.

Claims (1)

An error amplifying means for amplifying an error between the DC output voltage and the first reference voltage, and a carrier signal generating means, are connected to a DC power source based on a comparison result between the carrier signal and the output of the error amplifying means. In order to obtain a constant DC output,
A switching power supply control method for forcibly turning on a switch element at a timing when an output of the error amplification means exceeds a second reference voltage.

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