JP2018130011A - Switching regulator and controller thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a current mode control switching regulator circumventing the impact of ringing noise.SOLUTION: A switching regulator 1 converts a current IH flowing to a high-side transistor TH1 and a current IL flowing to a low-side transistor TL1 into voltages by respective on-resistances, and then amplifies these voltages by high-side amplification means 6 and a low-side transistor amplification means 7, respectively. The amplified high-side amplification voltage VHα and low-side amplification voltage VLβ are summed up by summation means 8, and smoothed by a lowpass filter 10, thus setting and adjusting the DC level of a slop signal Vsl. A slope signal Vsl and an error signal Verr are compared by a PWM comparator 5, and a reset signal Soff having a controlled pulse duty ratio is outputted to the comparator 5.SELECTED DRAWING: Figure 1A

Description

  The present invention relates to a current mode control type switching regulator, and more particularly to a current mode control type switching regulator that can eliminate the influence of ringing noise generated when a high side transistor and a low side transistor are turned on / off.

  Conventionally, some current mode control type switching regulators perform current mode control by detecting a current flowing in at least one of a low side transistor and a high side transistor.

  Patent Document 1 proposes a current mode control type switching power supply. FIG. 1 of Patent Document 1 detects the current flowing through the low-side transistor, FIG. 14 detects the current flowing through the high-side transistor, and FIG. 11 detects the current flowing through both transistors. Each thing is disclosed.

  Patent Document 2 discloses a motor control device that can detect current while avoiding the influence of ringing noise. Such a motor control device uses a current detection means to connect a brushless motor in an ON section in which an arm switch having a larger duty ratio is turned on among an upper arm switch (high side transistor) and a lower arm switch (low side transistor). Current detection means for detecting or estimating the value of the current flowing through the circuit is provided.

  Referring to paragraph 0020 (Example 3) of Patent Document 2, an example in which the motor current is always detected on the on side of the upper arm switch and the on side of the lower arm switch, and the average of both detection values is used as the current detection value. Indicates. Further, referring to paragraph 0021, it is suggested that ringing noise usually occurs in an opposite phase when the upper arm switch is turned on and when the lower arm switch is turned on. According to Patent Document 2, current detection that avoids the influence of ringing noise can be performed without changing the switching operation.

Japanese Patent Laid-Open No. 2006-67113 JP 2011-135629 A

  Patent Document 1 discloses various current mode control type switching regulators. However, an object of the present invention is to provide a current mode control type switching power supply suitable for both cases where the ratio of the output voltage to the input voltage is small and large. It is not intended to avoid the ringing effects that occur in switching regulators.

  In Patent Document 2, ringing noise is generated at the time of switching of the high-side transistor and the low-side transistor, and further, in an on section where the arm switch on the side with a large duty ratio is turned on in order to avoid the influence of the ringing noise, This suggests that the current detection means detects the value of the current flowing through the upper arm switch (high side transistor) or the lower arm switch (low side transistor). However, since the duty ratio calculation circuit for calculating the duty ratio is an essential component, the circuit configuration becomes complicated. In addition, since the current detecting means specifically uses a shunt resistor and the shunt resistor is connected to the coil of the brushless motor, power consumption is generated at the shunt resistor. Further, since the shunt resistor must be prepared separately from the circuit portion of the inverter, there arises a problem that the circuit scale increases.

  The present invention has been made to overcome the above-described problems, and an object of the present invention is to provide a current mode control type switching regulator capable of avoiding the influence of ringing noise with a simple circuit configuration. .

One aspect of the current mode control type switching regulator according to the present invention comprises the following constituent elements.
(A) switching means including a high-side transistor and a low-side transistor that convert an input voltage into a predetermined output voltage and output the output voltage;
(B) an inductor that switches between storage and release of energy by the switching operation of the switching means;
(C) smoothing means for receiving energy released from the inductor and smoothing the output voltage;
(D) an output terminal for outputting the output voltage taken out from the smoothing means;
(E) an error signal voltage generation circuit that generates an error signal voltage corresponding to a difference between the output voltage or a feedback voltage corresponding thereto and a predetermined reference voltage;
(G) high-side voltage detection means and low-side voltage detection means for converting the currents flowing separately to the high-side transistor and the low-side transistor into voltages,
(H) a high-side detection voltage amplifying means and a low-side detection voltage amplifying means for separately amplifying the detection voltages output from the high-side voltage detection means and the low-side voltage detection means,
(I) Detection voltage summing means for summing the amplified output voltages output from the high side detection voltage amplifying means and the low side detection voltage amplifying means,
(J) a low-pass filter for smoothing the summed voltage output from the detection voltage summing means;
(K) a PWM comparator that compares the output voltage of the low-pass filter with a slope signal and generates a PWM [pulse width modulation] signal in which the pulse duty ratio is controlled; and
(L) A PWM control circuit that switches the high-side transistor and the low-side transistor with a PWM output signal of the PWM comparator.

  Furthermore, in another aspect of the current mode control type switching regulator according to the present invention, the high-side voltage detecting means is an on-resistance of the high-side transistor, and the low-side voltage detecting means is an on-resistance of the low-side transistor.

  Furthermore, in another aspect of the current mode control type switching regulator according to the present invention, the current flowing through the high-side transistor is IH, the on-resistance of the high-side transistor is RonH, and the voltage amplification degree of the high-side detection voltage amplification means is set. When I is α, the current flowing through the low-side transistor is IL, the on-resistance of the low-side transistor is RonL, and the voltage amplification factor of the low-side detection voltage amplification means is β, IH × RonH × α = IL × RonL × β Has been.

  Furthermore, in another aspect of the current mode control type switching regulator according to the present invention, the voltage amplified by the high side amplifying means and the low side amplifying means is converted into a current, and the high side amplifying means and the low side amplifying means Output separately from the output stage.

  Furthermore, in another aspect of the current mode control type switching regulator according to the present invention, the summing means is provided with a summing resistor coupled to an output stage of the high side amplifying means and the low side amplifying means.

  Furthermore, in another aspect of the current mode control type switching regulator according to the present invention, the sum signal is applied to the low-pass filter via a buffer.

  In spite of a relatively simple circuit configuration, the present invention adds the ringing noise generated when the high-side transistor and the low-side transistor are turned on / off, and further suppresses the added noise component with a low-pass filter. Since the switching regulator is controlled, it is possible to provide a current mode control type switching regulator that avoids the influence of ringing noise.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit configuration diagram (transistor built-in type) illustrating an electronic device including a step-down current mode control type switching regulator according to a first embodiment of the present invention. 1 is a circuit configuration diagram (transistor external type) showing an electronic device including a step-down current mode control type switching regulator according to a first embodiment of the present invention. FIG. 2 is a signal waveform diagram of main nodes in FIGS. 1A and 1B. 1A and 1B are schematic diagrams illustrating ringing noise included in main signals and voltages when the on-duty ratio of a high-side transistor is low. 1A and 1B are schematic diagrams showing ringing noise included in main signals and voltages when the on-duty ratio of a high-side transistor is high in FIGS. 1A and 1B. FIG. FIG. 3 is a signal waveform diagram of a node different from the node shown in FIG. 2 in FIGS. 1A and 1B. FIGS. 1A and 1B are signal waveform diagrams illustrating voltages and signals output from the summing unit 8, the low-pass filter 10 and the slope signal generation circuit 11 which are features of the present invention in FIGS. It is a circuit block diagram (built-in transistor type) which shows the electronic device provided with the step-up type current mode control type switching regulator according to the second embodiment of the present invention. It is a circuit block diagram (transistor external type) which shows the electronic device provided with the pressure | voltage rise type current mode control type switching regulator which is the 2nd Embodiment of this invention.

(First embodiment)
1A and 1B are circuit configuration diagrams of an electronic device including a step-down current mode control type switching regulator to which the present invention is applied. It should be noted that the constituent elements drawn within the one-dot chain line frame in each figure indicate that the constituent elements are integrated in the semiconductor integrated circuit device. An embodiment of the present invention will be described below with reference to the drawings. An output voltage of a DC power source such as a battery (not shown) becomes the input voltage Vin of the current mode control type switching regulator 1. The input terminal IN to which the input voltage Vin is applied is connected to the source of the high side transistor TH1 (= corresponding to an output switch). The drain of the high side transistor TH1 and the drains of the inductor L1 and the low side transistor TL (= corresponding to a synchronous rectification switch) are connected in common at the node N1. The source of the low side transistor TL1 is connected to the ground potential GND. The high side transistor TH1 and the low side transistor TL1 are turned on and off based on the high side gate signal GH and the low side gate signal GL output from the PWM control circuit 13, and are switching transistors that control the inductor current Isw flowing through the inductor L1. Function. In this document, regardless of the step-down type or step-up type, the high-side transistor is referred to as a high-side transistor, and the high-side transistor is referred to as a low-side transistor, which is arranged on the ground potential GND side.

  1A and 1B, the high-side transistor TH1 is a p-channel MOS (metal oxide semiconductor) field effect transistor (hereinafter referred to as a pMOS transistor), and the low-side transistor TL1 is an n-channel MOS field effect transistor (hereinafter referred to as a p-channel MOS field effect transistor). Hereinafter referred to as an nMOS transistor). Further, as the high-side transistor TH1 and the low-side transistor TL1, an IGBT [Insulated Gate Bipolar Transistor] or the like can be used. Further, the high side transistor TH1 and the low side transistor TL1 may be formed of bipolar transistors.

  One end of the inductor L1 is connected to the node N1. The other end of the inductor L1 is connected to the node N2. One end of the resistor R1, one end of the smoothing capacitor C1, and the output terminal OUT are connected to the node N2. The other end of the smoothing capacitor C1 is grounded. A load RL is connected to the output terminal OUT. The load RL is, for example, a CPU. The other end of the resistor R1 is commonly connected to one end of the resistor R2 at the node N3, and the other end of the resistor R2 is connected to the ground potential GND.

  The feedback voltage generation circuit 2 includes resistors R1 and R2 connected in series between the node N2 and the ground potential GND, and outputs the feedback voltage Vfb to the node N3 that is a common connection point.

  The error amplifier circuit 3 compares the feedback voltage Vfb input to the inverting input terminal with the reference voltage Vt1 input to the non-inverting input terminal, and outputs an error signal Verr of the difference.

  The phase compensation circuit 4 is prepared for preventing abnormal oscillation of the current mode control type switching regulator 1. The phase compensation circuit 4 includes a capacitor C2 and a resistor R3 connected in series between the output terminal of the error amplifier circuit 3 and the ground terminal.

  The PWM comparator 5 compares the error signal Verr applied to the inverting input terminal with the slope signal Vsl applied to the non-inverting input terminal, and generates the reset signal Soff. The PWM comparator 5 outputs the reset signal Soff at the timing when the error signal Verr exceeds the slope signal Vsl.

  The high side amplifying means 6 (= corresponding to the first amplifying unit) is composed of, for example, an operational amplifier, and the high side which is a difference between the input voltage Vin applied to the source of the high side transistor TH1 and the switching voltage Vsw generated at the drain. The detection voltage VH (= corresponding to the first detection signal) is amplified and the high-side detection amplification voltage VHα (= corresponding to the first amplification detection signal) is output. The magnitude of the voltage amplification degree of the high side amplifying means 6 is indicated by the symbol α. The non-inverting input terminal of the high side amplifying means 6 is connected to the source of the high side transistor TH1, that is, the input terminal IN, and the inverting input terminal of the high side amplifying means 6 is connected to the drain of the high side transistor TH1, that is, the node N1. . The high side detection voltage VH is directly proportional to the high side current IH flowing through the high side transistor TH1. This is because if the on-resistance of the high-side transistor TH1 is RonH, the high-side detection voltage VH is expressed as VH = RonH × IH. Accordingly, the on-resistance RonH of the high side transistor TH1 functions as a current-voltage conversion unit that converts the high side current IH into the high side detection voltage VH. That is, the on-resistance RonH of the high-side transistor TH1 is used as high-side voltage detection means (= corresponding to the first current detection unit) of the present invention. However, as the high side voltage detection means, for example, a resistance element having a low resistance value of, for example, several Ω to several tens of Ω can be separately used.

  The high-side detection amplification voltage VHα output from the high-side amplification means 6 is expressed by VH × α = Ron × IH × α, which is obtained by multiplying the high-side detection voltage VH by the voltage amplification degree α. The output of the high side amplifying means 6 is taken out as a detection output current i6. As will be described later, this is because the high-side detection amplification voltage VHα and the low-side detection amplification voltage VLβ are added together by the addition resistor R4.

  The low side amplifying unit 7 (= corresponding to the second amplifying unit) is composed of, for example, an operational amplifier similarly to the high side amplifying unit 6, and the voltage between the source and drain of the low side transistor TL1, that is, the ground potential GND and the node N1 A low-side detection voltage VL (= corresponding to the second detection signal) that is a difference from the switching voltage Vsw appearing at is amplified to output a low-side detection amplification voltage VLβ (= corresponding to the second amplification detection signal). The magnitude of the voltage amplification degree of the low side amplifying means 7 is indicated by the symbol β. The non-inverting input terminal of the low side amplifying means 7 is connected to the ground potential GND to which the source of the low side transistor TL1 is connected, and the inverting input terminal of the low side amplifying means 7 is connected to the drain of the low side transistor TL1, that is, the node N1. The low side detection voltage VL is directly proportional to the low side current IL flowing through the low side transistor TL1. This is because if the on-resistance of the low-side transistor TL1 is RonL, the low-side detection voltage VL is expressed as VL = RonL × IL. Therefore, the on-resistance RonL of the low-side transistor TL1 functions as current-voltage conversion means for converting the low-side current IL into the low-side detection voltage VL. That is, the on-resistance RonL of the low-side transistor TL1 is used as low-side voltage detection means (= corresponding to the second current detection unit) of the present invention.

  The low-side detection amplification voltage VLβ output from the low-side amplification means 7 is expressed by VL × β = RonL × IL × β, which is obtained by multiplying the low-side detection voltage VL by the voltage amplification degree β. The output of 7 is taken out as a detection output current i7. As will be described later, this is because the sum of the low-side detection amplification voltage VLβ and the high-side detection amplification voltage VHα is easily performed by the addition resistor R4.

  The low side detection amplification voltage VLβ output from the low side amplification unit 7 is VLBβ = VL × β = RonL × IL × β, and the high side detection amplification voltage VHα output from the high side amplification unit 6 is VHα = VH × As described above, α = RonH × IH × α. In an embodiment of the present invention, it is preferable to set VHα = VLβ, that is, RonH × IH × α = RonL × IL × β. Thereby, the current ripple of the inductor current Isw can be detected.

  The summing means 8 (= corresponding to the summing unit) includes a summing resistor R4, and generates a combined voltage Vsense (= corresponding to the summing detection signal) by converting the sum of the detection output current i6 and the detection output current i7 into a voltage. . The combined voltage Vsense generated by the summing unit 8 in this manner is a voltage obtained by adding the high side detection amplification voltage VHα and the low side detection amplification voltage VLβ. The detected output current i6 is output from the output stage of the high side amplifying means 6, and the detected output current i7 is output from the output stage of the low side amplifying means 7. It can be said that the detection output currents i6 and i7 are current output signals of the high-side amplification unit 6 and the low-side amplification unit 7, respectively. Since the detection output currents i6 and i7 are output from the output stage having a high output impedance, the current corresponding to the high-side detection voltage VH and the low-side detection voltage VL is faithfully supplied to the summing resistor R4. Thereby, the summing resistor R4 can add the high side detection voltage VH and the low side detection voltage VL without loss. In the combined resistor R4, when the detection output currents i6 and i7 are added together, the combined current is converted again into a voltage to generate a combined voltage Vsense.

  The buffer 9 is prepared for accurately transmitting the summed voltage Vsense output from the summing means 8 at the preceding stage to the low-pass filter 10 at the succeeding stage. The non-inverting input terminal of the buffer 9 is connected to the summing means 8 and the summed voltage Vsense is input. The inverting input terminal and the output terminal of the buffer 9 are connected in common and are connected to the low-pass filter 10 at the subsequent stage. The buffer 9 outputs a buffer output voltage Vbuf. The magnitude of the buffer output voltage Vbuf is equal to that of the combined voltage Vsense.

  The low-pass filter 10 (= corresponding to a smoothing unit) smoothes the buffer output voltage Vbuf. As a result, ringing noise included in the buffer output voltage Vbuf is smoothed. The low pass filter 10 outputs a low pass filter output voltage Vlpf (= corresponding to a smoothing detection signal). The low-pass filter 10 can be constituted by an integration circuit combining a well-known operational amplifier, capacitor, and resistor. If the integration effect of the integration circuit is insufficient, ringing noise remains and the anti-ringing noise characteristics deteriorate. On the other hand, if the CR time constant is set large, for example, in order to increase the integration effect of the integration circuit, the responsiveness of the current mode control type switching regulator decreases. Therefore, the time constant of the low-pass filter 10 is set in consideration of both.

  The slope signal generation circuit 11 is prepared for generating a slope signal Vsl such as a triangular wave voltage or a sawtooth wave voltage necessary for PWM control of the current mode control type switching regulator 1. The DC level of the slope signal Vsl is determined by the low-pass filter output voltage Vlpf from the low-pass filter 10.

  The oscillator 12 is configured by, for example, a well-known CR oscillator, or a circuit in which inverters or differential amplifiers are connected in a ring shape. The oscillator 12 generates a set signal Son at a predetermined oscillation frequency and supplies it to the PWM control circuit 13 at the subsequent stage. The set signal Son is also supplied to the slope signal generation circuit 11 via the node N5, and becomes a reference signal for generating the slope signal Vsl.

  The PWM control circuit 13 receives the set signal Son output from the oscillator 12 and the reset signal Soff output from the PWM comparator 5, outputs a high side gate signal GH and a low side gate signal GL, and outputs a high side transistor TH1 and a low side transistor. T1L is complementarily turned on / off. A sequential circuit (not shown) such as an RS flip-flop is prepared inside the PWM control circuit 13, a set signal Son generated by the oscillator 12 is set to the set terminal of the RS flip-flop, and a PWM comparator 5 is set to the reset terminal. The reset signal Soff output from is applied respectively.

  In the PWM control circuit 13, in order to prevent an excessive through current flowing from the high-side transistor TH1 to the low-side transistor TL1, an interval in which both the high-side gate signal GH and the low-side gate signal GL are at a low level, a so-called dead time is generated. Is provided. During the dead time period, the high-side transistor TH1 and the low-side transistor TL1 are both turned off to block the current path of the through current.

  Further, the PWM control circuit 13 has a function of forcibly stopping the switching operation of the switch output stage in accordance with an abnormality protection signal (not shown) (both signals output from the high side transistor TH1 and the low side transistor TL1 are set to a low level). Function).

  1A and 1B, the low side transistor TL1 operates in a complementary manner in synchronization with the high side transistor TH1 as a synchronous rectification transistor. The low side transistor TL1 is turned on when the high side transistor TH1 is off, and is turned off when the high side transistor TH1 is on. The low side transistor TL1 is turned on when the low side gate signal GL is at a high level, and is turned off when the low side gate signal GL is at a low level.

  By switching on / off the high side transistor TH1 and the low side transistor TL1 in a complementary manner, a rectangular wave switching voltage Vsw appears at the node N1. By smoothing the switching voltage Vsw with the inductor L1 and the smoothing capacitor C1, the output voltage Vout is taken out to the output terminal OUT.

  The current mode switching regulator 1 of this configuration example uses the high side transistor TH1, the low side transistor TL1, the inductor L1, and the smoothing capacitor C1 to step down the input voltage Vin supplied to the input terminal IN and to a desired level. A switch output stage for generating the output voltage Vout at the output terminal OUT is formed. The high side transistor TH1 and the low side transistor TL1 may be built in the semiconductor integrated circuit device as shown in FIG. 1A, or may be externally attached to the semiconductor integrated circuit device as shown in FIG. 1B.

  The error amplifier circuit 3, the PWM comparator 5, the slope signal generation circuit 11, the oscillator 12, and the PWM control circuit 13 complement the high-side transistor TH1 and the low-side transistor TL1 by current mode control according to the low-pass filter output voltage Vlpf. As a switch driving unit that is driven in an integrated manner, it is integrated in a semiconductor integrated circuit device.

  FIG. 2 shows signal waveforms of main nodes of the current mode control type switching regulator 1 shown in FIGS. 1A and 1B. The switching voltage Vsw is output to the node N1. The switching voltage Vsw is generated by the complementary operation of the high side transistor TH1 and the low side transistor TL1 as described above. In FIG. 2, for the sake of drawing, the high-level H section T1 is longer than the low-level section T2, and the duty ratio is about 65%. The actual duty ratio changes according to the weight and lightness of the load RL coupled to the output terminal OUT.

  In FIG. 2, a high side current IH is a current flowing through the high side transistor TH1. The high side current IH gradually increases in the high level H section of the switching voltage Vsw. The maximum value of the high side current IH is, for example, about 400 mA. The low side current IL is a current flowing through the low side transistor TL1. The low-side current IL plays a role of supplying current to the inductor L1 from the ground potential GND side in a section where the switching voltage Vsw is at the low level L, that is, in a section where the high-side transistor TH1 is off. The maximum value of the low side current IL is about 400 mA, which is the same as the high side current IH. The inductor current Isw is a current that flows through the inductor L1. The inductor current Isw is a combined current of the high side current IH and the low side current IL. The inductor current Isw has a triangular wave shape, and its amplitude value is indicated by a symbol ΔIsw. The amplitude value ΔIsw is, for example, about 100 mA. The summed voltage Vsense is taken from the node N4 that is the output of the summing means 8, that is, the summing resistor R4. The amplitude value ΔVsense of the combined voltage Vsense is, for example, about 1 mV, which is an extremely small value, but is shown enlarged on the drawing.

  3A and 3B schematically show a state in which ringing noise is included in the switching voltage Vsw, which is accompanying FIG. Ringing noise is generated in opposite phase when the high-side transistor TH1 and the low-side transistor TL1 each transition from the off state to the on state. 3A and 3B show a case where the duty ratio of the switching voltage Vsw output to the node N1 in FIGS. 1A and 1B is relatively low, for example, about 10%, and a case where the duty ratio is, for example, about 90%. The voltage and signal waveforms are schematically shown in two states in the high case.

  FIG. 3A shows a case where the duty ratio is low, and FIG. 3B shows a case where the duty ratio is high. In FIG. 3A, the switching voltage Vsw includes ringing noise nr whose amplitude width and amplitude value irregularly change with time. The high side detection voltage VH indicates the voltage between the drain and source of the high side transistor TH1. This figure shows a high level H section of the high side detection voltage VH and a state in which ringing noise nr appears immediately after the transition from the high level H to the low level L. The influence of the ringing noise nr increases as the period T of the switching voltage Vsw becomes shorter, that is, as the frequency becomes higher.

  The low side detection voltage VL indicates a voltage between the source and the drain of the low side transistor TL1. This figure shows a section of the low level L of the low side detection voltage VL and a state in which the ringing noise nr occurs immediately after the transition from the low level L to the high level H. The influence of the ringing noise nr increases as the period T of the switching voltage Vsw becomes shorter, that is, as the frequency becomes higher.

  3A and 3B, the combined detection voltage Vsense is output to the node N4. The combined detection voltage Vsense is a voltage obtained by adding the high side detection voltage VH and the low side detection voltage VL. In this figure, although the ringing noise nr is included a little in the combined detection voltage Vsense, it shows a state where it is attenuated more than that included in the high-side detection voltage VH and the low-side detection voltage VL. The low-pass filter output voltage Vlpf is output from the low-pass filter 10, but this figure shows a state in which the ringing noise nr is hardly included because it is smoothed. The low-pass filter output voltage Vlpf determines the DC level of the slope signal Vsl generated by the subsequent slope signal generation circuit 11. The slope signal Vsl set to a predetermined DC level is compared with the error signal Verr by the PWM comparator 5, and current mode control is executed.

  FIG. 4 shows voltages and signals different from the nodes of FIGS. 2 to 3A and 3B described above.

  The (a) stage in FIG. 4 shows the set signal Son output from the node N5, that is, the oscillator 12. The set signal Son serves as a set signal for the PWM logic circuit 13 and also serves as a reference signal for generating the slope signal Vsl.

  The (b) stage of FIG. 4 shows the reset signal Soff output from the PWM comparator 5. The reset signal Soff is a reset signal for the PWM logic circuit 7.

  The stage (c) in FIG. 4 shows the switching voltage Vsw output to the node N1, which is the same as the switching voltage Vsw shown in FIGS. 2, 3A, and 3B, but shows a slightly shaped waveform. Yes. The switching voltage SW transitions from the high level H to the low level L at the rising edge of the reset signal Soff.

  The stage (d) in FIG. 4 shows the buffer output voltage Vbuf output from the buffer 9 and the low-pass filter output voltage Vlpf output from the low-pass filter 12. The buffer output voltage Vbuf is the same as the combined detection voltage Vsense output to the node N4.

  4E shows the error signal Verr output from the error amplifier 4, the low-pass filter output voltage Vlpf output from the low-pass filter 10, and the slope signal Vsl output from the slope signal generation circuit 11. The direct current level of the slope signal Vsl is determined by the low-pass filter output voltage Vlpf. The relationship between the DC level of the slope signal Vsl and the low-pass filter output voltage Vlpf is also shown in FIG. The direct current level of the low-pass filter output voltage Vlpf is shifted based on the magnitudes of the high-side current IH flowing through the high-side transistor TH1 and the low-side current IL flowing through the low-side transistor TL1. Thereby, the direct current level of the slope signal Vsl is controlled, and the PWM comparator 5 shifts the comparison level with the error signal Verr, thereby realizing the current mode control type switching regulator 1. The low-pass filter output voltage Vlpf is smoothed with ringing noise by the low-pass filter 12 and is output as a substantially DC output voltage. Note that the reset signal Soff shown in the stage (b) of FIG. 4 rises at the timing when the error signal Verr and the slope signal Vsl intersect. Further, the switching voltage Vsw shown in the stage (c) of FIG. 4 becomes a high level H when the slope signal Vsl is lower than the error signal Verr, and becomes a low level L when the slope signal Vsl is higher than the error signal Verr. .

  FIG. 5 shows the combined voltage Vsense output from the summing unit 8 in FIGS. 1A and 1B, the low-pass filter output voltage Vlpf output from the low-pass filter 10, and the slope signal Vsl output from the slope signal generation circuit 11. It is a signal waveform diagram explaining each generation process. Since the generation of these voltages and signals is also related to other voltages, currents, and signals, some signals will be briefly described with reference to FIGS. 1A and 1B.

  The load current Io is a current flowing through the load RL. The load current Io is a relatively small load current Io1 from time t1 to t2, and the time t2, t3 and time t4 indicate a state of transition to a relatively large load current Io2. That is, a relatively large load current Io2 is supplied to the load RL at the time t2.

  The switching voltage Vsw is output from the node N1. The switching voltage Vsw supplies electromagnetic energy to the inductor L1.

  The switching current Isw flows through the inductor L1. The switching current Isw has a sawtooth wave shape or a triangular wave shape, and is linked to the load current Io to indicate a state in which the average level has increased from is1 to is2 with respect to time t2.

  The high-side detection voltage VH is a voltage generated between the source and the drain of the high-side transistor TH1, follows the switching current Isw, and the interval from time t1 to t2 is a relatively small voltage VH1, but from time t3 to t4 During this period, the voltage VH2 is relatively large.

  The low-side detection voltage VL is a voltage generated between the drain and the source of the low-side transistor TL1, follows the switching current Isw similarly to the high-side detection voltage VH, and a period from time t1 to t2 is a relatively small voltage VL1. However, the period from time t3 to t4 is a relatively large voltage VL2.

  The combined voltage Vsense is output from the summing unit 8. The synthesized voltage Vsense is a voltage obtained by synthesizing the high side detection voltage VH and the low side detection voltage VL. As a result, the switching current Isw follows and the voltage waveform is almost the same as the switching current Isw. Therefore, the average level vse1 rises to the average level vse2 at the times t2 and t3.

  The low-pass filter output voltage Vlpf is output from the low-pass filter 10. The low-pass filter output voltage Vlpf is a voltage obtained by filtering the high-frequency signal component from the combined voltage Vsense (more precisely, the buffer output voltage Vbuf) by the low-pass filter 10, but substantially follows the transition of the combined voltage Vsense. Then, it gradually rises from time t3. The low-pass filter output voltage Vsense is supplied to the subsequent slope signal generation circuit 11.

  The slope signal Vsl is generated by the slope signal generation circuit 11. The slope signal Vsl has a sawtooth waveform and a triangular waveform. The slope signal Vsl is generated by charging or discharging a capacitor (not shown) with a constant current, for example. The lower limit level of the slope signal Vsl is determined by the low-pass filter output voltage Vlpf. Therefore, the lower limit level of the slope signal Vsl follows the level of the low-pass filter output voltage Vlpf, and therefore gradually increases from time t3. The amplitude value vsl1 from the upper limit value to the lower limit value of the slope signal Vsl from the time t1 to the time t2 and the amplitude value vsl2 after the time t3 are set to be vsl1 = vsl2. The relationship between the DC level of the slope signal Vsl and the filter output voltage Vlpf is also shown in the stage (e) of FIG.

(Second Embodiment)
6A and 6B are circuit configuration diagrams showing an embodiment of an electronic device including a step-up current mode control type switching regulator to which the present invention is applied. It should be noted that the constituent elements drawn within the one-dot chain line frame in each figure indicate that the constituent elements are integrated in the semiconductor integrated circuit device. The step-up current mode control type switching regulator 1a boosts the input voltage Vin and takes out the output voltage Vout to the output terminal. 6A and 6B, one end of an inductor L2 is connected to an input terminal IN to which an input voltage Vin is supplied, and the other end of the inductor L2 is a low-side transistor TL2 (= corresponding to an output switch). ) Connected to the drain. The drain of the low side transistor TL2 and the source of the high side transistor TH2 (= corresponding to a synchronous rectification switch) are connected in common. These common connection points are indicated by node N1. The source of the low side transistor TL2 is connected to the ground potential GND. The high-side transistor TH2 and the low-side transistor TL2 are switched on and off based on the high-side gate signal GH and the low-side gate signal GL output from the PWM control circuit 13, respectively, and control the inductor current Isw that flows through the inductor L2. Function as.

  The high side transistor TH2 is a pMOS transistor, and the low side transistor TL2 is an nMOS transistor. An IGBT or the like can also be used as the high side transistor TH2 and the low side transistor TL2. Further, the high side transistor TH2 and the low side transistor TL2 may be composed of bipolar transistors.

  6A and 6B, the node N2 is commonly connected to the output terminal OUT. One end of the resistor R1 and one end of the smoothing capacitor C1 are connected to the node N2. The other end of the smoothing capacitor C1 is connected to the ground potential GND. A load RL is connected to the output terminal OUT. The load RL is, for example, a CPU. The other end of the resistor R1 is commonly connected to one end of the resistor R2 at the node N3, and the other end of the resistor R2 is connected to the ground potential GND.

  The feedback voltage generation circuit 2 includes resistors R1 and R2 connected in series between the node N2 and the ground potential GND, and outputs the feedback voltage Vfb to the node N3 that is a common connection point. The feedback voltage Vfb is connected to the inverting input terminal of the error amplifier circuit 3. A reference voltage Vt1 is connected to the non-inverting input terminal of the error amplifier circuit 3. The output terminal of the error amplification circuit 3 is connected to the phase compensation circuit 4.

  The high side amplifying means 6 is composed of, for example, an operational amplifier as in the case of FIGS. 1A and 1B, and detects the high side current IH2 flowing through the high side transistor TH2. The high side current IH2 is performed by detecting a voltage drop between the source and drain of the high side transistor TH2. Since such a detection method is the same as that of the step-down current mode control type switching regulator 1 of FIGS. 1A and 1B, the description thereof is omitted. The low side amplifying means 7 is composed of, for example, an operational amplifier, and detects a low side current IL2 flowing through the low side transistor TL2. The low side current IL2 is performed by detecting a voltage drop between the source and drain of the low side transistor TL2. Since such a detection method is also the same as that of the step-down current mode control type switching regulator 1 of FIGS. 1A and 1B, description thereof is omitted.

  In summary, the step-up current mode switching regulator 1a shown in FIGS. 6A and 6B is different from the step-down current mode switching regulator 1 shown in FIGS. 1A and 1B in that the input terminal IN and the high-side transistor are the same. The circuit connection among TH2, the low-side transistor TL2, and the inductor L2 is different, but the other circuit configuration and circuit connection are the same, and thus the description thereof is omitted. Note that the high-side transistor TH2 and the low-side transistor TL2 may be incorporated in the semiconductor integrated circuit device as shown in FIG. 6A, or may be externally attached to the semiconductor integrated circuit device as shown in FIG. 6B.

  As is clear from the above description, the current mode control type switching regulator of the present invention can eliminate the influence of ringing noise in spite of a simple circuit configuration, so that the industrial applicability is extremely high. high.

DESCRIPTION OF SYMBOLS 1,1a Current mode control type switching regulator 2 Feedback voltage generation circuit 3 Error amplification circuit 4 Phase compensation circuit 5 PWM comparator 6 High side amplification means (= corresponding to first amplification section)
7 Low-side amplification means (= corresponding to the second amplification section)
8 Summing means (= corresponding to summing part)
9 Buffer 10 Low-pass filter (= Equivalent to smoothing part)
DESCRIPTION OF SYMBOLS 11 Slope signal generation circuit 12 Oscillator 13 PWM control circuit C1 Smoothing capacitor C2 Capacitor GH High side gate signal GL Low side gate signal i6, i7 Detection output current IH High side current IL Low side current IN Input terminal Io Load current Isw Switching current L1, L2 Inductor N1 to N5 Node OUT Output terminal R1 to R3 Resistance R3 Total resistance RL Load Son Set signal Soff Reset signal TH1, TH2 High side transistor TL1, TL2 Low side transistor Vbuf Buffer output voltage Verr Error signal Vfb Feedback voltage VH High side detection voltage ( = Corresponds to the first detection signal)
VHα High side amplified voltage (= corresponding to the first amplified detection signal)
Vin input voltage VL Low side detection voltage (= corresponding to the second detection signal)
VLβ Low side amplified voltage (= corresponding to second amplified detection signal)
Vlpf Low-pass filter output voltage (= corresponding to smooth detection signal)
Vout output voltage Vsl slope signal Vsw switching voltage Vt1 reference voltage Vsense combined detection voltage (= corresponding to combined detection signal)

Claims (20)

A control device that is a control body of a switching regulator including an output switch and a synchronous rectification switch,
A summing unit that sums the first detection signal corresponding to the current flowing through the output switch and the second detection signal according to the current flowing through the synchronous rectification switch to generate a summed detection signal;
A smoothing unit that smoothes the sum detection signal to generate a smooth detection signal;
A switch driver that complementarily drives the output switch and the synchronous rectification switch by current mode control according to the smoothing detection signal;
A control device comprising: A first amplifier for amplifying the first detection signal to generate a first amplified detection signal;
A second amplifier for amplifying the second detection signal to generate a second amplified detection signal;
Further comprising
The control device according to claim 1, wherein the summation unit sums the first amplification detection signal and the second amplification detection signal to generate the summation detection signal.   The control apparatus according to claim 2, wherein each of the first amplification signal and the second amplification signal is a current signal.   The control device according to claim 3, wherein the summation unit includes a summing resistor that converts the summation current of the first amplification signal and the second amplification signal into a voltage to generate the summation detection signal.   The control device according to claim 1, further comprising a buffer that transmits the sum detection signal to the smoothing unit.   The control device according to claim 1, wherein the smoothing unit is a low-pass filter. The switch driver is
An oscillator that generates a set signal at a predetermined oscillation frequency;
An error amplification circuit that generates an error signal according to a difference between an output voltage of the switching regulator or a feedback voltage corresponding thereto and a predetermined reference voltage;
A slope signal generation circuit that generates a slope signal according to the smoothing detection signal;
A PWM (pulse width modulation) comparator that generates a reset signal by comparing the slope signal and the error signal;
A PWM control circuit for generating drive signals for the output switch and the synchronous rectifier switch in response to the set signal and the reset signal;
The control apparatus according to any one of claims 1 to 6, wherein the control apparatus includes:   The control apparatus according to claim 7, wherein a phase compensation circuit is connected to an output terminal of the error amplifier circuit. A switch output stage including the output switch that converts an input voltage into a predetermined output voltage and outputs the output voltage, and the synchronous rectification switch;
The control device according to any one of claims 1 to 8, which performs drive control of the switch output stage;
A switching regulator comprising: The switch output stage is
An inductor that switches between storing and releasing energy by switching operation of the output switch and the synchronous rectifier switch;
Smoothing means for receiving energy released from the inductor and smoothing the output voltage;
The switching regulator according to claim 9, further comprising:   The apparatus further comprises a first current detection unit and a second current detection unit for detecting the currents flowing through the output switch and the synchronous rectification switch separately to generate the first detection signal and the second detection signal. The switching regulator according to claim 9 or 10.   The switching regulator according to claim 11, wherein the first current detection unit is an on-resistance of the output switch, and the second current detection unit is an on-resistance of the synchronous rectification switch.   The current flowing through the output switch is IH, the on-resistance of the output switch is RonH, the amplification factor of the first amplification unit that amplifies the first detection signal is α, the current flowing through the synchronous rectification switch is IL, and the synchronous When the on-resistance of the rectifying switch is RonL and the voltage amplification degree of the second amplifying unit for amplifying the second detection signal is β, IH × RonH × α = IL × RonL × β is set. The switching regulator according to any one of claims 9 to 12.   The switching regulator according to any one of claims 9 to 13, wherein the output voltage is lower than the input voltage.   15. The switching regulator according to claim 14, wherein the output switch is a p-channel MOS [metal oxide semiconductor] field effect transistor, and the synchronous rectification switch is an n-channel MOS field effect transistor.   The switching regulator according to any one of claims 9 to 13, wherein the output voltage is higher than the input voltage.   The switching regulator according to claim 16, wherein the output switch is an n-channel MOS field effect transistor, and the synchronous rectification switch is a p-channel MOS field effect transistor.   The switching regulator according to any one of claims 9 to 17, wherein the output switch and the synchronous rectification switch are built in a semiconductor integrated circuit device in which the control device is integrated.   The switching regulator according to any one of claims 9 to 17, wherein the output switch and the synchronous rectification switch are externally attached to a semiconductor integrated circuit device in which the control device is integrated. . A switching regulator according to any one of claims 9 to 19,
A load that receives power supply from the switching regulator;
An electronic device comprising:

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