JP2009021374A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a trench gate type IGBT with an insulating gate trench formed as the aggregate of cells on a semiconductor substrate, which can prevent element damage even when a high DC voltage or dV/dt surge voltage is applied and which have high resistance to element damage. <P>SOLUTION: In the semiconductor device 100, the semiconductor substrate 1 includes a first semiconductor layer 1a of a first conductivity type on a main surface side, a second semiconductor layer 1b of a second conductivity type on a reverse-surface side, and a third semiconductor layer 1c of the first conductivity type disposed therebetween and having high impurity density. A first semiconductor region 2a of the second conductivity type is formed on surface layer portion of the first semiconductor layer 1a, and an insulating gate trench ZT is formed penetrating the first semiconductor region 2a. A charge supply means 1ch of supplying electric charges to nearby the tip of the insulating trench gate ZT when the IGBT 10 is off is disposed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which a trench gate type IGBT having an insulated gate trench is formed as an assembly of cells on a semiconductor substrate.

  An IGBT (Insulated Gate Bipolar Transistor) used in an inverter circuit for driving a load such as a motor is a so-called punch-through (PT) type IGBT, non-punch-through (NPT) type IGBT, and an intermediate between them. The field stop (FS) type IGBT disclosed in Japanese Patent Application Laid-Open No. 2004-103982 (Patent Document 1) can be roughly classified. The PT type IGBT has a structure in which a thick substrate of P conductivity type (P +) is used as a collector layer and an N conductivity type (N +) buffer layer is inserted between the N conductivity type (N−) drift layer. . The NPT type IGBT has a structure in which a P conductivity type (P +) collector layer is formed on the back surface of a thin N conductivity type (N−) substrate (body layer) functioning as a drift layer. The FS type IGBT has an N conductivity type (N) which is a drift layer by inserting an N conductivity type (N) buffer layer called a field stop (FS) layer between the drift layer and the collector layer of the NPT IGBT. The substrate (body layer) of −) is further thinned.

  The IGBT is roughly classified into a planar gate type IGBT and a trench gate type IGBT depending on the difference in gate structure. In the planar gate type IGBT, an oxide film formed on a semiconductor substrate is used as a gate insulating film, and a polycrystalline silicon film formed on the oxide film is used as a gate electrode. In a trench gate type IGBT, a sidewall oxide film of a trench formed in a surface layer portion of a semiconductor substrate is used as a gate insulating film, and polycrystalline silicon embedded in the trench is used as a gate electrode. Since the trench gate type IGBT can increase the integration density as compared with the planar gate type IGBT, it has a mainstream insulated gate structure in the IGBT in recent years.

  FIG. 7 is a diagram showing a schematic cross section of a semiconductor device 90 in which a trench gate type IGBT 10 having an insulated gate trench is formed using the FS type IGBT described above.

  A semiconductor device 90 shown in FIG. 7 is a semiconductor device in which a trench gate type IGBT 10 having an insulated gate trench ZT is formed on the semiconductor substrate 1 as a cell aggregate (IGBT cell region TR). The semiconductor substrate 1 includes an N conductivity type (N−) first semiconductor layer 1a on the main surface side, a P conductivity type (P) second semiconductor layer 1b on the back surface side, a first semiconductor layer 1a, and a second semiconductor. The third semiconductor layer 1c is disposed between the layers 1b and has an N conductivity type (N) and an impurity concentration higher than that of the first semiconductor layer 1a. The first semiconductor layer 1a, the second semiconductor layer 1b, and the third semiconductor layer 1c are a carrier drift layer, a collector layer, and a field stop (FS) layer of the IGBT 10, respectively. Incidentally, the reference numeral 4 formed on the main surface side of the semiconductor substrate 1 is a field oxide film, and the reference numeral 5 is a wiring layer made of aluminum or the like. Further, a portion denoted by reference numeral 6 formed on the back surface side of the semiconductor substrate 1 is an electrode layer made of aluminum or the like and serves as a collector electrode of the IGBT 10.

In the semiconductor device 90 of FIG. 7, the first semiconductor region 2a of P conductivity type (P) is formed in the surface layer portion of the first semiconductor layer 1a. The insulated gate trench ZT of the IGBT 10 is formed so as to penetrate the first semiconductor region 2a. Thus, the first semiconductor region 2a is divided into a channel formation region indicated by reference numeral 2ab and a floating region indicated by reference numeral 2af. In the channel forming region 2ab, an emitter region 3 of N conductivity type (N) is formed adjacent to the insulated gate trench ZT, and the emitter region 3 and the channel forming region 2ab are formed by the wiring layer 5. 5a is connected. On the other hand, the floating region 2af is a region in which the emitter electrode 5a is not connected and stores carriers in an electrically floating state. As described above, the IGBT 10 in the semiconductor device 90 of FIG. 7 is also a thinned channel IGBT in which the channel forming region 2ab connected to the emitter electrode 5a and the floating region 2af not connected to the emitter electrode 5a are configured. A thinned channel IGBT similar to that of the semiconductor device 90 is disclosed in, for example, Japanese Patent Laid-Open No. 2001-308327 (Patent Document 2). According to Patent Document 2, when the ratio of the width of the channel formation region to the floating region is 1: 2 to 1: 7, not only the on-voltage but also the switching loss is lowered, thereby reducing the total generation loss of the IGBT. can do.
JP 2004-103982 A JP 2001-308327 A

  The IGBT 10 shown in FIG. 7 can be a high breakdown voltage IGBT, and can have a breakdown voltage of about 600 to 1200 V and a current of about 30 to 300 A, for example. There are several modes for evaluating the withstand voltage of the IGBT. For example, the direct current (DC) withstand voltage, the withstand voltage when a sudden voltage change (dV / dt surge) is applied in an unenergized state, and the energized state (ON state) A so-called UIS (Unclamped Inductive Switching) RBSOA (Reverse Bias Safe Operating Area) test is representative.

  FIG. 8 schematically shows the collector-emitter voltage-collector current (Vce-Ic) characteristics of the operation mode 1 when measuring the DC withstand voltage and the operation mode 2 when measuring the dV / dt surge withstand voltage for the IGBT 10 of FIG. FIG.

  In the operation mode 1 of the DC withstand voltage test, when the collector-emitter voltage is increased, the avalanche breakdown starts at the point P1B of the voltage BVces, and the negative resistance indicated by the dotted line in the figure is generated at the point P1D. Device destruction occurs. The current up to the element destruction is in the range of μA to mA, and the element destruction occurs even with such a minute current. In the operation mode 2 of the dV / dt surge withstand voltage test, when the collector-emitter voltage is increased, the avalanche breakdown starts at the point P2B of the voltage Vce (sus2) lower than the voltage BVces of the mode 1, and the negative resistance At the point P2D where the phenomenon occurs, element destruction occurs. The current up to the element breakdown is in the range of mA to A, which is larger than that in the operation mode 1, but the element breakdown occurs with a smaller current than the rated current.

  In either case of the operation mode 1 or the operation mode 2, once the IGBT 10 is destroyed, it cannot be used again. Therefore, when a high DC voltage or a dV / dt surge voltage is applied to the IGBT 10, even if an avalanche breakdown starts, element breakdown does not occur and the high DC voltage or dV / dt surge voltage is released. It is desirable to return to the initial state at this point.

  Therefore, the present invention is a semiconductor device in which a trench gate type IGBT having an insulated gate trench is formed as an assembly of cells on a semiconductor substrate, where a high DC voltage or a dV / dt surge voltage is applied. It is an object of the present invention to provide a semiconductor device that can prevent element destruction and has high resistance to element destruction.

  The semiconductor device according to claim 1 is a semiconductor device in which a trench gate type IGBT having an insulated gate trench is formed on a semiconductor substrate as an assembly of cells, and the semiconductor substrate is formed on the main surface side. A first-conductivity-type first semiconductor layer; a second-conductivity-type second semiconductor layer on the back side; and a first-conductivity-type first semiconductor layer disposed between the first-semiconductor layer and the second-semiconductor layer. A third semiconductor layer having an impurity concentration higher than that of the first layer, wherein a first semiconductor region of a second conductivity type is formed in a surface layer portion of the first semiconductor layer, and penetrates the first semiconductor region, An insulated gate trench is formed, and charge supplying means for supplying charge is provided near the tip of the insulated gate trench when the trench gate type IGBT is turned off.

  The IGBT in the semiconductor device is a trench gate type IGBT, and a third semiconductor layer disposed between the first semiconductor layer which is a carrier drift layer and the second semiconductor layer which is a collector layer is a so-called field stop (FS). ) IGBT that functions as a layer.

  In general, the trench gate type IGBT can increase the integration density as compared with the planar gate type IGBT, but when a high DC voltage or a dV / dt surge voltage is applied, the trench gate type IGBT is near the tip of the insulated gate trench. Since the electric field strength becomes maximum, the device can be destroyed even with a small current when avalanche breakdown starts. However, in the trench gate type IGBT of the semiconductor device, charge supply means for supplying charge is provided near the tip of the insulated gate trench when the IGBT is off. Therefore, in the IGBT, it is possible to introduce a very small amount of carriers (charges) into the depletion layer immediately before the start of avalanche breakdown using the charge supply means. As a result, when avalanche breakdown starts, the impact ionization rate near the tip of the insulated gate trench decreases due to a very small amount of carriers (charges) introduced into the depletion layer, and local concentration of breakdown current is alleviated. , Surge breakdown resistance can be improved. Incidentally, since the introduction of carriers (charges) by the charge supply means may be extremely small, it is possible to hardly cause the DC breakdown voltage deterioration of the IGBT.

  As described above, the semiconductor device is a semiconductor device in which a trench gate type IGBT having an insulated gate trench is formed as a collection of cells on a semiconductor substrate, and a high DC voltage or a dV / dt surge voltage is applied. Even in such a case, element destruction can be prevented and a semiconductor device having high resistance against element destruction can be obtained.

  The charge supply means in the semiconductor device includes, for example, a third semiconductor layer formed so as to penetrate the third semiconductor layer and the first semiconductor layer reaches the second semiconductor layer. It can be a through hole.

  In this case, the DC voltage or dV / dt surge voltage applied to the collector electrode when the IGBT is off causes the first semiconductor from the second semiconductor layer, which is the collector layer on the back surface side, through the third semiconductor layer through hole. A very small amount of carriers (charges) can be supplied near the tip of the insulated gate trench protruding into the layer. Therefore, this can alleviate local concentration of breakdown current and improve surge breakdown resistance.

  According to a third aspect of the present invention, the third semiconductor layer through hole is disposed immediately below a flat bottom surface of the first semiconductor region where a depletion layer is formed flat with the first semiconductor layer. It is preferable that According to this, the supply of carriers (charges) to the depletion layer can be made uniform in the depth direction through the third semiconductor layer through hole.

  Furthermore, as described in claim 4, it is more preferable that the third semiconductor layer through hole is disposed immediately below the cell assembly. According to this, carriers (charges) can be supplied to the vicinity of the tip of the insulated gate trench through the third semiconductor layer through hole at the shortest distance.

  The third semiconductor layer through-hole can be configured to be an aggregate of stripe-shaped through-holes arranged at regular intervals within the substrate surface, for example, as described in claim 5. Moreover, you may comprise so that it may consist of a checkered through-hole as described in Claim 6. Furthermore, as described in claim 7, it may be constituted by an assembly of through holes arranged at lattice points. According to these, the supply of carriers (charges) to the depletion layer can be made uniform in the substrate plane through the third semiconductor layer through hole.

  The configuration and size of the third semiconductor layer through hole can be appropriately selected in consideration of the supply amount of carriers (charges) and the allowable range of DC withstand voltage.

  The charge supply means in the semiconductor device according to claim 8, wherein the first semiconductor region through hole is formed so as to penetrate the first semiconductor region and the first semiconductor layer reaches the main surface side surface. It may be.

  In this case, through the first semiconductor region through hole and the electrode connected to the first semiconductor layer exposed on the surface of the hole, a DC voltage or a dV / dt surge voltage applied to the electrode when the IGBT is turned off, It is possible to supply a very small amount of carriers (charges) near the tip of the insulated gate trench protruding from the main surface side of the semiconductor substrate to the first semiconductor layer. Therefore, this also can alleviate local concentration of breakdown current and improve surge breakdown tolerance.

  The thinned channel according to claim 9, wherein the trench gate type IGBT is a specific region in the first semiconductor region divided by the insulated gate trench, and a floating region not connected to the emitter electrode is provided. In the case of a type IGBT, the first semiconductor region through hole can be configured to be disposed in the floating region.

  In this case, the first semiconductor region through-holes are configured to be formed of a collection of stripe-shaped through-holes arranged at equal intervals as described in claim 10 in the substrate surface. Can do. Moreover, you may comprise so that it may consist of an aggregate | assembly of the through-hole arrange | positioned at a lattice point. According to these, the supply of carriers (charges) to the depletion layer can be made uniform in the substrate plane via the first semiconductor region through hole.

  In addition, as described in claim 12, the first semiconductor region through hole may be configured to be disposed under a field oxide film adjacent to the cell assembly.

  In this case, a DC voltage or a dV / dt surge voltage applied to the electrode when the IGBT is turned off via the electrode connected to the first semiconductor region through hole and the first semiconductor layer exposed on the surface of the hole. Thus, it is possible to supply a very small amount of carriers (charges) from the periphery of the IGBT cell on the main surface side to the vicinity of the tip of the insulated gate trench protruding into the first semiconductor layer.

  According to a thirteenth aspect of the present invention, the charge supply unit in the semiconductor device may be a light irradiation unit configured to irradiate light from the main surface side near the tip of the insulated gate trench.

  In this case, light is irradiated from the main surface side of the semiconductor substrate through a light irradiation means such as an LED (Light Emitting Diode) when the IGBT is turned off, in the vicinity of the tip of the insulated gate trench protruding to the first semiconductor layer. A small amount of carriers (charges) can be generated. Therefore, this also can alleviate local concentration of breakdown current and improve surge breakdown tolerance.

  As described above, the semiconductor device is a semiconductor device in which a trench gate type IGBT having an insulated gate trench is formed as a collection of cells on a semiconductor substrate, and a high DC voltage or a dV / dt surge voltage is applied. Even in such a case, element destruction can be prevented and a semiconductor device having high resistance against element destruction can be obtained.

  Therefore, the semiconductor device is particularly suitable as an in-vehicle semiconductor device to which a high voltage surge is easily applied as described in claim 14.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  First, the basic concept of the semiconductor device of the present invention will be described.

  FIG. 1 shows the collector-emitter voltage-collector current (Vce-Ic) for the operation mode 3 when measuring the RBSOA breakdown voltage of the IGBT 10 of FIG. It is the figure typically shown on the characteristic. In FIG. 1, the operation mode 1 at the time of DC withstand voltage measurement and the operation mode 2 at the time of dV / dt surge withstand voltage measurement shown in FIG.

  In operation mode 3 of the RBSOA breakdown voltage test, when the collector-emitter voltage is increased in the ON state of the trench gate type IGBT, the avalanche breakdown starts at the point P3B of the voltage BVce (sus3), and the collector current decreases. . However, in operation mode 3, which is a withstand voltage test during energization, even if an avalanche breakdown occurs, element breakdown does not occur, and if the IGBT energization is turned off at point P3C, the initial state is traced through a minute current path. Return to zero.

  Analyzing the cause of element breakdown in operation modes 1 and 2 in the withstand voltage test when the IGBT is not energized (off state), in the operation mode 3 in the withstand voltage test when the IGBT is energized (on state) It is considered as follows.

  In operation modes 1 and 2, the carrier density is very low in the depletion layer of the IGBT immediately before the start of avalanche breakdown. In addition, in the trench gate type IGBT, the electric field strength is extremely high near the tip of the insulated gate trench, and when the avalanche breakdown starts, the impact ionization rate becomes very high under the insulated gate trench. For this reason, for example, even if there is a slight manufacturing variation, local concentration of breakdown current occurs. In a cell in which breakdown current due to carriers generated by an avalanche is concentrated, parasitic transistors operate to induce latch-up, and eventually lead to element destruction. On the other hand, in the operation mode 3, the IGBT immediately before the start of the avalanche breakdown is in a very high carrier density state. Even if avalanche breakdown starts in such a state, local concentration of breakdown current does not occur, and therefore element breakdown does not occur.

  Considering the above two operation modes in the withstand voltage test, if a small number of carriers (charges) are introduced into the depletion layer in the off state of the IGBT, the introduced carriers (charges) can be generated by a high DC voltage or surge. It is considered that when a voltage is applied, an effect of suppressing element destruction is brought about.

  Based on the above concept, an ideal operation mode is illustrated as an operation path indicated by a thick dotted line in FIG. This ideal operation mode achieves both the advantages of the operation mode 1 in the non-energized state (off state) and the operation mode 3 in the energized state (on state). You can follow the route. Therefore, the carrier (charge) density in the depletion layer immediately before the start of avalanche breakdown is increased by some charge supply means. As a result, in the ideal operation mode, when the collector-emitter voltage is increased, initial breakdown can be avoided even if avalanche breakdown starts near the voltage Vcex, and the path close to operation mode 3 is reversed. It can be normally turned off without breaking even at a rated current (for example, 300 A).

  Next, a specific structure of the semiconductor device of the present invention will be described.

  FIG. 2 is a schematic cross-sectional view of the semiconductor device 100 as an example of the semiconductor device of the present invention. In the semiconductor device 100 of FIG. 2, the same parts as those of the semiconductor device 90 shown in FIG.

  A semiconductor device 100 shown in FIG. 2 basically has the same structure as the semiconductor device 90 shown in FIG. That is, the semiconductor device 100 of FIG. 2 is a semiconductor device in which a trench gate type IGBT 20 having an insulated gate trench ZT is formed on the semiconductor substrate 1 as a cell aggregate (IGBT cell region TR). The semiconductor substrate 1 includes an N conductivity type (N−) first semiconductor layer 1a on the main surface side, a P conductivity type (P) second semiconductor layer 1b on the back surface side, a first semiconductor layer 1a, and a second semiconductor. The third semiconductor layer 1c is disposed between the layers 1b and has an N conductivity type (N) and an impurity concentration higher than that of the first semiconductor layer 1a. The first semiconductor layer 1a, the second semiconductor layer 1b, and the third semiconductor layer 1c are a carrier drift layer, a collector layer, and a field stop (FS) layer of the IGBT 10, respectively. As described above, the IGBT 20 in the semiconductor device 100 is a trench gate type IGBT, and the third semiconductor layer disposed between the first semiconductor layer 1a as the carrier drift layer and the second semiconductor layer 1b as the collector layer. 1c is also an FS type IGBT that functions as a so-called field stop (FS) layer. Incidentally, the reference numeral 4 formed on the main surface side of the semiconductor substrate 1 is a field oxide film, and the reference numeral 5 is a wiring layer made of aluminum or the like. Further, a portion denoted by reference numeral 6 formed on the back surface side of the semiconductor substrate 1 is an electrode layer made of aluminum or the like and serves as a collector electrode of the IGBT 10.

  Similarly to the semiconductor device 90 shown in FIG. 7, in the semiconductor device 100 of FIG. 2, the first semiconductor region 2a of P conductivity type (P) is formed in the surface layer portion of the first semiconductor layer 1a. The insulated gate trench ZT of the IGBT 20 is formed so as to penetrate the first semiconductor region 2a. Thus, the first semiconductor region 2a is divided into a channel formation region indicated by reference numeral 2ab and a floating region indicated by reference numeral 2af. In the channel formation region 2ab, an N-type (N) emitter region 3 is formed adjacent to the insulated gate trench ZT, and the emitter region 3 and the channel formation region 2ab are formed by the wiring layer 5. 5a is connected. On the other hand, the floating region 2af is a region in which the emitter electrode 5a is not connected and stores carriers in an electrically floating state. Therefore, the IGBT 20 in the semiconductor device 100 of FIG. 2 is also a thinned channel IGBT in which a channel formation region 2ab connected to the emitter electrode 5a and a floating region 2af not connected to the emitter electrode 5a are configured.

On the other hand, unlike the semiconductor device 90 shown in FIG. 7, the semiconductor device 100 of FIG. 2 penetrates the third semiconductor layer 1c so that the first semiconductor layer 1a reaches the second semiconductor layer 1b. A layer through hole 1ch is formed. Due to the formation of the third semiconductor layer through hole 1ch, in the semiconductor device 100 of FIG. 2, the third semiconductor layer through hole 1ch is generated by the DC voltage or the dV / dt surge voltage applied to the collector electrode 6 when the IGBT 20 is turned off. It is possible to supply a very small amount of carriers (holes) to the vicinity of the tip of the insulated gate trench ZT protruding from the second semiconductor layer 1b which is the collector layer on the back surface side to the first semiconductor layer 1a. Therefore,
The third semiconductor layer through hole 1ch functions as a charge supply means for supplying charges to the vicinity of the tip of the insulated gate trench ZT when the trench gate type IGBT 20 is off.

  As described above, the trench gate type IGBT can generally increase the integration density as compared with the planar gate type IGBT. However, when a high DC voltage or a dV / dt surge voltage is applied, the trench gate type IGBT is insulated. Since the electric field strength becomes maximum near the tip of the semiconductor device, even if a slight current is applied, the device is destroyed when the avalanche breakdown starts. However, in the trench gate type IGBT 20 of the semiconductor device 100 shown in FIG. 2, the charge supply means (third semiconductor layer through-hole 1ch) for supplying charges to the vicinity of the tip of the insulated gate trench ZT when the IGBT 20 is off is disposed. Has been. Therefore, in the IGBT 20, it is possible to introduce a very small amount of carriers (holes) into the depletion layer by using the above-described charge supply means, which is filled in FIG. 2 just before the avalanche breakdown starts. The carrier introduction region CR shown is formed. As a result, the ideal operation mode indicated by the thick dotted line in FIG. 1 described above can be realized in the semiconductor device 100, and when the avalanche breakdown starts, the impact ionization rate in the vicinity of the tip of the insulated gate trench ZT decreases. , Local concentration of breakdown current can be relaxed, and surge breakdown resistance can be improved. Incidentally, since the introduction of carriers (charges) by the charge supply means may be extremely small, it is possible to hardly cause the DC breakdown voltage degradation of the IGBT 20.

  3 shows the semiconductor device 90 (sample 1) of FIG. 7 in which no through hole is formed in the third semiconductor layer 1c and the semiconductor device 100 (sample 2) of FIG. 2 in which the third semiconductor layer through hole 1ch is formed. It is the result of evaluating the collector-emitter voltage-collector current (Vce-Ic) characteristic by DC withstand voltage measurement.

  As shown in FIG. 3, in the semiconductor device 90 (sample 1) of FIG. 7 in which the through hole is not formed in the third semiconductor layer 1c, the avalanche breakdown occurs when the collector-emitter voltage Vce reaches about 1300V. Immediately after the occurrence, device breakdown occurred when the collector current Ic became 0.2 mA. On the other hand, in the semiconductor device 100 (sample 2) of FIG. 2 in which the third semiconductor layer through-hole 1ch is formed in the third semiconductor layer 1c, when the collector-emitter voltage Vce reaches about 1000 V, the second semiconductor layer 1b The supply of holes became prominent, and the collector current Ic gradually increased. Even when the collector current Ic reached 10 mA, the device was not destroyed.

  As shown in FIG. 2, the third semiconductor layer through hole 1ch in the semiconductor device 100 is directly below the flat bottom surface 2as of the first semiconductor region 2a where the depletion layer is formed flat with the first semiconductor layer 1a. It is preferable to be provided. According to this, the supply of carriers (charges) to the depletion layer can be made uniform in the depth direction via the third semiconductor layer through hole 1ch.

  Furthermore, as shown in FIG. 2, the third semiconductor layer through hole 1ch is more preferably disposed immediately below the cell aggregate (IGBT cell region TR). According to this, carriers (charges) can be supplied to the vicinity of the tip of the insulated gate trench through the third semiconductor layer through hole 1ch at the shortest distance.

  4A to 4C are schematic plan views each showing a preferred configuration example in the substrate plane for the third semiconductor layer through-hole 1ch in the semiconductor device 100 of FIG. In the drawing, a region 2as surrounded by an alternate long and short dash line indicates a range of the flat bottom surface 2as in the first semiconductor region 2a of FIG.

  The third semiconductor layer through-hole 1cha shown in FIG. 4A is configured to be an assembly of stripe-shaped through-holes arranged at equal intervals in the substrate surface. The third semiconductor layer through-hole 1chb shown in FIG. 4B is configured to have a checkered through-hole. Further, the third semiconductor layer through-hole 1chc shown in FIG. 4C is configured to be an assembly of through-holes arranged at lattice points. 4A to 4C, carriers (charges) are uniformly supplied to the depletion layer in the substrate plane via the third semiconductor layer through-holes 1cha to 1chc, respectively. Can do. The configuration and size of the third semiconductor layer through holes 1cha to 1chc can be appropriately selected in consideration of the supply amount of carriers (charges) and the allowable range of DC withstand voltage.

  As described above, the semiconductor device 100 shown in FIG. 2 is a semiconductor device in which the trench gate type IGBT 20 having the insulated gate trench ZT is formed on the semiconductor substrate 1 as an assembly of cells, and has a high DC voltage or dV. Even when a / dt surge voltage is applied, element destruction can be prevented and a semiconductor device having high resistance against element destruction can be obtained.

  FIGS. 5A and 5B are examples of another semiconductor device according to the present invention and are schematic cross-sectional views of the semiconductor devices 101 and 102, respectively. Note that, in the semiconductor devices 101 and 102 of FIGS. 5A and 5B, the same parts as those of the semiconductor device 100 shown in FIG.

  In the semiconductor device 100 shown in FIG. 2, as a charge supply means for supplying charges to a depletion layer with a tip of the insulated gate trench ZT when the trench gate type IGBT 20 is turned off, the third semiconductor layer 1c is penetrated and the first semiconductor The third semiconductor layer through hole 1ch is formed so that the layer 1a reaches the second semiconductor layer 1b. On the other hand, in the semiconductor devices 101 and 102 shown in FIGS. 5A and 5B, the charge supply means penetrates the first semiconductor region 2a, and the first semiconductor layer 1a is the semiconductor substrate 1. First semiconductor region through holes 2aha and 2ahb are formed so as to reach the main surface side surface of the first semiconductor region. The first semiconductor region through hole 2 aha in the semiconductor device 101 of FIG. 5A is disposed in the floating region 2 af in the trench gate type IGBT (thinned channel type IGBT) 21. The first semiconductor region through hole 2ahb in the semiconductor device 102 of FIG. 5B is disposed under the field oxide film 4 adjacent to the cell aggregate (IGBT cell region TR) of the trench gate type IGBT 22.

  In both of the semiconductor devices 101 and 102 of FIGS. 5A and 5B, the first semiconductor region through holes 2aha and 2ahb and the electrodes 5b connected to the first semiconductor layer 1a exposed at the surface of the holes, respectively. The insulated gate trench ZT protruding from the main surface side of the semiconductor substrate 1 to the first semiconductor layer 1a due to the DC voltage or dV / dt surge voltage applied to the electrodes 5b and 5c when the IGBTs 21 and 22 are turned off via the 5c It is possible to supply a very small amount of carriers (charges) in the vicinity of the tip of the substrate. Therefore, also in the semiconductor devices 101 and 102 of FIGS. 5A and 5B, the local concentration of the breakdown current can be alleviated and the surge breakdown resistance can be improved.

  Note that the first semiconductor region through-hole 2aha in the semiconductor device 101 of FIG. 5A is the same as the case of the third semiconductor layer through-holes 1cha and 1chc shown in FIG. 4A or 4C. In the substrate surface, it is preferable to be configured to include a collection of stripe-shaped through holes arranged at equal intervals or a collection of through holes arranged at lattice points. According to these, the supply of carriers (charges) to the depletion layer can be made uniform in the substrate plane via the first semiconductor region through hole 2aha. On the other hand, in the semiconductor device 102 of FIG. 5B, an IGBT cell (IGBT cell region) is connected via the first semiconductor region through hole 2ahb and the electrode 5c connected to the first semiconductor layer 1a exposed at the surface of the hole. It is possible to supply a very small amount of carriers (charges) from around TR.

  FIG. 6 is also a diagram illustrating a schematic cross section of the semiconductor device 103 as another example of the semiconductor device according to the present invention. In the semiconductor device 103 of FIG. 6 as well, the same parts as those of the semiconductor device 100 shown in FIG.

  In the semiconductor device 103 shown in FIG. 6, the charge supply means irradiates light such as an LED (Light Emitting Diode) that irradiates light from the main surface side of the semiconductor substrate 1 near the tip of the insulated gate trench ZT. Means (not shown). In the semiconductor device 103, when the IGBT 23 is turned off via the light irradiation means, light is irradiated from the main surface side of the semiconductor substrate 1, and a very small amount is near the tip of the insulated gate trench ZT protruding into the first semiconductor layer 1a. It is possible to generate carriers (charges). Therefore, also in the semiconductor device 103 shown in FIG. 6, it is possible to alleviate local concentration of breakdown current and improve surge breakdown resistance.

  As described above, each of the semiconductor devices 100 to 103 described above is a semiconductor device in which a trench gate type IGBT having an insulated gate trench is formed as an assembly of cells on a semiconductor substrate, and a high DC voltage or Even when a dV / dt surge voltage is applied, element breakdown can be prevented and a semiconductor device having high resistance to element breakdown can be obtained.

  Therefore, the semiconductor device is particularly suitable as a vehicle-mounted semiconductor device to which a high voltage surge is easily applied.

7 schematically shows the collector-emitter voltage-collector current (Vce-Ic) characteristics of the operation mode 3 when measuring the RBSOA withstand voltage of the IGBT 10 of FIG. 7 and the operation mode when applying an ideal surge according to the present invention. It is. 1 is a schematic cross-sectional view of a semiconductor device 100 as an example of the semiconductor device of the present invention. 7 shows the result of evaluating the collector-emitter voltage-collector current (Vce-Ic) characteristics by DC withstand voltage measurement for the semiconductor device 90 (sample 1) in FIG. 7 and the semiconductor device 100 (sample 2) in FIG. (A)-(c) is the typical top view which showed the suitable structural example in the board | substrate surface about the 3rd semiconductor layer through-hole 1ch in the semiconductor device 100 of FIG. 2, respectively. (A), (b) is the example of another semiconductor device in this invention, and is the figure which showed the typical cross section of the semiconductor devices 101 and 102, respectively. FIG. 6 is a diagram showing a schematic cross section of a semiconductor device 103 as an example of another semiconductor device according to the present invention. It is the figure which showed the typical cross section of the semiconductor device 90 in which the trench gate type IGBT which has an insulated gate trench was formed by FS type IGBT. 7 is a diagram schematically showing the collector-emitter voltage-collector current (Vce-Ic) characteristics of the operation mode 1 when measuring the DC withstand voltage and the operation mode 2 when measuring the dV / dt surge withstand voltage for the IGBT 10 of FIG. is there.

Explanation of symbols

90, 100 to 103 Semiconductor device 10, 20 to 23 (Trench gate type IGBT) IGBT
ZT Insulated gate trench CR carrier introduction region TR IGBT cell region 1 Semiconductor substrate 1a First semiconductor layer (carrier drift layer)
1b Second semiconductor layer (collector layer)
1c Third semiconductor layer (FS layer)
1ch, 1cha-1chc Third semiconductor layer through hole (charge supply means)
2a First semiconductor region 2ab Channel formation region 2af Floating region 2aha, 2ahb First semiconductor region through hole (charge supply means)
3 emitter region 4 field oxide film 5 wiring layer 5a emitter electrode 5b, 5c electrode 6 (collector) electrode layer

Claims (14)

A trench gate type IGBT having an insulated gate trench is a semiconductor device formed on a semiconductor substrate as an assembly of cells,
The semiconductor substrate is
The first conductivity type first semiconductor layer on the main surface side, the second conductivity type second semiconductor layer on the back surface side, and the first conductivity type disposed between the first semiconductor layer and the second semiconductor layer. And a third semiconductor layer having an impurity concentration higher than that of the first semiconductor layer.
A first semiconductor region of a second conductivity type is formed on a surface layer portion of the first semiconductor layer;
The insulated gate trench is formed so as to penetrate the first semiconductor region,
A semiconductor device comprising charge supply means for supplying charge near the tip of the insulated gate trench when the trench gate type IGBT is off. The charge supply means;
2. The semiconductor device according to claim 1, wherein the semiconductor device is a third semiconductor layer through-hole formed so as to penetrate the third semiconductor layer and the first semiconductor layer reaches the second semiconductor layer. The third semiconductor layer through-hole is
The semiconductor device according to claim 2, wherein the semiconductor device is disposed immediately below a flat bottom surface of the first semiconductor region. The third semiconductor layer through-hole is
4. The semiconductor device according to claim 3, wherein the semiconductor device is disposed immediately below the cell assembly. The third semiconductor layer through-hole is
5. The semiconductor device according to claim 2, comprising a collection of stripe-shaped through-holes arranged at equal intervals in a substrate plane. The third semiconductor layer through-hole is
5. The semiconductor device according to claim 2, wherein the semiconductor device includes a checkered through-hole in a substrate surface. The third semiconductor layer through-hole is
5. The semiconductor device according to claim 2, wherein the semiconductor device includes an assembly of through holes arranged at lattice points in a substrate plane. The charge supply means;
2. The semiconductor device according to claim 1, wherein the semiconductor device is a first semiconductor region through-hole formed so as to penetrate the first semiconductor region and the first semiconductor layer reaches a main surface side surface. The trench gate type IGBT is
A thinned channel IGBT in which a floating region that is not connected to an emitter electrode is provided in a specific region in the first semiconductor region divided by the insulated gate trench,
The first semiconductor region through-hole is
The semiconductor device according to claim 8, wherein the semiconductor device is disposed in the floating region. The first semiconductor region through-hole is
10. The semiconductor device according to claim 9, comprising a collection of stripe-shaped through holes arranged at equal intervals in a substrate plane. The first semiconductor region through-hole is
The semiconductor device according to claim 9, wherein the semiconductor device is formed of an assembly of through holes arranged at lattice points in a substrate plane. The first semiconductor region through-hole is
12. The semiconductor device according to claim 8, wherein the semiconductor device is disposed under a field oxide film adjacent to the cell assembly. The charge supply means;
The semiconductor device according to claim 1, wherein the semiconductor device is a light irradiation unit configured to irradiate light from a main surface side near a tip of the insulated gate trench.   The semiconductor device according to claim 1, wherein the semiconductor device is an in-vehicle semiconductor device.

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