JP2009021004A - Thin-film magnetic substance storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform a data reading operation only by accessing a selection memory cell. <P>SOLUTION: During data reading, a bias magnetic field of a level that will not destroy stored data is applied to a selection memory cell. With the application of the bias magnetic field, a data-line voltage difference between before and after the change of electric resistance of the selection memory cell by polarity according to a stored data level is amplified by a sense amplifier, and thus data reading is performed by only accessing the selection memory cell. Additionally, an activated write digit line WDL is driven by a power supply voltage Vcc1, which is higher than a power supply voltage Vcc2 of other peripheral circuits that include a data reading circuit system. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a thin film magnetic memory device, and more particularly to a random access memory including a memory cell having a magnetic tunnel junction (MTJ).

  An MRAM (Magnetic Random Access Memory) device has attracted attention as a storage device that can store nonvolatile data with low power consumption. An MRAM device is a storage device that performs non-volatile data storage using a plurality of thin film magnetic bodies formed in a semiconductor integrated circuit and allows random access to each of the thin film magnetic bodies.

  In particular, in recent years, it has been announced that the performance of MRAM devices will be dramatically improved by using a thin film magnetic body using a magnetic tunnel junction as a memory cell. For MRAM devices with memory cells with magnetic tunnel junctions, see “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, Feb 2000. and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, Feb. 2000.

  FIG. 11 is a schematic diagram showing a configuration of a memory cell having a tunnel junction (hereinafter also simply referred to as “MTJ memory cell”).

  Referring to FIG. 11, the MTJ memory cell includes a tunnel magnetoresistive element TMR whose electric resistance changes according to the data level of magnetically written storage data, and an access transistor ATR. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR between write bit line WBL and read bit line RBL. Typically, a field effect transistor formed on a semiconductor substrate is applied as access transistor ATR.

  For MTJ memory cells, write bit line WBL and write digit line WDL for flowing data write currents in different directions during data write, word line WL for instructing data read, and data read A read bit line RBL that receives supply of current is provided. At the time of data reading, in response to turn-on of access transistor ATR, tunneling magneto-resistance element TMR is electrically coupled between write bit line WBL set to ground voltage GND and read bit line RBL. .

FIG. 12 is a conceptual diagram illustrating a data write operation for the MTJ memory cell.
Referring to FIG. 12, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter simply referred to as “fixed magnetization layer”) FL having a fixed fixed magnetization direction and an externally applied magnetic field. A ferromagnetic layer (hereinafter, also simply referred to as “free magnetic layer”) VL that is magnetized in the direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite (antiparallel) direction to fixed magnetic layer FL according to the level of stored data to be written. A magnetic tunnel junction is formed by these fixed magnetic layer FL, tunnel barrier TB and free magnetic layer VL.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, the electrical resistance of the tunnel magnetoresistive element TMR becomes the minimum value Rmin when the magnetization direction of the fixed magnetization layer FL and the magnetization direction of the free magnetization layer VL are parallel, and the magnetization directions of both are opposite (reverse) In the case of the (parallel) direction, the maximum value Rmax is obtained.

  At the time of data writing, word line WL is deactivated and access transistor ATR is turned off. In this state, the data write current for magnetizing free magnetic layer VL flows in the direction corresponding to the level of the write data in each of write bit line WBL and write digit line WDL.

  FIG. 13 is a conceptual diagram showing the relationship between the data write current and the magnetization direction of the tunnel magnetoresistive element in data write.

  Referring to FIG. 13, the horizontal axis H (EA) indicates a magnetic field applied in the easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. On the other hand, the vertical axis H (HA) indicates a magnetic field that acts in the hard magnetization axis (HA) direction in the free magnetic layer VL. Magnetic fields H (EA) and H (HA) correspond to one of the two magnetic fields generated by the currents flowing through write bit line WBL and write digit line WDL, respectively.

  In the MTJ memory cell, the fixed magnetization direction of the fixed magnetization layer FL is along the easy magnetization axis of the free magnetization layer VL, and the free magnetization layer VL has the stored data level (“1” and “0”). Accordingly, it is magnetized in the direction parallel to the fixed magnetic layer FL or in the antiparallel (opposite) direction along the easy axis direction. The MTJ memory cell can store 1-bit data (“1” and “0”) corresponding to the two magnetization directions of the free magnetic layer VL.

  The magnetization direction of the free magnetic layer VL can be newly rewritten only when the sum of the applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in the figure. it can. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  As indicated by the asteroid characteristic line, by applying a magnetic field in the hard axis direction to the free magnetic layer VL, the magnetization threshold required to change the magnetization direction along the easy axis is lowered. be able to.

When the operating point at the time of data writing is designed as in the example shown in FIG. 13, in the MTJ memory cell that is the data writing target, the strength of the data writing magnetic field in the easy axis direction is HWR. Designed to be That is, the value of the data write current flowing through write bit line WBL or write digit line WDL is designed so that this data write magnetic field HWR is obtained. Generally, data write magnetic field H _WR is the switching magnetic field H _SW necessary for switching the magnetization direction is indicated by the sum of the margin [Delta] H. That is, H _WR = H _SW + ΔH.

  In order to rewrite the storage data of the MTJ memory cell, that is, the magnetization direction of the tunnel magnetoresistive element TMR, it is necessary to pass a data write current of a predetermined level or more to both the write digit line WDL and the write bit line WBL. Thus, free magnetic layer VL in tunneling magneto-resistance element TMR is parallel to fixed magnetic layer FL or in the opposite (anti-parallel) direction according to the direction of the data write magnetic field along the easy axis (EA). Magnetized. The magnetization direction once written in tunneling magneto-resistance element TMR, that is, data stored in the MTJ memory cell is held in a nonvolatile manner until new data writing is executed.

FIG. 14 is a conceptual diagram illustrating data reading from the MTJ memory cell.
Referring to FIG. 14, at the time of data reading, access transistor ATR is turned on in response to activation of word line WL. Write bit line WBL is set to ground voltage GND. Thereby, tunneling magneto-resistance element TMR is electrically coupled to read bit line RBL while being pulled down by ground voltage GND.

  In this state, if the read bit line RBL is pulled up with a predetermined voltage, the current path including the read bit line RBL and the tunnel magnetoresistive element TMR is changed according to the electric resistance of the tunnel magnetoresistive element TMR, that is, the MTJ memory cell. A memory cell current Icell corresponding to the level of stored data passes. For example, the stored data can be read from the MTJ memory cell by comparing the memory cell current Icell with a predetermined reference current.

As described above, tunnel magnetoresistive element TMR changes its electric resistance in accordance with the direction of magnetization that can be rewritten by the applied data write magnetic field, and therefore, tunnel magnetoresistive element TMR has an electric resistance Rmax / Rmin and a stored data By associating each level (“1” / “0”) with each other, nonvolatile data storage can be executed. As described above, in the MRAM device, data storage is performed using the difference in junction resistance (ΔR = Rmax−Rmin) corresponding to the difference in the stored data level in the tunnel magnetoresistive element TMR.
Roy Scheuerline and 6 others, “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Using FET Switches and Magnetic Tunnel Junctions in Each Cell Tunnel Junction and FET Switch in each Cell), (USA), 2000 Annual Meeting of the Institute of Electrical and Electronics Engineers International Solid State Circuits TA7.2 (2000 IEEE ISSCC Digest of Technical Papers, TA7.2), p. 128-129. D. Durlam and five others, “Nonvolatile RAM based on Magnetic Tunnel Junction Elements” (USA), 2000 International Institute of Electrical and Electronics Engineers of Japan Proceedings TA7.3 (2000 IEEE ISSCC Digest of Technical Papers, TA7.3), p. 130-131. Peter K. Naji et al., "256 kb, 3.0 volts and 1 transistor 1 magnetic tunnel junction type non-volatile magnetoresistive random access memory (A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM)" (USA), 2001 IEEE ISSCC Digest of Technical Papers (TA7.6), p. 122-123.

  In general, a reference cell for generating a reference current to be compared with the memory cell current Icell is provided in addition to a normal MTJ memory cell for performing data storage. The reference current generated by the reference cell needs to be designed to be an intermediate value between the two types of memory cell currents Icell respectively corresponding to the two types of electrical resistances Rmax and Rmin of the MTJ memory cell. Basically, these reference cells are also designed to include a tunnel magnetoresistive element TMR similar to a normal MTJ memory cell.

  The passing current of tunneling magneto-resistance element TMR is greatly affected by the thickness of the insulating film used as the tunneling film. For this reason, if the tunnel film thickness results differ between the regular MTJ memory cell and the reference cell, the reference current is not set to a desired level. For this reason, it is difficult to accurately set the level of the reference current generated using the reference cell to a level that can detect the minute current difference as described above. The accuracy may be reduced.

In particular, in a general MTJ memory cell, the resistance difference ΔR generated according to the storage data level is not so large. Typically, the electrical resistance Rmin remains around several tens of percent of Rmax. For this reason, the change of the memory cell current Icell according to the stored data level is not so large and remains in the order of microamperes (μA: 10 ⁻⁶ A). Therefore, it is necessary to increase the accuracy of the tunnel film thickness manufacturing process in the regular MTJ memory cell and reference.

  However, if the tunnel film thickness accuracy in the manufacturing process is tightened, there is a concern about an increase in manufacturing cost due to a decrease in manufacturing yield or the like. Against this background, there is a demand for a configuration for executing data reading based on the above-described resistance difference ΔR in the MTJ memory cell with high accuracy without causing a strict manufacturing process in the MRAM device.

  In order to solve such a problem, a configuration of an MRAM device that performs data reading by only accessing a selected memory cell without using a reference cell, that performs data reading of a so-called “self-reference method” is disclosed in US Pat. No. 6,317,376B1.

  In the conventional self-reference read disclosed in the US patent, one data read operation is continuously executed, (1) reading stored data from the selected memory cell, and (2) reading to the selected memory cell. Data reading after forced writing of “0” data, (3) Data reading after forced writing of “1” data to the selected memory cell, (4) Reading results of (1) to (3) above Read data generation based on this and (5) read data rewrite (restore) to the selected memory cell. According to such a data reading operation, data reading can be executed only by accessing the selected memory cell, so that high-precision data reading can be executed regardless of manufacturing variations of the reference cell.

  However, in the conventional self-reference reading, it is necessary to repeatedly execute forced data writing and data reading in one data reading operation, and the stored data of the selected memory cell is destroyed. Since rewriting is necessary, there is a problem that the speeding up of the data reading operation is hindered.

  The present invention has been made to solve such problems, and an object of the present invention is to configure a thin film magnetic memory device that performs high-speed and high-precision data reading based on a self-reference method. Is to provide.

  A thin-film magnetic memory device according to the present invention includes a plurality of memory cells each magnetized along an easy magnetization axis in a direction corresponding to magnetically written storage data and having an electric resistance corresponding to the magnetization direction. A data line electrically coupled to a fixed voltage via a selected memory cell selected as a data read target among a plurality of memory cells at the time of data reading, and at least a data line coupled to a predetermined voltage at the time of data reading A current supply circuit that receives the first power supply voltage, and a magnetic field application unit that applies a data write magnetic field along a hard magnetization axis to a memory cell that is a data write target during data writing; A data read circuit that receives the second power supply voltage and the fixed voltage and generates read data corresponding to the data stored in the selected memory cell, and the difference between the first power supply voltage and the fixed voltage is the second power supply voltage Voltage Greater than the difference between the fixed voltage.

  Preferably, each of the magnetic field application units is provided for each predetermined section of the plurality of memory cells, and supplies a current for applying a magnetic field in a direction along the hard axis to each corresponding memory cell. A plurality of current wires selectively received and a plurality of current wires are provided corresponding to each of the plurality of current wires, and each is connected in series with a corresponding one of the plurality of current wires between the first power supply voltage and the fixed voltage. A plurality of driver transistors and a plurality of current wiring drive control units provided corresponding to the plurality of current wirings, respectively, each of the plurality of current wiring drive control units corresponding to each at the time of data reading and writing A second control signal for controlling on / off of one of the plurality of driver transistors is generated based on the first control signal indicating whether or not the current wiring to be operated corresponds to the selected memory cell. Having a signal generating circuit that, the signal generation circuit includes a level converting function larger than the amplitude of the amplitude of the second control signal a first control signal.

  More preferably, each current wiring drive control unit further includes an operation current control unit that controls the operation current of the signal generation circuit, and the operation current control unit is configured to reduce the operation current when reading data than when writing data. Decrease.

  The thin film magnetic memory device according to the present invention utilizes the change (increase or decrease) of the electrical resistance of the selected memory cell with the polarity according to the stored data by applying a bias magnetic field along the hard axis direction. Self-reference type data reading in which only the selected memory cell is accessed can be executed at high speed without compulsory data writing and data reading and rewriting of stored data to the selected memory cell. Furthermore, since the configuration for generating the bias magnetic field can be shared with the configuration for generating a predetermined data write magnetic field at the time of data writing, the circuit configuration can be simplified. In particular, since the current wiring can be driven with a sufficient voltage difference, a current for generating a bias magnetic field and a data write magnetic field can be sufficiently supplied.

  Preferably, by gradually generating a bias magnetic field at the time of data reading, it is possible to avoid a sudden fluctuation in the voltage of the data line and to perform stable data reading with reduced noise.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Embodiment 1]
FIG. 1 is a schematic block diagram showing an overall configuration of MRAM device 1 according to the embodiment of the present invention.

  Referring to FIG. 1, MRAM device 1 according to an embodiment of the present invention performs random access in response to a control signal CMD and an address signal ADD from the outside, and is selected as a data read or data write target Input data DIN is written to or output data DOUT is read from a cell (hereinafter also referred to as “selected memory cell”).

  The MRAM device 1 includes a control circuit 5 that controls the overall operation of the MRAM device 1 in response to a control signal CMD, and a memory array 10 that includes MTJ memory cells MC arranged in a matrix. The configuration and data storage principle of each MTJ memory cell MC are the same as those described with reference to FIGS.

  In memory array 10, word line WL and write digit line WDL are arranged corresponding to each row of MTJ memory cells, and bit line BL and source line SL are arranged corresponding to each column of MTJ memory cells. The FIG. 1 shows one representative MTJ memory cell MC and the arrangement of word line WL, write digit line WDL, bit line BL, and source line SL corresponding thereto.

  The MRAM device 1 includes row selection circuits 20 and 21 for performing row selection corresponding to the row address RA indicated by the address signal ADD, and column selection in the memory array 10 based on the column address CA indicated by the address signal ADD. Column decoder 25 and read / write control circuits 30 and 35.

  Read / write control circuits 30 and 35 collectively represent a circuit group for performing a data read operation and a data write operation on MTJ memory cells MC arranged in memory array 10. .

  In the following, binary high voltage states (for example, power supply voltages Vcc1 and Vcc2) and low voltage states (for example, ground voltage GND) such as signals, signal lines, and data are respectively set to “H level” and “ Also referred to as “L level”.

  As will be apparent from the following description, in the present invention, the bias magnetic field is applied to the selected memory cell to speed up the self-reference type data reading. First, the principle of data reading according to the present invention will be described first.

  FIG. 2 is a conceptual diagram showing the relationship (hysteresis characteristics) between the current for applying a magnetic field to the MTJ memory cell and the electrical resistance of the MTJ memory cell.

  Referring to FIG. 2, the horizontal axis represents the bit line current I (BL) flowing through the bit line, and the vertical axis represents the electric resistance Rcell of the MTJ memory cell. The magnetic field generated by the bit line current I (BL) has a direction along the easy axis direction (EA) in the free magnetic layer VL shown in FIG. On the other hand, the magnetic field generated by the digit line current I (WDL) flowing through the write digit line WDL has a direction along the hard axis direction (HA) in the free magnetic layer VL.

  Therefore, when the bit line current I (BL) exceeds the threshold value for reversing the magnetization direction of the free magnetic layer VL, the magnetization direction of the free magnetic layer VL is reversed and the memory cell resistance Rcell changes. In FIG. 2, when the bit line current I (BL) in the plus direction exceeds the threshold value, the memory cell resistance Rcell becomes the maximum value Rmax, and the bit line current I (BL) in the minus direction is reduced. When flowing beyond the threshold value, the memory cell resistance Rcell becomes the minimum value Rmin. The threshold value of the bit line current I (BL) varies depending on the current I (WDL) flowing through the write digit line WDL.

  First, the hysteresis characteristic of the memory cell resistance Rcell when the digit line current I (WDL) flowing through the write digit line WDL = 0 is shown by a dotted line in FIG. In this case, the threshold values of the bit line current I (BL) in the positive direction and the negative direction are respectively It0 and -It0.

  On the other hand, when a current flows through write digit line WDL, the threshold value of bit line current I (BL) decreases. In FIG. 2, the hysteresis characteristic of the memory cell resistance Rcell when the digit line current I (WDL) = Ip is shown by a solid line. Due to the influence of the magnetic field in the hard axis direction caused by the digit line current I (WDL), the positive and negative thresholds of the bit line current I (BL) become It1 (It1 <It0) and −It1 (− It1> -It0). This hysteresis characteristic indicates the behavior of the memory cell resistance Rcell during the data write operation. Therefore, the bit line current I (BL) during the data write operation, that is, the data write currents + Iw and −Iw are set in the range of It1 <+ Iw <It0 and −It0 <−Iw <−It1.

  On the other hand, the bit line current I (BL) in the data read operation, that is, the data read current Is flows as a charge current for the data line DIO connected with the selected memory cell, parasitic capacitance, etc. as the RC load. Compared with the bit line current I (BL) at, that is, the data write current ± Iw, it is generally a level that is two to three orders of magnitude smaller. Therefore, in FIG. 2, it can be considered that the data read current Is≈0.

  In the state before data reading, the state (a) or (c) in FIG. 2, that is, the free magnetic layer in tunneling magneto-resistance element TMR so that the selected memory cell has either electric resistance Rmin or Rmax. The magnetization direction is set.

  FIG. 3 is a conceptual diagram illustrating the magnetization direction of the tunnel magnetoresistive element in each state shown in FIG.

  FIG. 3A shows the magnetization direction in the state shown in FIG. In this state, since the magnetization direction of the free magnetic layer VL and the magnetization direction of the fixed magnetic layer FL are parallel, the memory cell resistance Rcell is set to the minimum value Rmin.

  FIG. 3C shows the magnetization direction in the state shown in FIG. In this state, since the magnetization direction of the free magnetic layer VL and the magnetization direction of the fixed magnetic layer FL are antiparallel (reverse direction), the memory cell resistance Rcell is set to the maximum value Rmax.

  From this state, when a predetermined current (for example, data write current Ip) is passed through write digit line WDL, the magnetization direction of free magnetic layer VL does not reach the inverted state, but is rotated to some extent, and tunneling occurs. The electric resistance Rcell of the magnetoresistive element TMR changes.

  For example, as shown in FIG. 3B, when a predetermined bias magnetic field in the hard axis (HA) direction due to the digit line current I (WDL) is further applied from the magnetization state of FIG. The magnetization direction of the free magnetic layer VL is somewhat rotated to form a predetermined angle with the magnetization direction of the fixed magnetic layer FL. Thereby, in the magnetization state corresponding to FIG. 3B, the memory cell resistance Rcell increases from the minimum value Rmin to Rm0.

  Similarly, when the same predetermined bias magnetic field is further applied from the magnetization state of FIG. 3C, the magnetization direction of the free magnetic layer VL is somewhat rotated, and the magnetization direction of the fixed magnetic layer FL and the predetermined magnetic field Make an angle. Thereby, in the magnetization state corresponding to FIG. 3D, the memory cell resistance Rcell falls from the maximum value Rmax to Rm1.

  As described above, by applying a bias magnetic field in the hard axis (HA) direction, the memory cell resistance Rcell of the MTJ memory cell storing data corresponding to the maximum value Rmax is lowered, while corresponding to the minimum value Rmin. The memory cell resistance Rcell of the MTJ memory cell that stores data increases.

  In this way, if a bias magnetic field in the hard axis direction is applied to an MTJ memory cell in which certain storage data is written, a change in electrical resistance having a polarity corresponding to the storage data is caused in the memory cell resistance Rcell. be able to. That is, the change in the memory cell resistance Rcell that occurs in response to the application of the bias magnetic field has a different polarity according to the stored data level. In the present embodiment, data reading is executed using such magnetization characteristics of the MTJ memory cell.

  FIG. 4 is a circuit diagram showing a configuration according to the first embodiment of a circuit group for performing a data read operation and a data write operation on memory array 10.

  Referring to FIG. 4, in memory array 10, MTJ memory cells MC are arranged in a matrix. As already described, word line WL and write digit line WDL are arranged corresponding to each memory cell row, and bit line BL and source line SL are arranged corresponding to each memory cell column. Each of MTJ memory cells MC has a configuration similar to that described with reference to FIG. 11, and includes tunneling magneto-resistance element TMR and access transistor ATR connected in series between corresponding bit line BL and source line SL. Including.

  As already described, tunneling magneto-resistance element TMR has an electrical resistance corresponding to the magnetization direction. That is, before data reading, in each MTJ memory cell, tunnel magnetoresistive element TMR stores either H level (“1”) or L level (“0”) data in a predetermined direction. And its electric resistance is set to either Rmax or Rmin.

  Each source line SL is coupled to a fixed voltage Vss (typically ground voltage GND). Thereby, the source voltage of each access transistor ATR is fixed to Vss. As a result, in the selected row where the corresponding word line WL is activated to H level, tunneling magneto-resistance element TMR is connected to bit line BL while being pulled down to fixed voltage Vss (ground voltage GND).

  Next, the circuit configuration of the row selection circuits 20 and 21 for executing row selection in the memory array 10 will be described.

  Row selection circuits 20 and 21 have a word line driver 80 and a write digit line driver 85 arranged for each memory cell row. Although not shown, each word line driver 80 is supplied with power supply voltage Vcc2 and fixed voltage Vss, and each write digit line driver 85 is supplied with power supply voltage Vcc1 and fixed voltage Vss. The power supply voltage Vcc1 is higher than the power supply voltage Vcc2, that is, | (Vcc1-Vss) |> | (Vcc2-Vss) |.

  Each word line driver 80 is provided on one end side of each word line WL, and is based on a corresponding one of row decode signals Rd (1) to Rd (4),... The activation of the word line WL to be controlled is controlled. Specifically, the word line WL is connected by the word line driver 80 to the power supply voltage Vcc2 (H level) when activated, and to the fixed voltage Vss when deactivated.

  Each write digit line driver 85 is provided on one end side of each write digit line WDL, and is based on a corresponding one of row decode signals Rd (1) to Rd (4),... The activation of the corresponding write digit line WDL is controlled. Specifically, the write digit line WDL is connected by the write digit line driver 85 to the power supply voltage Vcc1 (H level) when activated, and to the fixed voltage Vss when deactivated. In the following description, the row decode signals Rd (1) to Rd (4),... Are collectively referred to simply as a row decode signal Rd.

  Row decode signal Rd is obtained by a decode circuit (not shown), and is set to H level (power supply voltage Vcc2) when a corresponding memory cell row is selected. Otherwise, row decode signal Rd is set to L level (fixed). Voltage Vss). At least in one data read operation and one data write operation, the row decode signal Rd of each memory cell row is held by a latch circuit (not shown).

Further, a transistor switch 90 for coupling the other end side of the word line WL to the fixed voltage Vss is arranged corresponding to each memory cell row except during data reading including data writing. Transistor switch 90 receives at its gate an inverted signal / RE of control signal RE activated (H level) during data reading, and is electrically coupled between word line WL and fixed voltage Vss. In the configuration example of FIG. 4, the transistor switch 90 is configured by an N-channel MOS (Metal Oxide Semiconductor) transistor. In this specification, a MOS transistor is shown as a typical example of a field effect transistor.

  The other end side of the write digit line WDL is connected to the fixed voltage Vss. Therefore, at the time of data writing, data write current Ip flows through activated write digit line WDL from write digit line driver 85 in the direction toward fixed voltage Vss.

  On the other hand, at the time of data reading, each word line WL is disconnected from fixed voltage Vss by transistor switch 90. Further, the word line driver 80 activates the corresponding word line WL according to the row decode signal Rd of the corresponding memory cell row. In response, access transistor ATR corresponding to the selected row is turned on, and tunneling magneto-resistance element TMR is electrically coupled between bit line BL and source line SL. In this way, the row selection operation in the memory array 10 is executed.

  A similar configuration is similarly provided corresponding to the word line WL and write digit line WDL of each memory cell row. As shown in FIG. 4, word line drivers 80 and write digit line drivers 85 are arranged in a staggered manner for each memory cell row. That is, the word line driver 80 and the write digit line driver 85 are alternately arranged for each row on one end side of the word line WL and the write digit line WDL and on the other end side of the word line WL and the write digit line WDL. Thereby, the row selection circuits 20 and 21 can be efficiently arranged with a small area.

  Read / write control circuit 30 further includes a write driver control circuit 180. The write driver control circuit 180 operates in response to an operation instruction from the control circuit 5. Write driver control circuit 180 writes a write control signal for each memory cell column according to input data DIN transmitted via data input terminal 4b and input buffer 195 and the column selection result from column decoder 25 during operation. WDTa and WDTb are set.

  Read / write control circuit 30 further includes a write driver WDVb arranged for each memory cell column. Similarly, read / write control circuit 35 includes a write driver WDVa provided for each memory cell column. In each memory cell column, the write driver WDVa drives one end side of the corresponding bit line BL with either the power supply voltage Vcc1 or the fixed voltage Vss in accordance with the corresponding write control signal WDTa. Similarly, the write driver WDVb drives the other end side of the corresponding bit line BL with either the power supply voltage Vcc1 or the fixed voltage Vss in accordance with the corresponding write control signal WDTb.

  At the time of data writing, write control signals WDTa and WDTb corresponding to the selected column are set to one of H level and L level according to the level of write data DIN. For example, when H level (“1”) data is written, write control signal WDTa is set to H level in order to flow data write current + Iw in the direction from write driver WDVa to WDVb, and WDTb Is set to L level. On the other hand, when writing L level (“0”) data, write control signal WDTb is set to H level in order to flow data write current −Iw in the direction from write driver WDVb to WDVa. , WDTa are set to L level. In the following, data write currents + Iw and -Iw in different directions are collectively referred to as data write currents ± Iw.

  In the non-selected column, each of write control signals WDTa and WDTb is set to the L level. Also, except during the data write operation, write control signals WDTa and WDTb are set to the L level.

  In tunnel magnetoresistive element TMR in which data write currents Ip and ± Iw are supplied to both corresponding write digit line WDL and bit line BL, the write data corresponding to the direction of data write current ± Iw is magnetically Written. A similar configuration is similarly provided corresponding to the bit line BL of each memory cell column.

Next, a data reading operation from the memory array 10 will be described.
Read / write control circuit 30 further includes a data line DIO for transmitting a voltage corresponding to the electric resistance of the selected memory cell, and a read selection gate RCSG provided between data line DIO and each bit line BL. including. A read column selection line RCSL indicating the selection state of the corresponding memory cell column is coupled to the gate of read selection gate RCSG. Each read column selection line RCSL is activated to H level when the corresponding memory cell column is selected. A similar configuration is provided corresponding to each memory cell column. That is, the data line DIO is shared by the bit line BL on the memory array 10.

  With such a configuration, the selected memory cell is electrically coupled to data line DIO via bit line BL of the selected column and corresponding read selection gate RCSG during data reading.

  Read / write control circuit 30 further includes a data read circuit 100 and a current supply transistor 105.

  The data read circuit 100 includes a coupling capacitor 110, a sense amplifier (voltage amplifier) 120, a voltage holding capacitor 130, a feedback switch 140, a transistor switch 145, a sense amplifier (voltage amplifier) 146, and a latch circuit 148. Including.

  Coupling capacitor 110 is connected between sense input node N1 (corresponding to one of the input nodes of sense amplifier 120) and data line DIO. Voltage holding capacitor 130 is connected between sense input node N2 and fixed voltage Vss in order to hold the voltage level of sense input node N2 (corresponding to the other input node of sense amplifier 120). Sense amplifier 120 amplifies the voltage difference between sense input nodes N1 and N2, and outputs the amplified voltage difference to node N3 (corresponding to the output node of sense amplifier 120). The feedback switch 140 is provided between the node N3 and the sense input node N2. The transistor switch 145 is provided between the data line DIO and the sense input node N1. In response to the control signal / RS, the feedback switch 140 and the transistor switch 145 are turned on before the bias magnetic field is applied and turned off after the bias magnetic field is applied in the data read operation.

  Sense amplifier 146 amplifies and outputs a voltage difference between a predetermined reference voltage Vcp and node N3. Latch circuit 148 latches the output of sense amplifier 146 and outputs it as read data RDT at a predetermined timing after the application of the bias magnetic field during the data read operation. Read data RDT read from latch circuit 148 is output as output data DOUT from data output terminal 4a via output buffer 190. Thus, the voltage difference between the sense input nodes N1 and N2 is amplified by the plurality of stages of sense amplifiers 120 and 146, so that a sufficient operation margin can be ensured. Further, since the sensitivity can be changed by adjusting the level of the reference voltage Vcp input to the second-stage sense amplifier 146, it is possible to correct a change in sensitivity due to variations in element characteristics during manufacturing.

  Current supply transistor 105 is formed of a P-channel MOS transistor, and receives at its gate a control signal WE which is an inverted signal of control signal / WE activated (H level) in a data write operation. That is, the current supply transistor 105 is turned on except during the data write operation.

  Therefore, data line DIO is coupled to precharge voltage Vpc by turning on current supply transistor 105 before the data read operation. At this stage, the data line DIO is charged to the precharge voltage Vpc because the read selection gate RCSG in each memory cell column is disconnected from the bit line BL and the memory cell MC.

  When the data read operation is started, the word line WL of the selected row and the read column selection line RCSL of the selected column are activated to the H level, and the data line DIO receives the fixed voltage Vss (ground voltage) via the selected memory cell. Pulled down to GND). Since the current supply transistor 105 maintains the turn-on state even during the data read operation, the data read current Is passing through the selected memory cell is supplied by the precharge voltage Vpc. As a result, a voltage corresponding to the electric resistance of the selected memory cell is generated on the data line DIO.

  One data read operation includes a first half period in which a bias magnetic field is not applied to the selected memory cell and a second half period in which a bias magnetic field is applied to the selected memory cell. In the latter half period, the write digit line driver 85 of the selected row operates in the same manner as when data is written, and activates the corresponding write digit line WDL. That is, a bias magnetic field is generated by the current supplied to the write digit line WDL of the selected row. With such a configuration, it is not necessary to newly arrange a circuit for generating a bias magnetic field at the time of data reading, so that the circuit configuration can be simplified.

  Before the bias magnetic field is applied, that is, in a state where no current is passed through the corresponding write digit line WDL (I (WDL) = 0), the data line DIO settles to a voltage corresponding to the storage data of the selected memory cell.

  Next, after applying the bias magnetic field, that is, in a state where a bias current is passed through the write digit line WDL corresponding to the selected row (I (WDL) = Ip), a predetermined memory cell along the hard axis direction is selected. The bias magnetic field acts. As described above, by applying such a bias magnetic field, the memory cell resistance Rcell of the selected memory cell changes with a polarity corresponding to the stored data level as compared to before the bias magnetic field application. Thereby, the voltage of the data line DIO rises or falls than before the bias magnetic field application.

  Specifically, when storage data (for example, “0”) corresponding to the electrical resistance Rmin is stored in the selected memory cell, the data line voltage is higher after the bias magnetic field is applied than before the bias magnetic field is applied. Get higher. This is because the current flowing through the tunnel magnetoresistive element TMR decreases as the memory cell resistance Rcell increases due to the action of the bias magnetic field caused by the digit line current I (WDL). On the other hand, when storage data (for example, “1”) corresponding to the electric resistance Rmax is stored in the selected memory cell, the data line voltage is higher after the bias magnetic field is applied than before the bias magnetic field is applied. Lower. This is because the current flowing through the tunnel magnetoresistive element TMR increases as the memory cell resistance Rcell decreases due to the action of the bias magnetic field caused by the digit line current I (WDL).

Next, the operation of the data read circuit 100 will be described in detail with reference to FIG.
FIG. 5 is a circuit diagram showing a configuration of a main part of the data read circuit shown in FIG.

  Referring to FIG. 5, sense amplifier 120 is connected between power supply voltage Vcc2 and nodes N3 and N4, P channel MOS transistors 122 and 124, respectively, and between nodes N3 and N4 and fixed voltage Vss, respectively. N channel MOS transistors 126 and 128 are provided. The gates of transistors 122 and 124 are connected to node N4, the gate of transistor 126 is connected to sense input node N2, and the gate of transistor 128 is connected to sense input node N1. That is, the transistors 122 to 128 operate as “differential amplifiers” having the sense input nodes N1 and N2 as input nodes and the node N3 as an output node.

  Since the arrangement of coupling capacitor 110, current supply transistor 105, voltage holding capacitor 130, feedback switch 140, and transistor switch 145 has been described with reference to FIG. 4, detailed description thereof will not be repeated.

  Before the data read operation, each of current supply transistor 105, feedback switch 140, and transistor switch 145 is on, so that data line DIO is precharged to precharge voltage Vpc, and data line DIO and sense input node N1 is short-circuited, and the sense input node N2 and the node N3 are also short-circuited.

  In this state, the data read operation is started, and the data line DIO is pulled down to the fixed voltage Vss (ground voltage GND) via the selected memory cell. Even during the data read operation, the current supply transistor 105 maintains the ON state, so that the current supply transistor 105 has not only the precharge function of the data line DIO before the data read operation but also the data line DIO during the data read operation. It also has a data read current supply function. As a result, the voltage of the data line DIO falls below the precharge voltage Vpc according to the passing current of the selected memory cell, that is, the electric resistance of the selected memory cell. The voltage of data line DIO at the time of data reading is determined by the relationship between the impedance of current supply transistor 105 and the impedance (electric resistance) of the selected memory cell.

  In the first half period from the start of data reading to the application of the bias magnetic field, control signal / RS is inactivated to the H level. Therefore, since feedback switch 140 and transistor switch 145 are turned on, data line DIO and sense input node N1, and sense input node N2 and node N3 remain short-circuited. As a result, in the first half of the data read operation (before applying the bias magnetic field), sense input nodes N1 and N2 are virtually short-circuited by the negative feedback operation by sense amplifier 120 and set to the same voltage level. . The voltage at the sense input node N2 in this state is held by the voltage holding capacitor 130 even after the bias magnetic field is applied.

  Strictly speaking, there may occur a case where the sense input nodes N1 and N2 are not set to the same voltage due to variations in the element characteristics of the circuit elements constituting the sense amplifier 120. However, the voltage at the sense input node N2 including such variations may also occur. Is set in an equilibrium state in accordance with the voltage at the sense input node N1, so that the offset adjustment of the sense amplifier is also performed.

  Thereafter, control signal / RS is activated to L level during the latter half of the data read operation, that is, after application of a bias magnetic field to the selected memory cell. Thereby, data line DIO and sense input node N1, and sense input node N2 and node N3 are disconnected from each other. In this state, due to the action of the bias magnetic field on the selected memory cell, the voltage of the data line DIO rises or falls depending on the data stored in the selected memory cell than before the bias magnetic field is applied.

  The voltage change generated on data line DIO is transmitted to sense input node N1 by capacitive coupling by coupling capacitor 110. Therefore, the sense amplifier 120 amplifies the voltage difference between the voltage at the sense input node N2 (held by the voltage holding capacitor 130) that has reached an equilibrium state before application of the bias magnetic field and the voltage at the sense input node N1 after application of the bias magnetic field. Can be output to the node N3. That is, the voltage of the node N3 varies depending on the data stored in the selected memory cell.

FIG. 6 is an operation waveform diagram illustrating a data read operation according to the embodiment of the present invention.
Referring to FIG. 6, one data read operation according to the embodiment of the present invention can be executed in synchronization with clock signal CLK, for example.

  That is, when the chip select signal CS and the read command RC are taken in at the time t1, which is the activation edge of the clock signal CLK, the data read operation is started. As a result, the word line WL in the selected row is activated and the data read current Is is supplied to the bit line BL in the selected column. In the first half of the time t1 to tr (the H level period of the control signal / RS), the bias magnetic field is not applied, and the voltage of the bit line in the selected column, that is, the data line DIO is the electric resistance (memory data) of the selected memory cell. Reach the level according to. The data line voltage at this time is transmitted to sense input nodes N1 and N2, and held by voltage holding capacitor 130 at sense input node N2.

  In the second half after time tr (L level period of control signal / RS), word line WL and control signal RE in the selected row remain activated (H level), and write digit line WDL in the selected row. On the other hand, a bias current equivalent to the data write current Ip is made to flow gradually. That is, a bias magnetic field is gradually applied to the selected memory cell. In response to this, the voltage of the bit line (data line DIO) of the selected column changes (increases or decreases) with a polarity corresponding to the storage data of the selected memory cell. A configuration for supplying a bias current for generating a bias magnetic field will be described in detail later in a second embodiment.

  Since the change in the data line voltage due to the bias magnetic field is transmitted to the sense input node N1 by the coupling capacitor 110, a voltage difference of polarity according to the storage data of the selected memory cell is generated between the sense input nodes N1 and N2. . Read data RDT can be generated by amplifying the voltage difference using sense amplifiers 120 and 146 and latch circuit 148.

  Further, output data DOUT corresponding to read data RDT is output from data output terminal 4a at time t2 corresponding to the next clock activation edge. The magnetization direction of tunneling magneto-resistance element TMR is not reversed by the bias magnetic field applied to the selected memory cell by the bias current (data write current Ip) flowing through write digit line WDL. Therefore, when the bias magnetic field is extinguished, the magnetization direction of the selected memory cell returns to the same state as before the data read operation. Thus, since data reading according to the embodiment of the present invention is nondestructive reading, data rewriting operation like conventional self-reference reading is unnecessary.

  It should be noted that the MRAM device can also be configured from a plurality of blocks, with the configuration for executing 1-bit data reading and data writing shown in FIG. 4 as one block. FIG. 6 also shows the data read operation in such a configuration.

  In an MRAM device having a plurality of blocks, the same data read operation is executed in parallel in each block, and read data RDT from the selected memory cell is generated in each block at time t2. In such a configuration, at each clock activation edge after time t2, the read data RDT from each of the plurality of blocks can be output as output data DOUT in a burst manner. In FIG. 6, at time t2, “0” is output as output data DOUT corresponding to read data RDT from one block, and from time t3 which is the next clock activation edge, another 1 is output. An operation example in which “1” is output as output data DOUT corresponding to read data RDT in one block is shown.

  As described above, also in the configuration according to the present embodiment, the self-reference type data reading can be executed only by accessing the selected memory cell without using the reference cell. That is, read data is generated based on voltage comparison performed by the same data read path including the same memory cell, the same bit line, the same data line, the same sense amplifier, and the like. Since no reference cell is required, data can be stored in each MTJ memory cell, and all MTJ memory cells can be used as effective bits.

  By performing the self-reference type data reading, it is possible to avoid the influence of offset and the like due to manufacturing variations in each circuit constituting the data reading path, and to increase the accuracy of the data reading operation. That is, rather than performing data reading from the selected memory cell based on a comparison with other memory cells such as a reference cell and a data read circuit system associated therewith, eliminating the influence of manufacturing variations and the like, High-precision data reading can be executed.

  Further, in the configuration according to the present embodiment, in one data read operation, there is compulsory data writing and data reading as in the conventional self-reference reading, and the stored data destruction of the selected memory cell. Since rewriting is unnecessary, self-reference reading can be performed at high speed.

  In particular, data read is executed by starting application of a bias magnetic field while maintaining activation of the word line WL and taking out a continuous voltage change of the data line DIO due to the action of the bias magnetic field at a predetermined timing. Therefore, data reading can be further speeded up.

  Further, since the offset of the sense amplifier 120 can be adjusted by the negative feedback operation of the sense amplifier 120 before the bias is applied, the data reading can be further improved in accuracy.

  Further, by using the current flowing through write digit line WDL used at the time of data writing as a bias current for generating a bias magnetic field, a circuit configuration without newly arranging a circuit for supplying a bias current at the time of data reading Can be simplified.

[Modification of Embodiment 1]
In the first modification of the first embodiment, another configuration example of the data read circuit will be described.

  FIG. 7 is a circuit diagram showing a configuration of a main part of the data read circuit according to the modification of the first embodiment.

  Referring to FIG. 7, in the configuration according to the modification of the first embodiment, a precharge transistor 149 is provided instead of transistor switch 145 as compared with the configuration according to the first embodiment shown in FIG. It is different. Since the configuration of the data read circuit excluding the peripheral circuit portion of sense amplifier 120 shown in FIG. 7 and the configuration of other circuits are similar to those of the first embodiment, detailed description thereof will not be repeated.

  Precharge transistor 149 is formed of an N channel MOS transistor, and is connected between precharge voltage Vpc # and sense input node N1. Similar to feedback switch 140, precharge transistor 149 is turned on / off in response to control signal / RS.

  With such a configuration, sense input node N1 is precharged to precharge voltage Vpc # before the data read operation and before the bias magnetic field is applied during the data read operation. As a result, sense input node N2 is set to the same level as precharge voltage Vpc #.

  On the other hand, the data line DIO is precharged to the precharge voltage Vpc by the current supply transistor 105 before the data read operation as in the first embodiment, and in the data read operation, the electric resistance (memory) of the selected memory cell is stored. The voltage level changes according to the data.

  From this state, after the bias magnetic field is applied, the feedback switch 140 and the precharge transistor 149 are turned off, and the bias magnetic field is applied as in the first embodiment. Accordingly, the voltage at sense input node N1 changes from precharge voltage Vpc # according to the voltage change of data line DIO before and after application of the bias magnetic field. On the other hand, since sense input node N2 is held at precharge voltage Vpc #, the voltage at node N3 which is the output node of sense amplifier 120 changes in the same manner as in the first embodiment. As a result, data reading similar to that in the first embodiment is executed.

  As described above, in the configuration according to the modification of the first embodiment, precharge voltage Vpc of data line DIO and precharge voltage Vpc # of sense input nodes N1 and N2 in an equilibrium state before application of a bias magnetic field are made independent. Each can be set optimally.

For example, while considering the MR (Magneto-Resistive) characteristic in the MTJ memory cell, the precharge voltage Vpc of the data line DIO is set to a level at which the junction resistance difference ΔR (Rmax−Rmin) is likely to appear. Independently, precharge voltage Vpc # of sense input nodes N1 and N2 can be set to a level suitable for securing an operation margin of sense amplifier 120. This is realized by insulating the data line DIO and the sense input node N1 of the sense amplifier 120 by the coupling capacitor 110. Therefore, the precharge voltages of data line DIO and sense input node N1 can be arbitrarily selected.

  By adopting such a configuration, it is possible to further improve the data read operation margin as compared with the configuration according to the first embodiment.

[Embodiment 2]
In the second embodiment, a configuration for supplying a current to write digit line WDL also used as a data write current (during data writing) and a bias current (during data reading) will be described.

  FIG. 8 is a circuit diagram showing a configuration according to the second embodiment of a circuit group for controlling current supply to write digit line WDL.

  Referring to FIG. 8, write digit line driver 85 provided corresponding to each of write digit lines WDL has a corresponding write digit line between power supply voltage line VPL transmitting power supply voltage Vcc1 and ground voltage line GPL. A driver transistor 86, which is an N-channel MOS transistor, is connected in series with the WDL. The ground voltage wiring GPL is connected to the fixed voltage Vss through the transistor switch 88. The transistor switch 88 is turned on / off in response to the control signal ACT. The control signal ACT is activated to H level during the activation period except for the standby mode and the low power consumption mode of the MRAM device. In the inactive period of the control signal ACT, the ground voltage wiring GPL is in a floating state, and the source voltage of the N-channel MOS transistor is raised so that the gate-source voltage becomes a negative voltage, thereby reducing the leakage current of the transistor. Can be reduced.

  Further, a write digit line drive controller 150 is arranged corresponding to each write digit line driver 85 (driver transistor 86), that is, corresponding to each memory cell row.

  Each write digit line drive control unit 150 turns on the corresponding driver transistor 86 on the basis of the row selection result of the corresponding memory cell row at each of data reading and data writing. A current flows in the direction from the power supply voltage line VPL to the ground voltage line GPL through the write digit line WDL in which the driver transistor 86 is turned on. Thus, in order to pass a sufficient data write current during data writing, activated write digit line WDL has a power supply voltage Vcc1 higher than power supply voltage Vcc2 of other peripheral circuits including the data read circuit system. Driven by.

  Write digit line drive control unit 150 includes a logic circuit 155, a level conversion circuit 160, a current supply transistor 165, and an inverter 170. FIG. 8 representatively shows the configuration of the write digit line drive controller 150 in the j-th row (j: natural number) as an example.

  Logic circuit 155 outputs a logical gate 156 that outputs an OR logical operation result of control signals WE and RS, and outputs an AND logical operation result of row decode signal Rd (j) and an output signal of logical gate 156 to node N10. A gate 157. Control signals WE and RS are assumed to have an amplitude from fixed voltage Vss (L level) to power supply voltage Vcc2 (H level), similarly to the signal of data read system circuit (sense amplifier 120 and the like). That is, row decode signal Rd (j) is activated to H level (power supply voltage Vcc2) when the corresponding memory cell row is selected.

  By the logic circuit 155, the voltage of the node N10 is changed depending on whether the corresponding memory cell row is at the time of data writing (control signal WE = H level) or when the bias voltage is applied at the time of data reading (control signal RS = H level). When selected, it is set to H level (power supply voltage Vcc2), and otherwise it is set to L level (fixed voltage Vss).

  Inverter 170 has P channel MOS transistor 172 and N channel MOS transistor 174 connected to form a CMOS inverter between power supply voltage Vcc2 and fixed voltage Vss. Transistors 172 and 174 have their gates connected to node N10, and transistors 172 and 174 have their connection gates connected to node N12.

  Level conversion circuit 160 includes P-channel MOS transistors 161 and 162 connected between node N11 and nodes Ng and / Ng, respectively, and N-channel MOS connected between nodes Ng and / Ng and fixed voltage Vss, respectively. Transistors 163 and 164 are included. Transistor 161 has its gate connected to node / Ng, and transistor 162 has its gate connected to node Ng. Transistor 163 has its gate connected to node N12 corresponding to the output node of inverter 170, and transistor 164 has its gate connected to node N10.

  Level conversion circuit 160 sets output node Ng to H level (power supply voltage Vcc1) and node N10 to L level (fixed voltage Vss) when node N10 is set to H level (power supply voltage Vcc2). When set, output node Ng is set to L level (fixed voltage Vss). Node Ng is connected to the gate of corresponding driver transistor 86. The voltage of node / Ng is set to an inversion level with respect to node Ng.

  As described above, the level conversion circuit 160 increases the amplitude of the output signal of the logic circuit 155 based on the row selection result of the corresponding memory cell row and transmits it to the gate of the driver transistor 86.

  Current supply transistor 165 is formed of a P-channel MOS transistor connected between power supply voltage Vcc1 and node N11 and receiving control signal RS at its gate. Therefore, the current supply transistor 165 controls the operating current of the level conversion circuit 160 according to the level of the control signal RS.

  Specifically, during the L level period of the control signal RS, the current supply transistor 165 is fully turned on to supply the operating current, so that the level conversion circuit 160 can operate at high speed. On the other hand, in the H level period of the control signal RS, the gate voltage of the current supply transistor 165 is set to Vcc2, which is an intermediate level between the power supply voltage Vcc1 and the fixed voltage Vss. The current decreases. As a result, the operation of the level conversion circuit 160 is reduced by reducing the operating current.

  Therefore, in the data write operation, the gate voltage of driver transistor 86 in the selected row is quickly changed to the H level (power supply voltage Vcc1) by level conversion circuit 160 to which the operating current is fully supplied. As a result, write digit line WDL is coupled to power supply voltage Vcc1, and the supply of the data write current is quickly started.

  On the other hand, when the bias magnetic field is applied in the data read operation, the operating current for the level conversion circuit 160 is decreased, so that the gate voltage of the driver transistor 86 in the selected row is gradually H level (power supply voltage Vcc1). To change. As a result, the bias current supplied to write digit line WDL rises more slowly than the data write current during data writing.

  As a result, the bias magnetic field applied to the selected memory cell also changes gradually, so that the voltage of the data line DIO can be avoided from fluctuating rapidly, and stable data reading with reduced noise becomes possible.

  Further, by providing transistor switch 88 for ground voltage line GPL, write digit line WDL at the time of non-selection can be brought into a floating state. As a result, in the driver transistor 86 (N channel MOS transistor) corresponding to the non-selected write digit line, the source voltage (write digit line WDL voltage) is higher than the gate voltage (fixed voltage Vss). As a result, since a negative bias is applied between the gate and the source, the leakage current of the driver transistor 86 can be reduced.

  As a result, even if the threshold voltage of the driver transistor 86 is set low in order to increase the current driving capability at turn-on, the generation of leakage current at turn-off can be prevented.

[Modification 1 of Embodiment 2]
FIG. 9 is a circuit diagram showing a configuration according to the first modification of the second embodiment of the circuit group for controlling the current supply to write digit line WDL.

  Referring to FIG. 9, in the configuration according to the modification of the second embodiment, driver transistor 87 in which write digit line driver 85 is a P-channel MOS transistor, as compared with the configuration according to the second embodiment shown in FIG. The point which is comprised by differs. The gate of driver transistor 87 is connected to / Ng instead of node Ng.

  Accordingly, unlike the configuration shown in FIG. 8, transistor switch 88 is connected between power supply voltage Vcc1 and power supply voltage wiring VPL by applying a P-channel MOS transistor. Also, / ACT, which is an inverted signal of the control signal ACT, is input to the gate of the transistor switch 88.

  In write digit line drive control unit 150, N channel MOS transistor is applied as current supply transistor 165, and is provided not between power supply voltage Vcc1 and node N11 but between node N13 and fixed voltage Vss. Further, a current limit control circuit 175 for controlling the gate voltage of the current supply transistor 165 is further provided.

  Current limit control circuit 175 has a P-channel MOS transistor 176 connected between power supply voltage Vcc2 and node N14, and an N-channel MOS transistor 178 connected between node N14 and fixed voltage Vss. Node N14 is connected to the gate of current supply transistor (N-channel MOS transistor) 165. Since the gate of the transistor 176 is connected to the fixed voltage Vss, the transistor 176 is always on. On the other hand, the control signal RS is input to the gate of the transistor 178.

  Current limit control circuit 175 controls the voltage level of node N14 in response to control signal RS. Specifically, the voltage at node N14 is set to an intermediate level between power supply voltage Vcc2 and fixed voltage Vss during the H level period of control signal RS, that is, the bias magnetic field application period during data reading. As a result, the current passing through the current supply transistor 165 is limited, and the operation speed of the level conversion circuit 160 decreases. That is, voltage changes at nodes Ng and / Ng by level conversion circuit 160 are gradual.

  On the other hand, in the L level period of the control signal RS, the node N14 is set to the power supply voltage Vcc2 by the transistor 176. As a result, the passing current of current supply transistor 165 increases, and voltage changes at nodes Ng and / Ng by level conversion circuit 160 are rapid.

  Since the configuration and operation of the other parts of write digit line drive control unit 150 are the same as those described in FIG. 8, detailed description thereof will not be repeated. Therefore, even when a P-channel MOS transistor is applied to the driver switch of write digit line WDL, it is possible to enjoy the same effect as in the second embodiment.

[Modification 2 of Embodiment 2]
FIG. 10 is a circuit diagram showing a configuration according to the second modification of the second embodiment of the circuit group for controlling the current supply to the write digit line WDL.

  Referring to FIG. 10, in the configuration according to the second modification of the second embodiment, driver transistor 86, which is an N channel MOS transistor, has a corresponding write operation compared to the configuration according to the second embodiment shown in FIG. The difference is that it is connected between digit line WDL and fixed voltage Vss. Further, the arrangement of the transistor switch 88 for bringing the write digit line WDL into a floating state during standby is omitted.

  Since the configuration and operation of other parts including write digit line drive control unit 150 are the same as those described in FIG. 8, detailed description thereof will not be repeated. Even with such a configuration, it is possible to enjoy the same effects as those of the second embodiment.

  In the P-channel MOS transistor and the N-channel MOS transistor having the same transistor size, the latter has a larger current driving capability. Therefore, depending on the use of the N-channel MOS transistor as the driver transistor and the arrangement of the transistor switch 88, In the configuration shown in FIG. 8, the write digit line driver 85 can be particularly downsized.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of an MRAM device 1 according to an embodiment of the present invention. It is a conceptual diagram for illustrating the principle of a data read operation according to an embodiment of the present invention. It is a conceptual diagram explaining the magnetization direction of the tunnel magnetoresistive element in each state shown in FIG. 1 is a circuit diagram showing a configuration according to a first embodiment of a circuit group for performing a data read operation and a data write operation on memory array 10. FIG. FIG. 5 is a circuit diagram showing a configuration of a main part of the data reading circuit shown in FIG. 4. FIG. 11 is an operation waveform diagram illustrating a data read operation according to the embodiment of the present invention. FIG. 10 is a circuit diagram showing a configuration of a main part of a data read circuit according to a modification of the first embodiment. FIG. 6 is a circuit diagram showing a configuration according to a second embodiment of a circuit group that controls current supply to a write digit line WDL. FIG. 10 is a circuit diagram showing a configuration according to a first modification of the second embodiment of a circuit group that controls current supply to a write digit line WDL. FIG. 11 is a circuit diagram showing a configuration according to a second modification of the second embodiment of a circuit group that controls current supply to the write digit line WDL. It is the schematic which shows the structure of an MTJ memory cell. It is a conceptual diagram explaining the data write-in operation | movement with respect to an MTJ memory cell. It is a conceptual diagram which shows the relationship between the data write current in data writing, and the magnetization direction of a tunnel magnetoresistive element. It is a conceptual diagram explaining the data reading from an MTJ memory cell.

Explanation of symbols

  1 MRAM device, 5 control circuit, 10 memory array, 20, 21 row selection circuit, 25 column decoder, 80 word line driver, 85 write digit line driver, 86, 87 driver transistor, 90 transistor switch, 100 data read circuit, 105 Current supply transistor, 110 coupling capacitor, 120, 146 sense amplifier, 130 voltage holding capacitor, 140 feedback switch, 145 transistor switch, 146 sense amplifier, 148 latch circuit, 149 precharge transistor, 150 write digit line drive controller, 160 level Conversion circuit, 165 current supply transistor, 175 current limit control circuit, ADD address signal, ATR access transistor, BL bit line, CA code Address, DIO data line, DOUT output data, FL pinned magnetic layer, MC memory cell, N1, N2 sense input node, RA row address, RDT read data, Rd row decode signal, Rmax, Rmin Electric resistance value (memory cell) TB tunnel barrier, TMR tunnel magnetoresistive element, Vcc1, Vcc2 power supply voltage, Vpc, Vpc # precharge voltage, Vss fixed voltage, WDL write digit line, WL word line.

Claims (3)

A plurality of memory cells, each of which is magnetized along the easy magnetization axis in a direction corresponding to magnetically stored data and having an electrical resistance corresponding to the magnetization direction;
A data line electrically coupled to a fixed voltage via a selected memory cell selected as a data read target of the plurality of memory cells during data reading;
A current supply circuit for coupling the data line to a predetermined voltage at least during the data reading;
A magnetic field application unit for receiving a first power supply voltage and applying a data write magnetic field along the hard axis to the memory cell to be data written at the time of data writing;
A data read circuit that receives a second power supply voltage and the fixed voltage and generates read data corresponding to the data stored in the selected memory cell;
The thin film magnetic memory device, wherein a difference between the first power supply voltage and the fixed voltage is larger than a difference between the second power supply voltage and the fixed voltage. The magnetic field application unit is
Each of the plurality of memory cells is provided for each predetermined section of the plurality of memory cells, and selectively receives supply of current for applying a magnetic field in a direction along the hard axis to each of the corresponding memory cells. Current wiring,
A plurality of driver transistors provided corresponding to the plurality of current wires, each connected in series with a corresponding one of the plurality of current wires between the first power supply voltage and the fixed voltage; ,
A plurality of current wiring drive control units provided corresponding to the plurality of current wirings, respectively,
Each of the plurality of current line drive control units is configured to determine whether the corresponding current line corresponds to the selected memory cell in each of the data reading and writing based on the first control signal. A signal generation circuit for generating a second control signal for controlling on / off of a corresponding one of the plurality of driver transistors;
2. The thin film magnetic memory device according to claim 1, wherein the signal generation circuit has a level conversion function of making an amplitude of the second control signal larger than an amplitude of the first control signal. Each of the current wiring drive control units further includes an operating current control unit that controls an operating current of the signal generation circuit,
The thin film magnetic memory device according to claim 2, wherein the operating current control unit reduces the operating current at the time of reading data than at the time of writing data.

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