JP2009010359A - Nitride semiconductor element and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor element excellent in electric characteristics and reliability by coping with both of ohmic contact property and adhesiveness of metal electrodes formed on a silicon substrate, in the nitride semiconductor element employing the silicon substrate. <P>SOLUTION: The nitride semiconductor element includes the silicon substrate (2), the nitride semiconductor layer (10) formed on the silicon substrate (2) and the metal electrodes (8, 8') formed so as to be contacted with the silicon substrate (2). The metal electrodes (8, 8') are provided with first metal layers (4, 4') formed in the shape of islands separated so as to be contacted with the silicon substrate (2), and second metal layers (6, 6') formed while being contacted with the silicon substrate (2) exposed between the first metal layers (4, 4') so as to cover the first metal layers (4, 4'). The second metal layers (6, 6') are constituted of a metal, capable of being contacted with silicon through ohmic contact while the first metal layers (4, 4') are constituted of an alloy containing a metal different from the second metal layers (6, 6') and silicon. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor device using a silicon substrate and a manufacturing method thereof, and more particularly to a nitride semiconductor device including an electrode having excellent ohmic contact and adhesion to a silicon substrate and a manufacturing method thereof.

  Nitride semiconductor elements can emit high-output short-wavelength light, and are widely used as blue and green LEDs and white LEDs in combination with phosphors. In addition, nitride semiconductor elements have been actively studied in recent years as high-speed electronic devices such as HEMTs.

  A nitride semiconductor element is generally manufactured by heteroepitaxially growing a nitride semiconductor layer on a heterogeneous substrate such as sapphire because a GaN substrate for homoepitaxially growing a nitride semiconductor layer is expensive. However, even with a dissimilar substrate such as sapphire, it is difficult to obtain a large-diameter wafer, and the cost is not low. Moreover, since sapphire is insulative, an electrode cannot be formed on the back surface of the sapphire substrate, and bipolar electrodes must be formed on the same nitride semiconductor layer side. Therefore, it is difficult to make the current distribution in the nitride semiconductor device uniform.

Therefore, it has been studied to form a nitride semiconductor element on a silicon substrate which is conductive and can be formed with an electrode on the back surface, and a large-diameter wafer can be obtained at low cost.

  For example, Patent Document 1 discloses a nitrided structure in which a metal compound region mainly composed of gallium, indium and silicon and an aluminum nitride layer are formed on an n-type silicon substrate, and a nitride semiconductor device structure is formed thereon. A semiconductor device is disclosed. A cathode electrode obtained by vacuum-depositing titanium and aluminum is formed on the back surface of the n-type silicon substrate. An anode electrode obtained by vacuum-depositing nickel and gold is formed on the p side of the nitride semiconductor layer. It is also disclosed that instead of the cathode electrode of titanium and aluminum, an electrode in which titanium / gold germanium nickel alloy / gold is sequentially laminated is formed.

  Patent Document 2 discloses a nitride semiconductor element in which a group IIIB-containing layer is formed in advance on the surface of an n-type silicon substrate and a nitride semiconductor layer is formed thereon. A bonding electrode made of any of Al, Ti, Zr, Hf, V, or Nb is formed on the back surface of the n-type silicon substrate. A thin film transparent electrode made of Ta, Co, Rh, Ni, Pd, Pt, Cu, Ag or Au is formed on the p side of the nitride semiconductor layer, and a second bonding electrode is further formed. The

Further, in Patent Document 3, a nitride semiconductor layer grown on a heterogeneous substrate such as sapphire is bonded to a silicon substrate via a conductive bonding layer such as a eutectic layer, and then the heterogeneous substrate such as sapphire is bonded. A nitride semiconductor device formed by removal is disclosed.
JP 2002-208729 A Japanese Patent Laid-Open No. 2003-8061 JP 2005-108863 A

  However, when a nitride semiconductor element is configured using a silicon substrate as in Patent Documents 1 to 3, there is a problem that metal electrodes formed on the silicon substrate are easily peeled off in the element manufacturing process. That is, since the silicon substrate is conductive, it is possible to form a metal electrode on the back surface of the substrate, but the silicon substrate and the metal electrode must be in good ohmic contact. However, when a metal electrode is formed of a metal having good ohmic contact with the silicon substrate, the metal electrode may be peeled off from the silicon substrate during a nitride semiconductor element manufacturing process such as a dicing process. In a nitride semiconductor device, it is necessary to form a nitride semiconductor layer having a different thermal expansion coefficient and lattice constant on a silicon substrate. Therefore, compared to a normal silicon semiconductor device, the stress applied to the metal electrode formed on the silicon substrate is higher. growing. For this reason, it is estimated that peeling of the metal electrode is particularly likely to occur.

In particular, when a silicon substrate and a nitride semiconductor layer are bonded by bonding as in Patent Document 3, the growth is performed after bonding three layers having different thermal expansion coefficients, ie, a growth substrate, a nitride semiconductor layer, and a silicon substrate. Since the substrate is removed, the warpage of the silicon substrate during the manufacturing process is greatly changed, and the metal electrode is easily peeled off. Moreover, after joining a silicon substrate and a nitride semiconductor layer by a conductive joining layer as in Patent Document 3, annealing cannot be performed at a temperature exceeding the melting point of the conductive joining layer. For this reason, the metal electrode formed on the silicon substrate after the bonding needs to be a metal capable of ohmic contact without annealing at a high temperature, and the selection of the electrode material is limited. Therefore, it becomes more difficult to achieve both ohmic contact and adhesion of the metal electrode.

  Therefore, the present invention provides a nitride semiconductor device using a silicon substrate, which has both the ohmic contact property of the metal electrode formed on the silicon substrate and the adhesion to the substrate, and has excellent electrical characteristics and reliability. It aims at providing the manufacturing method.

  To achieve the above object, a nitride semiconductor device of the present invention includes a silicon substrate, a nitride semiconductor layer formed on the silicon substrate, and a metal electrode formed in contact with the silicon substrate. The metal electrode is in contact with the first metal layer formed in discrete island shapes in contact with the silicon substrate and the silicon substrate exposed between the islands of the first metal layer. A second metal layer formed to cover the first metal layer, wherein the second metal layer is made of a metal capable of ohmic contact with silicon, and the first metal layer is the second metal layer And an alloy containing silicon and different metals.

  According to the present invention, both the ohmic contact property and the mechanical stability can be obtained because the first metal layer can provide a high adhesion to the silicon substrate while ensuring good ohmic contact with the silicon substrate by the second metal layer. An excellent metal electrode can be easily obtained. That is, in the present invention, the second metal layer is made of a metal such as a platinum group that can satisfactorily make ohmic contact with silicon and does not have high adhesion to the silicon substrate. Good ohmic contact with the exposed surface of the silicon substrate. On the other hand, the first metal layer is made of an alloy containing silicon and a metal different from the second metal layer, and has high adhesion to the silicon substrate. Accordingly, by forming the first metal layer in an island shape on the silicon substrate, the first metal layer functions as an anchor for connecting the silicon substrate and the second metal layer, and ensures adhesion as the entire metal electrode. Can do.

  In the present invention, the “metal different from the second metal layer” means a metal different from the metal that is the main component of the second metal layer, and a metal contained in a small amount in the second metal layer is not excluded. In the present invention, “being a main component” refers to a case where the molar ratio of the component is 50% or more.

  The first metal layer is preferably made of an alloy containing a transition metal and silicon, and more preferably made of an alloy containing at least one selected from Ti, W, and Co and silicon. Since these silicon alloys exhibit high connection strength with respect to the silicon substrate, peeling of the metal electrode can be more effectively suppressed.

  The first metal layer is a layer for ensuring adhesion with the silicon substrate, and the ohmic contact with the silicon substrate is between the silicon substrate exposed between the first metal layers and the second metal layer. take. Accordingly, it is preferable that the island diameter of the first metal layer is 100 μm or less, whereby the ohmic contact region between the second metal layer and the silicon substrate is widened, and the contact resistance is further lowered. Further, the film thickness of the first metal layer is desirably 5 to 100 mm. With this thickness, the first metal layer can be formed into an island shape with a fine diameter by sputtering.

  When the silicon substrate is p-type, the second metal layer preferably contains at least one platinum group (Ru, Rh, Pd, Os, Ir, Pt) as a main component, and most preferably has Pt as a main component. Including. The platinum group metal can easily make ohmic contact with the p-type silicon substrate, and can make good ohmic contact even if the resistivity is high to some extent. In particular, Pt can make a good ohmic contact even if the resistivity of the p-type silicon substrate is 2 Ωcm or more. A white metal is also preferable in that ohmic contact is possible without performing high-temperature annealing if the resistivity of the p-type silicon substrate is low to some extent (for example, 0.5 Ωcm or less).

  In addition, it is preferable that the silicon substrate and the nitride semiconductor multilayer body are bonded using a conductive bonding layer, and thereby, the peeling prevention effect of the metal electrode according to the present invention becomes more important.

  In addition, a method for manufacturing a nitride semiconductor device according to the present invention includes a nitride semiconductor device including a silicon substrate, a nitride semiconductor layer provided on the silicon substrate, and a metal electrode formed in contact with the silicon substrate. In the manufacturing method, on the silicon substrate, the process of forming the first metal layer in discrete island shapes in contact with the silicon substrate, and the silicon substrate exposed from between the islands of the first metal layer Forming a second metal layer so as to cover and cover the first metal layer, wherein the second metal layer is made of a metal capable of ohmic contact with silicon, and the first metal The layer is made of an alloy containing a metal and silicon different from the second metal layer.

  According to this manufacturing method, on the silicon substrate, by forming a first metal layer having high adhesion to the silicon substrate, and subsequently forming a second metal layer having good ohmic contact with the silicon substrate, A metal electrode excellent in both ohmic contact and mechanical stability can be formed.

  As described above, according to the present invention, in a nitride semiconductor device using a silicon substrate, a nitride having excellent electrical characteristics and reliability, which achieves both ohmic contact and adhesion of a metal electrode formed on the silicon substrate. A semiconductor device and a manufacturing method thereof can be provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1A and 1B are a top view and a cross-sectional view showing a nitride semiconductor device according to the present embodiment. In the nitride semiconductor device 1 shown in FIGS. 1A and 1B, a metal electrode 8, a substrate-side adhesion layer 9, and a substrate-side barrier layer 11 are formed on a surface (first main surface) 22 of a substantially rectangular and conductive silicon substrate 2. The nitride semiconductor layer 10 is bonded via the conductive bonding layer 17, the semiconductor-side barrier layer 13, the semiconductor-side adhesion layer 15, and the p-electrode 12. A metal electrode 8 ′ is also formed on the back surface (second main surface) 24 of the silicon substrate 2. The p electrode 12 is ohmically connected to the p side of the nitride semiconductor layer 10 and can be electrically connected to the outside through the silicon substrate 2. An insulating protective film 14 is formed around the p-electrode 12. On the other hand, an n-electrode 16 is formed on the n-side of the nitride semiconductor layer 10 and is covered with the second insulating protective film 18 except for the pad portion 16a. The n electrode 16 can be electrically connected to the outside through a wire or the like connected to the pad portion 16a.

  The nitride semiconductor device 1 shown in FIGS. 1A and 1B uses a conductive silicon substrate 2 and is provided with a metal electrode 8 ′ on the back surface 24 of the silicon substrate 2. Can do. Further, since an inexpensive silicon substrate is used, the cost is low. Furthermore, since the silicon substrate 2 is originally a material that can be easily diced, and the metal electrodes 8 and 8 ′ are prevented from being peeled off during dicing, which has been a problem in the present embodiment, the silicon substrate 2 is manufactured with a high yield. Can do.

  FIG. 2 is a schematic diagram showing a portion of the metal electrode 8 on the silicon substrate 2. As shown in FIG. 2, the metal electrode 8 formed on the surface 22 of the silicon substrate 2 in the present embodiment covers the first metal layer 4 and the first metal layer 4 that are discretely formed in an island shape. And a second metal layer 6 formed in a planar shape on almost the entire surface of the silicon substrate 2. The second metal layer 6 is made of a metal that can satisfactorily make ohmic contact with silicon such as a platinum group, and is in ohmic contact with the surface 22 of the silicon substrate 2 exposed from the islands of the first metal layer 4 dispersed in an island shape. is doing. On the other hand, the first metal layer 4 is made of an alloy containing a metal different from the second metal layer 6 and silicon, and adheres to the silicon substrate 2 with high strength. The first metal layer 4 serves as an anchor for joining the silicon substrate 2 and the second metal layer 6 together. Therefore, according to the metal electrode 8 of the present embodiment, the second metal layer 6 is made of silicon by the anchor effect of the first metal layer 4 while ensuring good ohmic contact with the silicon substrate 2 by the second metal layer 6. Separation from the substrate 2 can be effectively prevented. The metal electrode 8 'formed on the back surface 24 of the silicon substrate 2 preferably has the same composition and structure as the metal electrode 8 on the front surface. The following description regarding the metal electrode 8 is also applicable to the metal electrode 8 '.

As shown in FIG. 3, when the metal electrode 8 having the first metal layer 4 and the second metal layer 6 is formed on the surface 22 of the silicon substrate 2, peeling of the metal electrode 8 can be suppressed during dicing (that is, This is preferable because the separation between the silicon substrate 2 and the nitride semiconductor 10 can be suppressed during dicing). It is also possible to establish ohmic contact between the surface 22 of the silicon substrate 2 and the metal electrode 8.
Similarly, when the metal electrode 8 ′ having the first metal layer 4 ′ and the second metal layer 6 ′ is formed on the back surface 24 of the silicon substrate 2 as shown in FIG. 4, the metal electrode 8 ′ is peeled off during dicing. Since it can suppress, it is preferable. Then, ohmic contact can be established between the surface 24 of the silicon substrate 2 and the metal electrode 8 ′.
Most preferably, the metal electrodes 8 and 8 'are formed on both the front surface 22 and the back surface 24 of the silicon substrate 2 as shown in FIG. Thereby, the metal electrodes 8 and 8 ′ excellent in ohmic contact and adhesion can be provided on both the front surface 22 and the back surface 24 of the silicon substrate 2.

  The first metal layer 4 is an alloy containing a metal different from the second metal layer 6 and silicon. Since the silicon alloy generally has high adhesion to silicon, the adhesion of the first metal layer 4 to the silicon substrate is high. In addition, silicon alloys have higher adhesion to metals that are excellent in ohmic contact with silicon such as the platinum group than silicon alone. Further, the second metal layer 6 embeds the periphery of the first metal layer 4 formed in an island shape, so that a mechanical bonding force is also generated between the first metal layer 4 and the second metal layer 6. Therefore, by forming the first metal layer 4 on the silicon substrate 2 in an island shape, the first metal layer 4 functions as an anchor that connects the silicon substrate 2 and the second metal layer 6, and peeling of the metal electrode 8 is effective. Can be suppressed.

Here, the “alloy including a metal different from the second metal layer and silicon” is not particularly limited as long as the silicon alloy can adhere to the silicon substrate 2 with high strength. However, the “metal different from the second metal layer” is preferably a transition metal, and more preferably one selected from the group consisting of Ti, Co, W, and Ni. Of these, Ti, Co and W are preferable, and Ti is most preferable. These silicon alloys exhibit high connection strength with respect to the silicon substrate 2. Moreover, it is preferable that the silicon content rate in the 1st metal layer 4 is 40-75 atom%. The connection strength with the silicon substrate 2 whose silicon content is lower than 40 atom% tends to decrease, and when the silicon content is higher than 75 atom%, the anchor effect that the first metal layer 4 exhibits with respect to the second metal layer 6 decreases. Tend to. The “alloy” in the present specification refers to a metal obtained by adding and dissolving another metal element or a non-metal element, and includes silicide. More preferably, the first metal layer 6 is silicide. Among these, TiSi ₂ is the most stable and preferable among the silicides.

  On the other hand, the second metal layer 6 is made of a metal capable of being in good ohmic contact with silicon. When the silicon substrate 2 is p-type, the second metal layer 6 is preferably a metal having a large work function. For example, the second metal layer 6 is desirably made of a platinum group (Ru, Rh, Pd, Os, Ir, Pt), and most preferably Pt. The platinum group metal can easily make ohmic contact with the p-type silicon substrate 2 and, for example, can make good ohmic contact even if the resistivity of the silicon substrate 2 is high to some extent. In particular, Pt can make a good ohmic contact even if the resistivity of the p-type silicon substrate 2 is 2 Ωcm or more. Further, if the metal is a white metal, ohmic contact is possible without performing high-temperature annealing if the resistivity of the p-type silicon substrate 2 is low to some extent. On the other hand, when the silicon substrate 2 is n-type, a metal containing Ti or Al as a main component, more preferably Ti or Al is desirable. In addition, the 2nd metal layer 6 should just be a metal with a favorable ohmic contact as a whole. For example, the platinum group metal may contain other metal elements to the extent that the ohmic contact is not hindered.

In addition, if the anchor effect by the 1st metal layer 4 is acquired, the 1st metal layer 4 and the 2nd metal layer 6 do not necessarily need to touch. For example, a third metal that can adhere to both of the first metal layer 4 and the second metal layer 6 may be interposed.

The metal electrode 8 can be formed as follows. First, the first metal layer 4 is grown on the silicon substrate 2 in an island-like discrete form. The first metal layer 4 can be formed in an island shape by patterning using photolithography, but it is preferably grown in an island shape using sputtering or vacuum deposition, and sputtering is particularly preferable. That is, in sputtering, island-shaped nuclei are generated as clusters in the early stage of growth, and when the growth is continued, the island-shaped clusters are connected to grow into a uniform film. Therefore, by stopping the sputtering before growing into a uniform film, it is possible to form the first metal layer 4 in the form of discrete islands having a fine diameter. Then, a second metal layer 6 is formed so as to cover the first metal layer 4 formed in an island shape. The second metal layer 6 can be formed by a usual method such as sputtering or vacuum deposition. As a result, the metal electrode 8 is formed on the silicon substrate 2.

The first metal layer 4 is a layer for ensuring adhesion to the silicon substrate 2, and the ohmic contact with the silicon substrate 2 is exposed between the first metal layers 4 and the second metal layer. Take between 6. Therefore, it is preferable that the island diameter of the first metal layer 4 is 100 mm or less, whereby the ohmic contact region between the second metal layer 6 and the silicon substrate 2 is widened, and the contact resistance is further reduced. Moreover, it is preferable that the average pitch at which the islands of the first metal layer 4 are arranged is equal to or larger than the average particle diameter of the islands. The film thickness of the first metal layer 4 is preferably 5 to 100 mm, more preferably 10 to 50 mm. With this thickness, the first metal layer 4 can be formed in a fine-pitch island shape with a fine diameter using sputtering cluster formation. On the other hand, the second metal layer 6 is formed so as to completely cover at least the first metal layer. The film thickness of the second metal layer 6 is desirably 2000 to 5000 mm, more preferably 2500 to 3000 mm.

The first metal layer 4 made of a silicon alloy is preferably formed by sputtering using a silicon alloy having a target composition as a target. As a result, the density of the silicon substrate 2 is kept constant even in the vicinity of the interface with the metal electrode 8. That is, for example, when a silicon alloy having a composition of TiSi ₂ is formed as the first metal layer 4, Ti can be formed into an island shape and then annealed to form TiSi ₂ . However, in that case, silicon in the silicon substrate 2 is consumed and a silicon alloy is formed, so that the density of the silicon substrate 2 decreases near the interface with the first metal layer 4. On the other hand, for example, if the first metal layer 4 is formed by sputtering using TiSi ₂ as a target, the density of the silicon substrate 2 is kept constant even in the vicinity of the interface with the metal electrode 8. If the density of the silicon substrate 2 is constant even in the vicinity of the interface with the metal electrode 8, it is preferable because the ohmic contact and adhesion between the silicon substrate 2 and the metal electrode 8 become better.

(Manufacturing method of nitride semiconductor device 1)
Next, a method for manufacturing the nitride semiconductor device 1 will be described with reference to FIGS. For simplification of the drawings, the patterns of the p-electrode 12 and the n-electrode 16 are simplified in FIGS.

  As shown in FIG. 5A, a nitride semiconductor layer 10 is formed on the surface of a growth substrate 20 such as sapphire. The nitride semiconductor layer 10 is formed by stacking a plurality of n-type and p-type nitride semiconductor layers in order to realize an appropriate device structure. From the standpoint of crystallinity, it is preferable to grow the n-type nitride semiconductor layer first and form the p-type nitride semiconductor layer later. For example, in the case of a nitride semiconductor light emitting device, it includes a buffer layer, a high temperature growth layer, an n-type cladding layer, an active layer, a p-type cladding layer, a p-type contact layer, and the like.

Next, as shown in FIG. 5B, the p-electrode 12 is formed so as to make ohmic contact with the p-side surface of the nitride semiconductor layer 10. For the p-electrode 12, for example, Rh can be used. Then, an insulating protective film 14 such as SiO ₂ is formed around the p-electrode 12 and the semiconductor side adhesion layer 15 such as Ti and the semiconductor side such as Pt are sequentially formed from the nitride semiconductor layer 10 side so as to cover the entire surface of the element. The barrier layer 13 and the first conductive bonding layer 17a are formed. The first conductive bonding layer 17a includes a metal having a relatively low melting point such as Sn or In as a main composition. Here, it is also preferable to form a layer (not shown) of Au or the like at the interface serving as the exposed surface of the first conductive bonding layer 17a and / or the interface with the semiconductor-side barrier layer 13. The Au layer has an effect of protecting the first conductive bonding layer 17a and improving the bonding.

Next, as shown in FIG. 5C, a p-type (or n-type) silicon substrate 2 is prepared, and a first metal layer 4 made of a silicon alloy such as TiSi ₂ is grown on the silicon substrate 2 in an island-like form. Let The first metal layer 4 is preferably grown by sputtering using a target of a target silicon alloy. That is, by stopping the sputtering before growing into a uniform film, it is possible to form the first metal layer 4 in the form of islands.

Next, as shown in FIG. 5D, a second metal layer 6 made of Pt or the like is formed so as to cover the first metal layer 4 formed in an island shape. The second metal layer 6 can be formed by a usual method such as sputtering or vacuum deposition. As a result, the metal electrode 8 is formed on the silicon substrate 2.

Next, as shown in FIG. 5E, a substrate side adhesion layer 9, a substrate side barrier layer 11, and a second conductive bonding layer 17b are further formed on the metal electrode 8 of the silicon substrate 2, and the silicon substrate 2 is turned upside down. To do. The second conductive bonding layer 17b is made of Pd, Au or the like, can be formed into a eutectic with the first conductive bonding layer 17a, and contains a metal having a melting point higher than that of the first conductive bonding layer 17a as a main composition. Then, the silicon substrate 2 is laminated on the nitride semiconductor layer 10 so that the first conductive bonding layer 17a and the second conductive bonding layer 17b are opposed to each other, and is heated and pressed. The substrate-side adhesion layer 9 and the substrate-side barrier layer 11 are not always necessary and may be omitted. Further, it is preferable that the first conductive bonding layer 17a and the second conductive bonding layer 17b have a good wettability with each other and are a combination of mutually diffusing materials. For example, Au and Sn, Sn and Pd, Ag and Sn, etc. have a good wettability with each other and are a combination of mutual diffusion. Therefore, for example, the first conductive bonding layer 17a can be made of an Au—Sn alloy, and the second conductive bonding layer 17b can be made of Au or Pd.

  As shown in FIG. 5F, when heat-welded, the first conductive bonding layer 17a and the second conductive bonding layer 17b diffuse to each other to form the conductive bonding layer 17, and the silicon substrate 2 and the nitride semiconductor layer 10 are joined.

  Then, as shown in FIG. 5G, the device is turned upside down so that the silicon substrate 2 is on the lower side and placed in a polishing machine, and the growth substrate 20 is lapped. At this time, the buffer layer and the underlying layer in the nitride semiconductor layer 10 can be removed together with the growth substrate 2.

Next, as shown in FIG. 5H, after polishing the n-side surface of the nitride semiconductor layer 10, an n-electrode 16 such as Ti / Al / Ni / Au is formed, and the second insulation protection is left leaving the pad portion. Cover with film 18. Next, a first metal layer 4 ′ such as TiSi ₂ is formed in an island shape on the back surface 24 of the silicon substrate 2, and a second metal layer 6 ′ such as Pt is formed so as to cover the first metal layer 4 ′. Thus, the metal electrode 8 ′ is formed. At this time, if a high temperature exceeding the melting point of the conductive bonding layer 17 is applied to the nitride semiconductor element, the silicon substrate 2 is peeled off from the nitride semiconductor layer 10. The metal electrode 8 ′ of this embodiment can take ohmic contact without annealing at a high temperature, for example, if the second metal layer 6 is Pt or the like. The metal electrode 8 ′ having a good ohmic contact can be formed without causing it.

  Note that the back surface 24 of the silicon substrate 2 may be polished before forming the first metal layer 4 ′ and the second metal layer 6 ′ on the back surface 24 of the silicon substrate 2. Thereby, the silicon substrate 2 becomes thin, and a thin nitride semiconductor element can be obtained. In particular, it is preferable that the thickness of the silicon substrate 2 is 50 μm to 250 μm because a thin nitride semiconductor element can be obtained while ensuring a thickness necessary to function as a substrate for the nitride semiconductor element 2.

  In order to thin the silicon substrate 2, it is preferable to polish the back surface 24 of the silicon substrate 2 after the nitride semiconductor layer 10 is bonded to the silicon substrate 2. Since the thin silicon substrate 2 has low strength, it is not desirable to polish the silicon substrate 2 before bonding the nitride semiconductor layer 10 because the silicon substrate 2 may be damaged. Furthermore, if the silicon substrate is thinned before bonding and bonded to the nitride semiconductor layer, even if bonded, the silicon substrate is damaged due to the difference in thermal expansion coefficient between the silicon substrate and the nitride semiconductor layer. This is undesirable. In particular, when the thickness of the silicon substrate 2 is reduced to 250 μm or less, the possibility of breakage due to these increases. Therefore, if the back surface 24 of the silicon substrate 2 is polished after the silicon substrate 2 is bonded to the nitride semiconductor layer 10, the silicon substrate 2 can be thinned without damaging the silicon substrate 2.

  As shown in the flowchart of FIG. 6, when the back surface 24 of the silicon substrate 2 is polished, the metal electrode 8 'on the back surface 24 must be formed after the polishing step S20. That is, after the step S10 for bonding the silicon substrate 2 and the nitride semiconductor layer 10, the step of forming the metal electrode 8 (step S30 for forming the first metal layer 4 ′ and the second metal layer 6 ′ are performed. It is necessary to perform the forming step S40). The metal electrode 8 'of the present embodiment can make ohmic contact without annealing at a high temperature. Therefore, even if the metal electrode 8 ′ is provided after the silicon substrate 2 and the nitride semiconductor layer 10 are joined, the ohmic contact is good without causing separation between the silicon substrate 2 and the nitride semiconductor layer 10. A metal electrode 8 'can be formed.

Then, the light emitting element is separated into chips by dicing. As a result, a nitride semiconductor element having a structure in which the nitride semiconductor layer 10 is stacked on the silicon substrate 2 and the n-electrode 16 and the p-electrode 12 sandwich the nitride semiconductor layer 10 from above and below can be obtained. At this time, the metal electrodes 8 and 8 ′ of the silicon substrate 2 are subjected to a force that causes peeling, such as stress and impact. However, since the metal electrodes 8 and 8 ′ of the present embodiment have excellent adhesion, Peeling is effectively prevented.

  Next, the structure and manufacturing process of main parts of the nitride semiconductor device of the present embodiment will be described in more detail.

(Silicon substrate 2)
The silicon substrate 2 bonded to the nitride semiconductor layer 10 may be either p-type or n-type. The conductivity of the silicon substrate 2 is preferably 0.002 to 3 Ωcm. When the conductivity (and impurity concentration) of the silicon substrate 2 is within the above range, the metal electrodes 8 and 8 'can easily be brought into ohmic contact, and the nitride semiconductor device can be made to have a low Vf. Note that the p-type silicon substrate becomes p-type by, for example, B doping, and can be produced by a low-cost CZ method. Also, the resistivity of the p-type silicon substrate is easier to control than the n-type silicon substrate.

(Substrate side adhesion layer 9, semiconductor side adhesion layer 15)
Adhesion layers such as the substrate-side adhesion layer 9 and the semiconductor-side adhesion layer 15 are layers for ensuring high adhesion between the base layer and any one of Ti, Ni, W and Mo. It is preferable to include. The thickness of the adhesion layer is preferably 50 to 500 nm.

(Substrate side barrier layer 11, semiconductor side barrier layer 13)
The barrier layers such as the substrate-side barrier layer 11 and the semiconductor-side barrier layer 13 are layers that prevent the metal in the conductive bonding layer 17 from diffusing, and are platinum group (Ru, Rh, Pd, Os, Ir, Pt ), Ti, Ni, W and the like are preferable. Among the platinum group, Pt, Pd, and Rh are preferable, and Pt or Pd is particularly preferable. The most preferred composition is Pd. For the barrier layer, the material mixed with the conductive bonding layer 17 may be selected to prevent diffusion, or the material not mixed may be selected to prevent diffusion. Examples of the former are platinum group, Ti and Ni, and examples of the latter are W. The thickness of the barrier layer is preferably 100 to 1000 nm. Note that the adhesion layer and / or the barrier layer may be omitted depending on the configuration of the nitride semiconductor element.

(First conductive bonding layer 17a)
The first conductive bonding layer 17a is a layer containing a metal having a relatively low melting point as a main composition. The melting point is preferably 300 ° C. or lower, and is preferably a metal that can form a eutectic with the second conductive bonding layer 17b described later. For example, Sn or In is preferable, and Sn is more preferable. The film thickness of the first conductive bonding layer 17a is preferably 1000 to 3000 nm.

(Au layer (not shown))
Further, in order to prevent oxidation of the first conductive bonding layer 17a, the first conductive bonding layer 17a has a higher melting point than the first conductive bonding layer 17a and lower than the second conductive bonding layer 17b. It is preferable to form a metal having a melting point, such as an Au layer. This Au layer may also be formed between the semiconductor-side barrier layer 13 and the first conductive bonding layer 17a in order to further prevent the first conductive bonding layer 17a from diffusing into the semiconductor-side adhesion layer 15 and the like. preferable.

(Second conductive bonding layer 17b)
The second conductive bonding layer 17b is a layer containing a metal having a relatively high melting point as a main composition. As the second conductive bonding layer 17b, a metal that can form a eutectic with the first conductive bonding layer 17a and has a higher melting point than the first conductive bonding layer 17a is selected. For example, the second conductive bonding layer 17b is preferably Pd or Au, and more preferably Pd. The film thickness of the second conductive bonding layer 17b is desirably 500 nm or less, more preferably 350 nm or less.

  In the present embodiment, the example in which the first conductive bonding layer 17a is formed on the nitride semiconductor layer 10 side and the second conductive bonding layer 17b is formed on the silicon substrate 2 side has been described. It doesn't matter. Even in that case, the above-described matters can be applied as they are when the nitride semiconductor layer and the silicon substrate are interchanged.

(Nitride semiconductor layer 10)
The nitride semiconductor layer 10 is a layer made of a nitride semiconductor represented by a general formula Al _a In _b Ga _1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, a + b ≦ 1). Depending on the type of element, various structures can be taken. For example, in the case of a nitride semiconductor light emitting device, at least one p-type nitride semiconductor layer and Al _a In _b Ga _1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, at least comprising a quantum well structure and a + b ≦ 1 well layer made of) and _{Al c In d Ga 1-c} -d N (0 ≦ c ≦ 1,0 ≦ d ≦ 1, c + d ≦ 1) consisting of a barrier layer It is preferable to have an active layer and one or more n-type nitride semiconductor layers.

(P electrode 12)
P electrode 12 is preferably in ohmic contact with the p-type nitride semiconductor layer and has a high reflectance. The p-electrode 12 is preferably made of a metal material containing at least one selected from the group consisting of Ag, Rh, Ni, Au, Pd, Ir, Ti, Pt, W, and Al. More preferably, any of Rh, Ag, nickel gold, Ni / Au / RhO and Rh / Ir, more preferably Rh can be used. Here, since the p-electrode 12 is formed on the p-type nitride semiconductor layer having a higher resistivity than the n-type nitride semiconductor layer, the p-electrode 12 is preferably formed on almost the entire p-side of the nitride semiconductor layer 10. The thickness of the p electrode 12 is preferably 0.05 to 0.5 μm.

The p electrode 12 in contact with the nitride semiconductor 10 is provided with an opening, and an insulating protective film 14 is formed in the opening. As the material of the insulating protective film 14, a single layer film or a multilayer film such as SiO ₂ , Al ₂ O ₃ , ZrO ₂ , or TiO ₂ can be used. By providing the insulating protective film 14, a short circuit or the like can be prevented, and yield and reliability can be improved. The insulating protective film 14 may have a two-layer structure with a reflective film (not shown). For example, by forming a reflective film (not shown) of Al, Ag, Rh, etc. with a film thickness of 500 mm or more and 2000 mm or less on the side of the insulating protective film 14 that is not in contact with the nitride semiconductor 10, The propagating light can be extracted efficiently. The reflective film may be on the silicon substrate 2 side or on the nitride semiconductor 10 side.

(N electrode 16)
The n electrode 16 formed on the n side of the nitride semiconductor layer 10 can be a multilayer electrode of Ti / Al / Ni / Au or W / Al / W / Pt / Au. The thickness of the n electrode 16 is preferably 0.1 to 1.5 μm. In addition, it is preferable to provide an insulating second insulating protective film 18 such as SiO ₂ , Al ₂ O ₃ , ZrO ₂ , or TiO ₂ so as to cover the exposed surface other than the n-electrode.

As shown in FIGS. 1A and 1B, the n-electrode 16 has a pad portion 16a at a corner on the diagonal line of the chip, and spreads in a mesh shape between the pad portions 16a. By forming the n-electrode 16 in the form of a mesh, a lattice, or the like over almost the entire surface of the light emission range, a current can be supplied uniformly to the nitride semiconductor layer 10. The pad portion 16a is not limited to two diagonal positions, and may be formed at all four corners. The p electrode 12 and the n electrode 16 are preferably disposed so as to face each other so that they do not overlap each other when viewed from the stacking direction of the nitride semiconductor layer 10. Thereby, the emitted light can be taken out efficiently without being blocked by the n-electrode 16.

(Growth substrate 20)
The growth substrate for growing the nitride semiconductor layer 10 includes sapphire, spinel (insulating substrate such as MgAl ₂ O ₄ ), SiC, main surface of any one of the C-plane, R-plane and A-plane. Examples thereof include an oxide substrate lattice-matched with Si and a nitride semiconductor. Sapphire and spinel are preferred.

(Step of removing the growth substrate 20)
Further, in order to remove the growth substrate 20 after bonding the silicon substrate 2, polishing, etching, electromagnetic wave irradiation, or a combination of these methods can be used. In the case of performing electromagnetic wave irradiation, for example, a laser is used for electromagnetic waves, and after the silicon substrate 2 is bonded, the entire surface of the growth substrate 20 on which the underlayer is not formed is irradiated with laser to decompose the underlayer. The substrate and the base layer can be removed. The removal by electromagnetic wave irradiation simplifies the work process and improves the yield as compared with the polishing method. Further, after removing the growth substrate and the underlying layer, the exposed surface of the nitride semiconductor layer is subjected to CMP to expose a desired film. Thereby, removal of a damage layer and adjustment of the thickness and surface roughness of a nitride semiconductor layer can be performed.

  In addition, after removing the growth substrate 20, in order to improve the light extraction efficiency, the exposed surface of the nitride semiconductor layer 10 may be formed with irregularities (dimple processing) by RIE. The unevenness (dimple processing) forming portion is on the light extraction side of the nitride semiconductor. Light that does not come out by total reflection due to the formation of irregularities on the surface can be extracted by changing the angle of light on the irregular surface. In other words, by diffusely reflecting the emitted light at the concavo-convex portion, the light that has been totally reflected in the prior art can be guided upward and taken out of the element. This unevenness formation can be expected to improve the output by 1.5 times or more compared to the case without unevenness. The planar shape of the irregularities is preferably a round shape, or a hexagonal or triangular polygonal shape. Further, the uneven planar shape may be formed in a stripe shape, a lattice shape, a rectangle, or the like.

(Phosphor)
When the nitride semiconductor element is a light emitting element, by forming a coating layer or a sealing member containing a fluorescent material that absorbs part or all of the light from the active layer and emits light of a different wavelength, It can emit light of various wavelengths. As the phosphor, one that absorbs a part of the light emitted from the active layer and converts it to a long wavelength and enables white light emission together with the light emission from the active layer is preferable.

In this embodiment, the case where the nitride semiconductor multilayer body is bonded to the silicon substrate has been described as an example, but the present invention is not limited to this. For example, a nitride semiconductor stacked body may be directly grown on a silicon substrate, and the substrate-side electrode described in this specification may be formed on the back surface of the silicon substrate.

  In this example, the present invention is applied to a light emitting diode having an emission wavelength of 375 nm, and a nitride semiconductor device having the structure shown in FIGS. 1A and 1B is produced according to the manufacturing method shown in FIGS.

(Growth substrate)
A substrate made of sapphire (C surface) was used as the growth substrate 20, and the surface was cleaned in a MOCVD reaction vessel at 1050 ° C. in a hydrogen atmosphere.

(Underlayer)
Buffer layer: Subsequently, a buffer layer made of GaN was grown to a thickness of about 200 mm on the substrate using ammonia and TMG (trimethylgallium) at 510 ° C. in a hydrogen atmosphere.
High temperature growth layer: After growing the buffer layer, only TMG is stopped, the temperature is increased to 1050 ° C., and when it reaches 1050 ° C., TMG and ammonia are used as source gases, and a high temperature growth nitride semiconductor 4 made of undoped GaN is formed The film was grown with a film thickness of 5 μm.

(N-type cladding layer and n-type contact layer)
Next, an n-type cladding layer made of n-type Al _0.18 Ga _0.82 N doped with Si at 5 × 10 ¹⁷ / cm ³ using TMG, TMA, ammonia, and silane at 1050 ° C. with a thickness of 400 mm. Formed.

(Active layer 6)
Next, the temperature is set to 800 ° C., TMI (trimethylindium), TMG, and TMA are used as source gases, a barrier layer made of Si-doped Al _0.1 Ga _0.9 N, and an undoped In _{0. A} well layer made of ₀₃ Al _0.02 Ga _0.95 N was laminated in the order of barrier layer (1) / well layer (1) / barrier layer (2) / well layer (2) / barrier layer (3). At this time, the barrier layer (1) was formed in a thickness of 200 mm, the barrier layers (2) and (3) in a thickness of 40 mm, and the well layers (1) and (2) in a thickness of 70 mm. The active layer has a multiple quantum well structure (MQW) with a total film thickness of about 420 mm.

(P-type cladding layer)
Next, from Al _0.2 Ga _0.8 N doped with 1 × 10 ²⁰ / cm ^{3 of} Mg using TMG, TMA, ammonia, Cp ₂ Mg (cyclopentadienyl magnesium) at 1050 ° C. in a hydrogen atmosphere. The resulting p-type cladding layer 7 was grown to a thickness of 600 mm.

(P-type contact layer)
Subsequently, the first p-type made of Al _0.04 Ga _0.96 N doped with 1 × 10 ¹⁹ / cm ^{3 of} Mg using TMG, TMA, ammonia, Cp ₂ Mg on the p-type cladding layer. A contact layer is grown to a thickness of 0.1 μm, and then a second p-type contact made of Al _0.01 Ga _0.99 N doped with 2 × 10 ²¹ / cm ^{3 of} Mg by adjusting the gas flow rate. The layer was grown to a thickness of 0.02 μm.

  After completion of the growth, the wafer was annealed in a reaction vessel at 700 ° C. in a nitrogen atmosphere to further reduce the resistance of the p-type cladding layer and the p-type contact layer.

(P electrode 12)
After annealing, the wafer was taken out of the reaction vessel, and an Rh film having a thickness of 2000 mm was formed on the p-type contact layer to form a p-electrode 12. Thereafter, ohmic annealing was performed at 600 ° C., and then SiO ₂ was formed as an insulating protective film 14 with a film thickness of 0.3 μm on the exposed surface other than the p-electrode 12.

(Semiconductor-side adhesion layer 15, semiconductor-side barrier layer 13, first conductive bonding layer 17a)
Next, a multilayer film of Ti / Pt / Au / Sn / Au was formed on the p electrode at a film thickness of 100 nm / 500 nm / 300 nm / 3000 nm / 100 nm. Here, Ti is the semiconductor-side adhesion layer 15, Pt is the semiconductor-side barrier layer 13, Sn is the first conductive bonding layer 17a, and the Au layer between Pt and Sn is diffused into the barrier layer 44. The outermost Au layer plays a role of improving the adhesion with the second conductive bonding layer.

(Silicon substrate 2)
On the other hand, as the conductive silicon substrate 2, a p-type silicon substrate having a film thickness of 400 μm, doped with boron, and having a resistance of 3 Ωcm or less was used. The silicon substrate 2 is immersed in an organic solvent such as acetone to remove organic substances on the surface, and further immersed in an HF aqueous solution to remove a natural oxide film formed on the surface, thereby cleaning the surface 22 of the silicon substrate 2. To do. Then, sputtering was performed on the surface 22 of the silicon substrate 2 using TiSi ₂ as a target, and the sputtering was stopped when the film thickness reached 30 mm in terms of the growth rate. Thereby, the first metal layer 4 made of island-like TiSi ₂ was formed. Sputtering was performed thereon using Pt as a target to form a second metal layer 6 made of Pt having a thickness of 2500 mm. As a result, the metal electrode 8 was formed on the silicon substrate 2. A second conductive bonding layer 17b made of Pd was formed thereon with a thickness of 350 nm.

  Next, in a state where the first conductive bonding layer 17a and the second conductive bonding layer 17b are opposed to each other, the heater temperature is press-pressed at 250 ° C. and heat-pressed. As a result, the first conductive bonding layer 17a and the second conductive bonding layer 17b were diffused to form the conductive bonding layer 17.

(Removal of growth substrate 20)
Next, after removing the sapphire substrate 1 by grinding, the exposed buffer layer and the high-temperature growth layer were polished and further polished until the n-type cladding layer was exposed to eliminate surface roughness.

(N electrode 16)
Next, a multilayer electrode made of Ti / Pt / Au was formed on the n-type clad layer functioning also as an n-type contact with a film thickness of 5 nm / 100 nm / 1800 nm to form an n-electrode 16. Then, after polishing the silicon substrate 2 to 100 μm, an island-shaped first metal layer 4 ′ made of TiSi ₂ and a second metal layer 6 ′ made of Pt are formed on the back surface 24 of the silicon substrate 2 with a film thickness of 2500 mm. 2 was formed in the same manner as the front side 22 of FIG. 2 to form a metal electrode 8 ′, and an Au layer was further formed with a thickness of 5000 mm. Next, the element was separated by dicing.

  The obtained nitride semiconductor device was remarkably excellent in the adhesion between the silicon substrate 2 and the metal electrodes 8 and 8 '.

The adhesion strength between the silicon substrate and the metal electrodes 8, 8 ′ can be evaluated by, for example, an improved edge lift-off test (mELT method) proposed by Kobelco Research Institute, Inc. The improved edge lift-off test is a method in which an epoxy resin is applied to a measurement sample and baked, the sample is cut into 10 mm square, cooled with liquid nitrogen, and the adhesion is measured from the temperature at which the film is peeled off. That is, the peel strength K _app [MPa · m ^1/2 ] is calculated from the following equation based on the peel temperature T, the residual stress σ of the epoxy resin, and the film thickness h of the epoxy resin.
Kapp = σ · (h / 2) ^1/2
Here, the residual stress σ of the epoxy resin at the temperature T can be calculated from the following equation based on Cf, m, and c of the epoxy resin.
σ = C _f T ² -mT-c

TiSi ₂ , Pt layer 1200 Å, Au layer 1200 Å, and Ti layer 100 Å (in order to improve adhesion to the epoxy resin) are formed on the silicon substrate in the same manner as in Example 1, and the thickness of TiSi ₂ is changed from 0 Å. The peel strength Kapp was measured by changing it between 100 mm. As a result, the peel strength of the sample in which TiSi ₂ was not formed (film thickness 0 mm) was about 0.15 [MPa · m ^1/2 ], whereas TiSi ₂ was formed in a film thickness of 10 to 100 mm. In all the samples, the peel strength Kapp was about 0.3 [MPa · m ^1/2 ], and the peel strength was improved about twice.

In Example 1, the exception that the first metal layer to NiSi ₂ to form a nitride semiconductor device in the same manner. Similar to Example 1, a nitride semiconductor device having a remarkably excellent adhesion between the silicon substrate and the metal electrodes 8, 8 ′ can be obtained.

  In Example 1, a nitride semiconductor device is formed in the same manner as in Example 1 except that the p-type silicon substrate is changed to an n-type silicon substrate and the second metal layer 6 is changed to Ti. Similar to the first embodiment, a nitride semiconductor device having a remarkably excellent adhesion between the silicon substrate and the metal electrodes 8, 8 'can be obtained.

  In Example 4, an element is formed by the process as shown in FIG. Similar to Example 1, the back surface 24 of the silicon substrate 2 is polished to reduce the thickness of the silicon substrate 2 from 400 μm to 100 μm. In this embodiment, a process of polishing the back surface 24 is further added thereafter. Then, after the polishing process, a metal electrode 8 'is formed. Compared with the first embodiment, a nitride semiconductor device in which the adhesion between the back surface 25 of the silicon substrate 2 and the metal electrode 8 ′ is further improved can be obtained.

(Comparative Example 1)
When a continuous TiSi ₂ layer is formed with a thickness of 100 mm on the front and back surfaces of the silicon substrate with a thickness of 100 mm and a Pt film is formed with a thickness of 1200 mm, no ohmic contact is obtained between the silicon substrate and the TiSi ₂ layer. It was. Therefore, the following elements are created. In Example 1, the metal electrodes 8 and 8 ′ are changed to produce a comparative nitride semiconductor element. In this comparative example, instead of forming the island-shaped first metal layers 4, 4 ′ on the front surface 22 and the back surface 24 of the silicon substrate 2, a continuous TiSi ₂ layer is formed with a thickness of 100 mm. Then, instead of the second metal layers 6 and 6 ', a Pt film is formed with a thickness of 1200 mm. Since the Pt film is formed on the TiSi ₂ layer, it is not in direct contact with the silicon substrate 2.
Since the obtained comparative device cannot obtain ohmic contact between the silicon substrate 2 and the TiSi ₂ layer, its driving voltage is very high as compared with the device of Example 1. Even when one of the metal electrode 8 on the front surface 22 side and the metal electrode 8 'on the back surface 24 side of the silicon substrate 2 is changed to an electrode having a TiSi ₂ layer and a Pt film configuration, the drive power of the element Becomes higher.

(Comparative Example 2)
In Example 1, the metal electrode 8 ′ is changed to produce a comparative nitride semiconductor element. In this comparative example, instead of forming the island-shaped first metal layer 4 ′ on the back surface 24 of the silicon substrate 2, a continuous Ti layer is formed with a thickness of 100 mm. Thereafter, the silicon substrate 2 is annealed at 600 degrees to form a TiSi ₂ layer having a thickness of 200 mm from the Ti layer. Then, instead of the second metal layer 6 ′, a Pt film is formed with a thickness of 1200 mm. Since the Pt film is formed on the TiSi ₂ layer, it is not in direct contact with the silicon substrate 2.
When this method is used, peeling occurs in the vicinity of the first conductive bonding layer 17a and the second conductive bonding layer 17b disposed between the silicon substrate 2 and the nitride semiconductor layer 10 at the time of annealing. The silicon substrate is peeled off from the nitride semiconductor layer, and an element cannot be obtained. Moreover, even if it does not peel off at the time of annealing, the same part will peel off in the dicing process at the time of elementization, and an element will not be obtained.

FIG. 1A is a plan view showing an example of a nitride semiconductor device according to the present invention. 1B is a cross-sectional view taken along the B-B ′ cross section of the nitride semiconductor device shown in FIG. 1A. FIG. 2 is a schematic diagram showing a silicon substrate and metal electrodes. FIG. 3 is a cross-sectional view showing a first modification of the nitride semiconductor device. FIG. 4 is a cross-sectional view showing a second modification of the nitride semiconductor device. FIG. 5A is a cross-sectional view showing a part of the manufacturing process of the nitride semiconductor device. FIG. 5B is a cross-sectional view showing a step subsequent to FIG. 5A. FIG. 5C is a cross-sectional view showing a step subsequent to FIG. 5B. FIG. 5D is a cross-sectional view showing a step subsequent to FIG. 5C. FIG. 5E is a cross-sectional view showing a step subsequent to FIG. 5D. FIG. 5F is a cross-sectional view showing a step subsequent to FIG. 5E. FIG. 5G is a cross-sectional view showing a step subsequent to FIG. 5F. FIG. 5H is a cross-sectional view showing a step subsequent to FIG. 5G. FIG. 6 is a flowchart for explaining a part of the manufacturing process of the nitride semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Nitride semiconductor element 2 Silicon substrate 4, 4 '1st metal layer 6, 6' 2nd metal layer 8, 8 'Metal electrode 10 Nitride semiconductor layer 12 P electrode 14 Insulating protective film 16 N electrode 17 Conductive junction layer 18 Second insulating protective film 20 Growth substrate 22 First main surface (surface) of silicon substrate
24 Second main surface (back surface) of silicon substrate

Claims (20)

A nitride semiconductor device comprising a silicon substrate, a nitride semiconductor layer formed on the silicon substrate, and a metal electrode formed in contact with the silicon substrate,
The metal electrode is in contact with the silicon substrate and covers the first metal layer formed in discrete island shapes and in contact with the silicon substrate exposed from between the islands of the first metal layer. A second metal layer formed as described above,
The nitride semiconductor device, wherein the second metal layer is made of a metal capable of ohmic contact with silicon, and the first metal layer is made of an alloy containing a metal different from the second metal layer and silicon.   The nitride semiconductor device according to claim 1, wherein the first metal layer is made of an alloy containing a transition metal and silicon. 3. The nitride semiconductor device according to claim 1, wherein the first metal layer is made of an alloy containing at least one selected from Ti, W, Co, and Ni and silicon.   The nitride semiconductor device according to any one of claims 1 to 3, wherein the first metal layer has an average particle size of islands of 100 mm or less.   5. The nitride semiconductor device according to claim 1, wherein a film thickness of the first metal layer is 5 to 100 mm.   6. The nitride semiconductor device according to claim 1, wherein the silicon substrate is p-type, and the second metal layer includes at least one platinum group as a main component.   The nitride semiconductor device according to claim 6, wherein the second metal layer contains Pt as a main component.   6. The nitride semiconductor device according to claim 1, wherein the silicon substrate is n-type, and the second metal layer contains Ti or Al as a main component.   The nitride semiconductor device according to claim 1, wherein the silicon substrate and the nitride semiconductor multilayer body are bonded using a conductive bonding layer.   The nitriding according to any one of claims 1 to 9, wherein the metal electrode is formed on a first main surface of the silicon substrate, and the nitride semiconductor layer is formed on the metal electrode. Semiconductor device.   The metal electrode is formed on a second main surface of the silicon substrate, and the nitride semiconductor layer is formed on a first main surface opposite to the second main surface. Item 11. The nitride semiconductor device according to any one of Items 1 to 10.   The nitride semiconductor device according to claim 1, wherein the silicon substrate has a thickness of 50 μm to 250 μm. A method for manufacturing a nitride semiconductor device comprising a silicon substrate, a nitride semiconductor layer on the silicon substrate, and a metal electrode formed in contact with the silicon substrate,
Forming a first metal layer in discrete islands on the silicon substrate and contacting the silicon substrate exposed between the islands of the first metal layer; Forming a second metal layer so as to cover the layer, and including a metal electrode forming step,
The second metal layer is made of a metal capable of ohmic contact with silicon, and the first metal layer is made of an alloy containing silicon and a metal different from the second metal layer. Production method. The nitride semiconductor layer on the first main surface of the silicon substrate;
14. The method for manufacturing a nitride semiconductor device according to claim 13, wherein in the metal electrode forming step, the metal electrode is formed on a second main surface opposite to the first main surface.   The method for manufacturing a nitride semiconductor device according to claim 14, further comprising a bonding step of bonding the silicon substrate and the nitride semiconductor layer before the electrode forming step.   16. The method for manufacturing a nitride semiconductor device according to claim 15, further comprising a polishing step of polishing the second main surface of the silicon substrate between the bonding step and the electrode forming step.   The method of manufacturing a nitride semiconductor device according to claim 16, wherein in the polishing step, the thickness of the silicon substrate is polished to 50 µm to 250 µm.   18. The nitride semiconductor according to claim 13, wherein in the step of forming the first metal layer, the first metal layer is formed of an alloy including a transition metal and silicon. Device manufacturing method.   19. In the process of forming the first metal layer, the first metal layer is formed so that an average particle diameter of an island is 100 mm or less. A method for producing a nitride semiconductor device according to claim 1. The silicon substrate is p-type;
20. The process of forming the second metal layer, wherein the second metal layer is formed of a material mainly containing at least one platinum group. A method for producing a nitride semiconductor device according to claim 1.

Images