JP2009005272A - Pilot pll circuit and fm stereo demodulation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pilot PLL circuit capable of enhancing control characteristics. <P>SOLUTION: The pilot PLL circuit includes: an NCO (Numerically Controlled Oscillator) 31 whose output frequency varies by control data given thereto; a ROM table 32 to which the output frequency is given to output cosine-wave data of a first frequency; a multiplier 33 to which FM demodulation data and the cosine-wave data are given, and which multiplies the both and outputs the multiplication results; an integrator 35 that outputs cumulative addition data obtained by integrating the multiplication results; an LPF 34 to which the multiplication results are given, and which outputs a signal for the frequency deviation between the FM demodulation data and the output frequency; an adder 36 that adds the cumulative addition data and the frequency deviation signal to output the control data; and a pilot signal detection circuit 50 that detects pilot signal component of the FM demodulation data to output a pilot signal detection signal, wherein the integrator controls the cumulative addition data values according to the pilot signal detection signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a pilot PLL circuit and an FM stereo demodulation circuit, and more particularly to a circuit suitable for FM stereo demodulation of a digital-compatible FM receiver.

  In recent years, a digital PLL circuit that generates a subcarrier signal used for stereo demodulation in a digital-compatible FM receiver that converts a received signal into an intermediate frequency signal and then converts it into a digital signal for demodulation processing. It is made up of.

However, in the conventional pilot PLL circuit, the phase control is performed using the value of the cumulative addition data in the integration circuit regardless of the presence or absence of the 19 kHz pilot signal component included in the FM stereo demodulated data, thereby improving the control characteristics. I couldn't.
JP 2006-129536 A

  In view of the above circumstances, an object of the present invention is to provide a pilot PLL circuit and an FM stereo demodulation circuit that can improve control characteristics.

  The pilot PLL circuit according to an aspect of the present invention is an FM demodulator in which a sum signal of signals L and R is a main channel signal, and a signal obtained by balanced modulation of a subcarrier signal using a difference signal of signals L and R is a subchannel signal. In a pilot PLL circuit to which data is supplied, a numerically controlled oscillator whose output frequency is changed by being supplied with control data, and a cosine wave data having a first frequency which is supplied with the output frequency from the numerically controlled oscillator. 1 ROM table, the FM demodulated data, and the cosine wave data of the first frequency are given and multiplied, a multiplier for outputting the multiplication result, the multiplication result is given, and the multiplication result is integrated. An integrator that outputs the accumulated addition data, the multiplication result, and the FM demodulated data and the output frequency from the numerically controlled oscillator A low-pass filter that outputs a frequency deviation signal including a frequency deviation component, an adder that adds the cumulative addition data and the frequency deviation signal, and outputs the result to the numerically controlled oscillator as the control data; and the FM demodulated data A pilot signal detection circuit that detects the presence or absence of a pilot signal component included in the signal and outputs a pilot signal detection signal, and the integrator controls the value of the cumulative addition data according to the pilot signal detection signal It is characterized by that.

  In the FM stereo demodulation circuit according to one aspect of the present invention, an FM signal in which a sum signal of signals L and R is a main channel signal, and a signal obtained by balanced modulation of a subcarrier signal using a difference signal between the signals L and R is a subchannel signal. In an FM demodulating circuit that receives demodulation data and performs demodulation processing, a numerically controlled oscillator whose output frequency changes by receiving control data, and a cosine of a first frequency given the output frequency from the numerically controlled oscillator A first ROM table that outputs wave data; a second ROM table that outputs sine wave data of a second frequency given the output frequency from the numerically controlled oscillator; the FM demodulated data; Multiplier given and multiplied with cosine wave data of the first frequency, and a multiplier for outputting the multiplication result, and the accumulation obtained by integrating the multiplication result An integrator that outputs calculation data; a low-pass filter that is provided with the multiplication result and outputs a frequency deviation signal including a frequency deviation component between the FM demodulated data and the output frequency from the numerically controlled oscillator; An adder that adds the accumulated addition data and the frequency deviation signal and outputs the added data as the control data to the numerically controlled oscillator; and detection of the presence or absence of a pilot signal component included in the FM demodulated data A pilot signal detection circuit that outputs a first pilot signal detection signal performed based on the second threshold signal and a second pilot signal detection signal performed based on the second threshold, and the integrator performs the cumulative addition A pilot PLL circuit for controlling a data value in accordance with the first pilot signal detection signal; the FM demodulated data; and the second pilot signal. An output signal, and when the second pilot signal detection signal indicates the presence of a pilot signal, a pilot cancellation circuit that performs processing for canceling the pilot signal with respect to the FM demodulated data; And a demodulating circuit which receives the output and sine wave data of the second frequency and generates the sub-channel signal.

  In the FM stereo demodulation circuit according to one aspect of the present invention, the sum signal of the signals L and R is the main channel signal, and the signal obtained by balanced modulation of the subcarrier signal using the difference signal of the signals L and R is the subchannel signal. In an FM demodulating circuit that performs demodulation processing by receiving FM demodulated data, a numerically controlled oscillator whose output frequency is changed by receiving control data, and a first frequency that is supplied with the output frequency from the numerically controlled oscillator From the first ROM table that outputs the cosine wave data of the second, the second ROM table that outputs the sine wave data of the second frequency given the output frequency from the numerically controlled oscillator, and the numerically controlled oscillator A third ROM table that outputs the first frequency sine wave data, the FM demodulated data, and the first frequency A multiplier for receiving and multiplying the cosine wave data of the wave number, outputting the multiplication result, an integrator for receiving the multiplication result, and outputting cumulative addition data obtained by integrating the multiplication result, and giving the multiplication result A low-pass filter that outputs a frequency deviation signal including a frequency deviation component between the FM demodulated data and the output frequency from the numerically controlled oscillator; and the accumulated addition data and the frequency deviation signal are added. An adder that outputs the control data to the numerically controlled oscillator; a second multiplication that multiplies the FM demodulated data and the sine wave data of the first frequency given and outputs a second multiplication result; A second low-pass filter that outputs the first low-frequency component given the second multiplication result, and an absolute value that is output by converting the sign of the first low-frequency component into a positive number A first comparator that outputs a first pilot signal detection signal obtained by comparing a path, an output from the absolute value circuit, and a first threshold; a cosine wave of the FM demodulated data and the first frequency; A third multiplier that multiplies the data and outputs a third multiplication result; a third low-pass filter that outputs the second low-frequency component given the third multiplication result; A second comparator that outputs the second pilot signal detection signal that compares the second low-frequency component with a second threshold; and the first pilot signal detection signal and the second pilot signal detection A pilot signal detection circuit having a logic circuit for receiving a signal and performing a predetermined logical operation and outputting a third pilot signal detection signal, wherein the integrator determines the value of the cumulative addition data. , Second or third pilot When a pilot PLL circuit that controls the signal detection signal according to any one of them, the FM demodulated data, and the third pilot signal detection signal are given, and the third pilot signal detection signal indicates the presence of the pilot signal , Given a pilot cancellation circuit that performs processing for canceling the pilot signal on the FM demodulated data, an output from the pilot cancellation circuit, and sine wave data of the second frequency, And a demodulating circuit to be generated.

  According to the pilot PLL circuit and the FM stereo demodulation circuit of the present invention, the control characteristics can be improved.

  Hereinafter, a pilot PLL circuit and an FM stereo demodulation circuit according to embodiments of the present invention will be described with reference to the drawings.

(1) Embodiment 1
As shown in FIG. 1, a digital-compatible FM receiver including a pilot PLL circuit according to the first embodiment and an FM stereo demodulation circuit including the pilot PLL circuit includes an antenna end 10, an FM front end circuit 11, and an FM intermediate circuit. A frequency amplifier 12, an A / D converter 13, an FM demodulation circuit 14, a stereo demodulation circuit 15, auditory correction circuits 16a and 16b, D / A converters 17a and 17b, and speakers 18a and 18b are provided.

  The FM wave received by the antenna end 10 is selected by the FM front-end circuit 11 as the reception frequency signal of the desired receiving station, converted into an intermediate frequency band by the FM intermediate frequency amplifier 12, amplified, and output as an intermediate frequency signal. Is done. This intermediate frequency signal is converted to a digital signal by the A / D converter 13 and converted to FM demodulated data (baseband signal) by the FM demodulating circuit 14.

  In the case of an FM stereo signal, this FM demodulated data is an (L + R) main channel signal and an (LR) subchannel signal. The stereo demodulator circuit 15 converts the main channel signal and the subchannel signal into stereo. Demodulated to a signal (L / R).

  The demodulated stereo signals (L / R) are subjected to auditory correction in the auditory correction circuits 16a and 16b, output as analog audio signals in the D / A converters 17a and 17b, and reproduced in the speakers 18a and 18b.

  An example of a specific configuration of the stereo demodulation circuit 15 is shown in FIG. The stereo demodulation circuit 15 includes a pilot cancellation circuit 21, a subchannel demodulation circuit 22, and a pilot PLL circuit 23 corresponding to a stereo dematrix circuit.

  The FM demodulated data output from the FM demodulating circuit 14 is input to the pilot cancel circuit 21 and the pilot PLL circuit 23. The FM demodulated data is an (L + R) main channel signal and an (LR) subchannel signal.

  As will be described later, in the pilot PLL circuit 23, a pilot signal detection signal that detects whether or not a 19 kHz pilot signal is included in the FM demodulated data is output to the pilot cancellation circuit 21. Further, the pilot PLL circuit 23 outputs a 38 kHz subcarrier signal generated based on the 19 kHz pilot signal to the subchannel demodulation circuit 22.

  In the pilot cancellation circuit 21, as described later, based on the pilot signal detection signal, when a 19 kHz pilot signal is superimposed on the FM demodulated data, it is removed by subtracting the pilot signal component from the main signal. When the pilot signal is not included, the operation is performed so as not to remove it.

  The FM demodulated data that is removed by including or eliminating the pilot signal is output to the subchannel demodulating circuit 22. The sub-channel demodulation circuit 22 is supplied with FM demodulated data not including a pilot signal and a 38 kHz sub-carrier signal, and multiplies them to generate a sub-channel signal (LR). Further, the main channel signal (L + R) and the subchannel signal (LR) are added and subtracted to generate a stereo signal (L, R).

  FIG. 3 shows an example of a specific configuration of a pilot PLL circuit that corresponds to the pilot PLL circuit 23 in the stereo demodulation circuit 15 and generates a pilot signal and a subcarrier signal.

  The pilot PLL circuit 23 includes a numerically controlled oscillator (hereinafter referred to as NCO) 31, a 19 kHz cosine wave ROM table 32, a multiplier 33, a low-pass filter 34, an integrator 35, an adder 36, a 38 kHz sine wave ROM table 37, 19 kHz. A sine wave ROM table 38 and a pilot signal detection circuit 50 are provided. The pilot signal detection circuit 50 includes a multiplier 39, a low-pass filter 40, and a comparator 41.

  The operation of pilot PLL circuit 23 having the above configuration will be described. First, the NCO 31 corresponds to a counter circuit that receives control data and outputs a counter value in which a cycle of the counter changes.

  When the counter value is output from the NCO 31, it is output to the 19kHz cosine wave ROM table 32, 38kHz sine wave ROM table 37, and 19kHz sine wave ROM table 38, respectively. These 19 kHz cosine wave ROM table 32, 38 kHz sine wave ROM table 37, and 19 kHz sine wave ROM table 38 respectively store cosine wave or sine wave data having a preset frequency, and provide counter values. Then, each data is called and 19 kHz cosine wave data, 38 kHz sine wave data, and 19 kHz sine wave data are output.

  The multiplier 33 is supplied with FM demodulated data and 19 kHz cosine wave data, and outputs a multiplication result. This multiplication result includes a signal component corresponding to a phase deviation existing between the 19 kHz component included in the FM demodulated data from the broadcast station and the 19 kHz component generated in the receiver.

  The multiplication result from the multiplier 33 is given to the integrator 35 and the low-pass filter 34. The integrator 35 outputs a value obtained by accumulating the phase deviation included in the multiplication result.

  On the other hand, only the low frequency component in the output from the multiplier 33 is output from the low-pass filter 34. This includes the 19 kHz component included in the FM demodulated data from the broadcasting station and the 19 kHz generated in the receiver. A signal component corresponding to a frequency deviation existing between the components is included.

  In the adder 36, the output from the integrator 35 and the output from the low pass filter 34 are added and fed back to the NCO 31 as control data. The control data includes a 19 kHz component included in the FM demodulated data, a signal component corresponding to a phase deviation existing between the 19 kHz component generated in the receiver, and a signal component corresponding to the frequency deviation. . Therefore, the NCO 31 outputs a counter value considering these phase deviations and frequency deviations.

  The counter value outputted from the NCO 31 to which such control data is given is given to the 38 kHz sine wave ROM table 37, and the 38 kHz sine wave data is outputted as a subcarrier signal and outputted to the demodulation circuit 22.

  The accumulated addition data in the integrator 33 is controlled by a pilot signal detection signal output from the pilot signal detection circuit 50 as will be described later.

Here, the multiplication result output from the multiplier 33 is expressed by Expression (1).
sin (α) * cos (β) = sin (α) * cos (α + delta) = sin (α) * {cos (α) * cos (delta) -sin (α) * sin (delta)}
= sin (α) * cos (α) * cos (delta)-sin (α) * sin (α) * sin (delta)
= {sin (2α)} / 2 * cos (delta) + {1-cos (2α)} / 2 * sin (delta) (1)

Further, the low-frequency component output when the multiplication result is given to the low-pass filter 34 assumes that the terms of sin (2α) and cos (2α) are removed by the low-pass filter 34, thereby obtaining the above equation (1). Is represented by the following equation (2).
sin (α) * cos (β) => 1/2 * sin (delta) (2)

  In this way, the 19 kHz pilot signal component included in the FM demodulated data is multiplied by the data that changes in accordance with the phase deviation and frequency deviation between the 19 kHz cosine wave data generated by the NCO 31 and the 19 kHz cosine wave ROM table 32. It can be taken out from the vessel 33. By supplying this data to the NCO 31 as control data, a pilot signal synchronized with the 19 kHz pilot signal included in the FM demodulated data is output and output to the pilot cancellation circuit 21, and a 38 kHz subcarrier signal is generated and demodulated. It can be output to the circuit 22.

  FIG. 4 shows the detection characteristic represented by the equation (1). Specifically, the horizontal axis indicates the phase deviation between 19 kHz of the pilot signal included in the FM demodulated data input to the multiplier 33 and 19 kHz output from the NCO 31 and 19 kHz cosine wave ROM table 32, and the vertical axis Shows the output value of the multiplier 33.

  When the phase deviation is “0” or “π”, the output value of the multiplier 33 is “0”, and when the phase deviation is π / 2, the output of the multiplier 33 takes the maximum value.

  The pilot signal detection circuit 50 detects the presence or absence of a 19 kHz pilot signal component in the FM demodulated data, that is, whether it is a stereo broadcast or a monaural broadcast, or a stereo broadcast, but the reception state is poor and a 19 kHz pilot signal. It is discriminate | determined whether the component is not contained.

  The multiplier 39 receives FM demodulation data and 19 kHz sine wave data output from the 19 kHz sine wave ROM table 37 and multiplies them. Here, the multiplier 33 multiplies the FM demodulated data including the pilot signal which is a 19 kHz sine wave and the 19 kHz cosine wave data, and outputs a multiplication result corresponding to the phase deviation between the two.

  On the other hand, in the multiplier 39, both of the input data are 19 kHz sine waves. Further, it is considered that the phase deviation and frequency deviation between 19 kHz and 19 kHz output from the 19 kHz cosine wave ROM table 32 in the FM demodulated data are converged by the control data supplied to the NCO 31. Therefore, both the phase deviation and frequency deviation input to the multiplier 39 are considered to have converged.

  For this reason, the calculation result in the multiplier 39 differs greatly depending on whether or not the 19 kHz pilot signal is included in the FM demodulated data. Therefore, by applying the multiplication result to the low-pass filter 40 to extract a low frequency signal component and comparing it with a predetermined threshold in the comparator 41, a signal for detecting the presence or absence of the pilot signal component can be extracted.

  The obtained pilot signal detection signal is input to the pilot cancel circuit 21 and the integrator 35. When the pilot signal detection signal indicates that the pilot signal component does not exist in the FM demodulated data, the pilot cancel circuit 21 outputs the FM demodulated data to the demodulating circuit 22 without performing the process of canceling the pilot signal. .

  Further, when the pilot signal detection signal is input to the integrator 33, as described above, the accumulated addition data in the integrator 33 is controlled. Specifically, when it is determined that the pilot signal component does not exist in the FM demodulated data, the accumulated addition data is cleared to a value of “0”. As a result, when it is not stereo broadcast, or when it is determined that the broadcast condition is poor but the reception state is bad and the pilot signal component does not exist, the addition data accumulated in the integrator 35 when the pilot signal exists is present. By once clearing, control characteristics can be improved.

  Here, the response characteristic of pilot PLL circuit 23 in the first embodiment will be described.

  As described above, the integrator 35 accumulates and adds a DC offset component corresponding to the phase deviation between 19 kHz included in the broadcast signal and 19 kHz generated by the pilot PLL circuit 23, and the value is added to the low-pass filter 34. The output is added to the NCO 31 as control data. Thereby, even if there is a phase deviation or a frequency deviation between the broadcast signal and the pilot PLL circuit 23, the PLL operation can be performed without any trouble.

  On the other hand, when the accumulated addition data in the integrator 35 deviates significantly from the convergence value due to switching from monaural broadcasting to stereo broadcasting or a change in reception state during stereo broadcasting, on the other hand, The response characteristics will be adversely affected, and there is a possibility that the time until locking will be longer or it may not be locked.

  Therefore, in the first embodiment, the accumulated addition data in the integrator 35 is controlled based on the result of detecting the presence or absence of a 19 kHz pilot signal in the FM demodulated data. Specifically, when the pilot signal is not detected from the FM demodulated data, that is, when the phase detection result of the PLL is not close to the lock in the vicinity of “0”, the accumulated addition data in the integrator 35 is temporarily set to “0”. To clear. When the pilot signal is detected from the FM demodulated data, the integrator 35 is caused to operate the original integration operation to transmit the DC offset component. As a result, the accumulated addition data is not significantly deviated from the convergence value, and the function of transmitting the original DC offset component can be ensured and the convergence of the PLL can be improved.

(2) Embodiment 2
A pilot PLL circuit according to Embodiment 2 of the present invention and a pilot PLL circuit in an FM stereo demodulation circuit including the pilot PLL circuit will be described with reference to FIG.

  The second embodiment is different from the first embodiment in the configuration of the pilot signal detection circuit 50a. In the second embodiment, the pilot signal detection circuit 50a includes a multiplier 39, a low-pass filter 40, and two comparators 41a and 41b. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  The multiplier 39 receives FM demodulation data and 19 kHz sine wave data output from the 19 kHz sine wave ROM table 37 and multiplies them. A low-frequency component is extracted from the multiplication result by the low-pass filter 34 and supplied to the comparators 41a and 41b.

  The first threshold value is compared with the output of the low-pass filter 40 in the comparator 41a, the comparison result is given to the pilot cancellation circuit 21, and the cancellation process is performed when the pilot signal is detected.

  Further, the comparator 41 b compares the second threshold value with the output of the low-pass filter 40, and the comparison result is given to the integrator 35. In the integrator 35, when the pilot signal is not detected, the accumulated addition data is cleared to “0” or processed so as not to be cleared.

  As described above, the presence or absence of the pilot signal component may be determined based on different threshold values in the pilot signal cancellation processing in the pilot cancellation circuit 21 and the accumulated addition data clear processing in the integrator 35. Thereby, optimization of each process can be aimed at.

(3) Embodiment 3
A pilot PLL circuit according to Embodiment 3 of the present invention and a pilot PLL circuit in an FM stereo demodulation circuit including the pilot PLL circuit will be described with reference to FIG.

  This pilot PLL circuit 23b differs from the pilot PLL circuit 23 in the first embodiment in the configuration of the pilot signal detection circuit 50b, and further switches between two outputs from the pilot signal detection circuit 50b to integrate one of them. The difference is that a switching device 49 for inputting to the device 35 is provided. Other identical components are denoted by the same reference numerals and description thereof is omitted.

  The pilot signal detection circuit 50b has two systems of pilot signal detection units. One has a multiplier 41, a low-pass filter 42, and a comparator 43, and the other has a multiplier 44, a low-pass filter 45, an absolute value circuit 46, and a comparator 47, and an AND circuit 48 for inputting respective outputs. Is provided.

  The multiplier 41 receives FM demodulation data and 19 kHz cosine wave data output from the 19 kHz cosine wave ROM table 32 and multiplies them. Low-frequency components are removed from the multiplication result by the low-pass filter 42 and supplied to the comparator 43.

  Here, when the pilot signal component of the FM demodulated data is “sin (α)”, the output from the low-pass filter 42 is “1/2 * sin (delta)” as shown in the above equation (2). It becomes.

On the other hand, the output from the low-pass filter 45 is “1/2 * cos (delta)” as shown in the following equation (3).
sin (α) * cos (β) = sin (α) * sin (α + delta) = sin (α) * {sin (α) * cos (delta) + cos (α) * sin (delta)}
= sin (α) * sin (α) * cos (delta) + sin (α) * cos (α) * sin (delta)
= {sin (2α)} / 2 * sin (delta) + {1-cos (2α)} / 2 * cos (delta)
=> 1/2 * cos (delta) (3)

  Here, it is assumed that the terms sin (2α) and cos (2α) are removed by the low-pass filter 42.

  In the comparator 43, the first threshold value REF1 and the output from the low-pass filter 42 are compared, and the comparison result is given to the AND circuit 48 and the switch 49.

  Further, the FM demodulated data and the 19 kHz sine wave data output from the 19 kHz sine wave ROM table 38 are input to the multiplier 44 and multiplied. The low frequency component is removed from the multiplication result by the low-pass filter 45 and given to the absolute value circuit 46.

  The absolute value circuit 46 converts the sign of the output from the low-pass filter 45 into a positive number and outputs it. The output value is given to the comparator 47, compared with the second threshold value REF2, and the comparison result is output to the AND circuit 48.

  In the AND circuit 48, the logical product of the comparison results in the comparators 43 and 47 is obtained, and when the logical product value is “1”, it is determined that the pilot signal component exists in the FM demodulated data. That is, a signal indicating the presence of the pilot signal component is output from the AND circuit 48 only during the period when the comparators 43 and 47 determine that the pilot signal component exists. The output from the AND circuit 48 is given to the switch 49 and the demodulation circuit 22.

  In the switch 49, the comparison result output from the comparator 43 and the logical product output from the AND circuit 48 are given, and a switch control signal (not shown) is given, and either one is supplied to the integrator 35. It is given as a control signal for clearing the cumulative addition data.

  The detection characteristics in pilot PLL circuit 23b according to the third embodiment will be described with reference to FIG.

  The output from the low-pass filter 42 is shown by a curve b1, and the first threshold value REF1 of the comparator 43 is shown by a straight line b2. A comparison result signal b3 that is logical “1” in a range where the value of the curve b1 is larger than the straight line b2 is output from the comparator 43.

  On the other hand, the output outputted from the low-pass filter 45 and passed through the absolute value circuit 46 is shown by a curve a1, and the second threshold value REF2 included in the comparator 47 is shown by a straight line a2. A comparison result signal a3 that is logical “1” in a range where the value of the curve a1 is larger than the straight line a2 is output from the comparator 47.

  When the comparison result signal b3 from the comparator 43 and the comparison result signal a3 from the comparator 47 are supplied to the AND circuit 48, the comparison result signal c in which the period during which both are logic “1” is “1” is “1”. Is output.

  According to the third embodiment, by using the comparison result signal b3 having a wider pulse width and the comparison result signal c having a relatively narrow pulse width, the multiplier 33, the integrator 35, the low-pass filter 34, the NCO 31 , A state transition to the unlocked state, the converged state, and the locked state in the PLL loop composed of the 19 kHz cosine wave ROM table 32 can be detected, and the operation of clearing the cumulative addition data in the integrator 35 can be controlled accordingly. .

1) While the comparison result signals b3 and c are both logic “0”, it is determined that the PLL loop is unlocked, and the comparison result signal c1 output from the AND circuit 48 is supplied to the integrator 35 and accumulated. Addition data is cleared to zero.

2) From this state, when the comparison result signal b3 is logic “1” but the comparison result signal c is logic “0”, it is determined that the PLL loop is approaching convergence, and the switch From 49, the comparison result signal b3 is applied to the integrator 35, the clear operation is not performed, and the integration operation is started.

3) Next, when both the comparison result signals b3 and c become logic “1”, it is determined that the PLL loop is locked, and the comparison result signal c is given from the switch 49 to the integrator 35, and the clear operation is performed. The integration operation is continued without this.

4) From this state, when the comparison result signal b3 is logic “1” but the comparison result signal c is logic “0”, it is determined that the PLL loop is not locked but is close to convergence. The comparison result signal c is supplied from the switch 49 to the integrator 35, the accumulated addition data is cleared, and the integration operation is stopped.

5) Further, when both of the comparison result signals b3 and c become logic “0”, it is determined that the PLL loop is in the unlock state during that time, and the comparison result signal b3 output from the AND circuit 48 is given to the integrator 35. In addition, the cumulative addition data is maintained cleared to zero, and the integration operation is stopped.

  As described above, as shown in 1) to 5), the cumulative addition data clearing operation and integration operation are controlled in accordance with the state transition.

  The above-described embodiments are merely examples and do not limit the present invention, and various modifications can be made within the technical scope of the present invention. For example, in the third embodiment, the integrator 35 clears the accumulated addition data accumulated in accordance with the output from the comparator 43 or the output from the AND circuit 48 given through the switching circuit 49 in FIG. ing. However, the present invention is not limited to this, and the accumulated addition data may be cleared according to any output from the comparator 43, the comparator 47, and the AND circuit 48.

1 is a block diagram showing a configuration of a digital-compatible FM receiver according to Embodiment 1 of the present invention. The block diagram which shows the structure of the FM stereo demodulation circuit contained in the FM receiver. The block diagram which shows the structure of the pilot PLL circuit contained in the FM stereo demodulation circuit. The graph which shows the relationship between the output value from the multiplier 33 contained in the pilot PLL circuit, and a phase deviation. The block diagram which shows the structure of the pilot PLL circuit contained in the FM stereo demodulation circuit of the FM receiver by Embodiment 2 of this invention. The block diagram which shows the structure of the pilot PLL circuit contained in the FM stereo demodulation circuit of the FM receiver by Embodiment 3 of this invention. 10 is a graph showing detection characteristics of a pilot signal component in the pilot PLL circuit according to the third embodiment.

Explanation of symbols

15 FM stereo demodulation circuit 21 Pilot cancellation circuit 22 Subchannel demodulation circuits 23, 23a, 23b Pilot PLL circuit 31 Numerically controlled oscillator (NCO)
32 19 kHz cosine wave ROM table 33, 39 Multiplier 34, 40 Low pass filter (LPF)
35 integrator 36 adder 37 38 kHz sine wave ROM table 38 19 kHz sine wave ROM table 39 multiplier 41, 41a, 41b comparator

Claims (5)

In a pilot PLL circuit to which FM demodulated data is provided in which a sum signal of signals L and R is a main channel signal and a signal obtained by balanced modulation of a subcarrier signal by a difference signal of signals L and R is a subchannel signal.
A numerically controlled oscillator whose output frequency changes given control data; and
A first ROM table that outputs the cosine wave data of the first frequency given the output frequency from the numerically controlled oscillator;
A multiplier that multiplies the FM demodulated data with the cosine wave data of the first frequency and outputs a multiplication result;
An integrator that is provided with the multiplication result and outputs cumulative addition data obtained by integrating the multiplication result;
A low-pass filter that is provided with the multiplication result and outputs a frequency deviation signal including a frequency deviation component between the FM demodulated data and the output frequency from the numerically controlled oscillator;
An adder that adds the cumulative addition data and the frequency deviation signal and outputs the addition data to the numerically controlled oscillator;
A pilot signal detection circuit that detects the presence or absence of a pilot signal component included in the FM demodulated data and outputs a pilot signal detection signal;
With
The pilot PLL circuit, wherein the integrator controls a value of the accumulated addition data in accordance with the pilot signal detection signal. The pilot PLL circuit of claim 1;
A second ROM table which is further included in the pilot PLL circuit and which outputs the sine wave data of the second frequency given the output frequency from the numerically controlled oscillator;
A pilot cancellation circuit that receives the FM demodulated data and the pilot signal detection signal, and performs processing for canceling the pilot signal for the FM demodulated data when the pilot signal detection signal indicates the presence of a pilot signal;
A demodulation circuit that receives the output from the pilot cancellation circuit and the sine wave data of the second frequency and generates the sub-channel signal;
The FM stereo demodulation circuit according to claim 1, further comprising: An FM stereo that performs demodulation processing by receiving FM demodulated data in which a sum signal of the signals L and R is a main channel signal, and a signal obtained by balanced modulation of a subcarrier signal by a difference signal of the signals L and R is a subchannel signal. In the demodulation circuit,
A numerically controlled oscillator whose output frequency changes given control data; and
A first ROM table that outputs the cosine wave data of the first frequency given the output frequency from the numerically controlled oscillator;
A second ROM table that outputs the sine wave data of the second frequency given the output frequency from the numerically controlled oscillator;
A multiplier that multiplies the FM demodulated data with the cosine wave data of the first frequency and outputs a multiplication result;
An integrator that is provided with the multiplication result and outputs cumulative addition data obtained by integrating the multiplication result;
A low-pass filter which is provided with the multiplication result and outputs a frequency deviation signal including a frequency deviation component between the FM demodulated data and the output frequency from the numerically controlled oscillator;
An adder that adds the cumulative addition data and the frequency deviation signal and outputs the addition data to the numerically controlled oscillator;
The first pilot signal detection signal that is detected based on the first threshold and the second pilot signal detection signal that is detected based on the second threshold are detected based on the first threshold. And a pilot PLL circuit that controls the value of the cumulative addition data in accordance with the first pilot signal detection signal.
When the FM demodulated data and the second pilot signal detection signal are given, and the second pilot signal detection signal indicates the presence of a pilot signal, processing for canceling the pilot signal is performed on the FM demodulated data A pilot cancellation circuit;
A demodulation circuit that receives the output from the pilot cancellation circuit and the sine wave data of the second frequency and generates the sub-channel signal;
An FM stereo demodulation circuit comprising: The pilot PLL circuit further includes a third ROM table that receives the output frequency from the numerically controlled oscillator and outputs sine wave data of the first frequency,
The pilot signal detection circuit includes:
A second multiplier that multiplies the FM demodulated data with the first frequency sine wave data and outputs a second multiplication result;
A second low-pass filter that is provided with the second multiplication result and outputs a low-frequency component;
A first comparator that outputs the first pilot signal detection signal that compares the low-frequency component with a first threshold;
A second comparator that outputs the second pilot signal detection signal comparing the low frequency component and a second threshold;
4. The FM stereo demodulation circuit according to claim 3, further comprising: FM demodulation that performs demodulation processing given FM demodulation data in which a sum signal of signals L and R is a main channel signal, and a signal obtained by balanced modulation of a subcarrier signal by a difference signal of signals L and R is a subchannel signal In the circuit
A numerically controlled oscillator whose output frequency changes given control data; and
A first ROM table that outputs the cosine wave data of the first frequency given the output frequency from the numerically controlled oscillator;
A second ROM table that outputs the sine wave data of the second frequency given the output frequency from the numerically controlled oscillator;
A third ROM table that outputs the sine wave data of the first frequency given the output frequency from the numerically controlled oscillator;
A multiplier that multiplies the FM demodulated data with the cosine wave data of the first frequency and outputs a multiplication result;
An integrator that is provided with the multiplication result and outputs cumulative addition data obtained by integrating the multiplication result;
A low-pass filter which is provided with the multiplication result and outputs a frequency deviation signal including a frequency deviation component between the FM demodulated data and the output frequency from the numerically controlled oscillator;
An adder that adds the cumulative addition data and the frequency deviation signal and outputs the addition data to the numerically controlled oscillator;
The FM demodulated data and the first frequency sine wave data are given and multiplied, a second multiplier for outputting a second multiplication result, and the second multiplication result given to the first multiplier A second low-pass filter that outputs a low-frequency component; an absolute value circuit that converts the sign of the first low-frequency component into a positive number and outputs it; and an output from the absolute value circuit and a first threshold value. A first comparator for outputting the compared first pilot signal detection signal;
The FM demodulated data and the cosine wave data of the first frequency are given and multiplied, a third multiplier for outputting a third multiplication result, and a second multiplier given the third multiplication result. A third low-pass filter that outputs a low-frequency component; a second comparator that outputs the second pilot signal detection signal obtained by comparing the second low-frequency component with a second threshold; A pilot signal detection circuit having a logic circuit that is supplied with the pilot signal detection signal and the second pilot signal detection signal and performs a predetermined logical operation and outputs a third pilot signal detection signal, A pilot PLL circuit in which an integrator controls a value of the cumulative addition data according to the first, second, or third pilot signal detection signal;
When the FM demodulated data and the third pilot signal detection signal are given, and the third pilot signal detection signal indicates the presence of a pilot signal, processing for canceling the pilot signal is performed on the FM demodulated data A pilot cancellation circuit;
A demodulation circuit that receives the output from the pilot cancellation circuit and the sine wave data of the second frequency and generates the sub-channel signal;
An FM stereo demodulation circuit comprising:

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