JPS594897B2 - receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a broadcast wave that is expressed as a composite signal of one carrier wave and a sideband wave obtained by amplitude modulating a plurality of carrier waves having the same frequency and different phases using a plurality of information signals. The present invention relates to a receiving device, and particularly to an AM-AM stereo broadcast receiver.

In recent years, stereo broadcasting has been proposed in which mutually orthogonal carrier waves are amplitude-modulated using two pieces of information, synthesized, and transmitted together with the carrier wave. By the way, such broadcast waves are (1)
where ER(t): broadcast wave, I: amplitude of carrier wave, Ki: AM modulation degree, Kj; AM modulation degree, ωo;
Angular frequency of carrier wave, Fi(t), Fj(t): information to be transmitted.

This broadcast wave can be transformed as shown in the following equation.

However, as is clear from equation (2), this broadcast wave is accompanied by phase fluctuations based on modulation.

Therefore, when receiving this broadcast wave, it cannot be demodulated by a normal demodulation circuit for AM broadcast reception, and the extraction of the carrier wave for demodulation always includes a phase fluctuation component as described above.
It is necessary to devise a method to extract a carrier wave with a fixed phase.

Conventionally proposed carrier wave extraction circuits excite a resonant circuit whose resonance point can be controlled by voltage with an input signal, compare the phase of the resonant output with the input signal, and control the resonant circuit with the phase comparison output. a first phase-locked circuit, and a similar second phase-locked circuit whose input is this resonance output;
The alternating current component of the phase comparator output of the second phase-locked circuit is fed back to the first phase comparator to control the resonance circuit and suppress tracking of the phase fluctuation component, thereby reducing the resonance of the second phase-locked circuit. A carrier wave with a fixed phase is obtained as a circuit output, and a demodulated signal is obtained by multiplying and detecting the carrier wave and an input signal.

However, when using this method, the carrier wave extraction circuit does not have frequency selection characteristics, so when several signals are input, the target carrier wave is not extracted, and reception is therefore impossible. be.

In order to solve this problem, the present inventor provided a voltage controlled oscillator (VCO) as a carrier wave extraction circuit, and a first phase comparator that compares the phase of its output and an input signal.
A first phase synchronized circuit that controls the CO with the DC component of the phase comparator output and a voltage-controlled resonant circuit excited by the VCO output, and a first phase synchronized circuit that compares the phases of the resonant circuit output and the VCO output. A second phase synchronization circuit is provided with a second phase comparator, and the second phase synchronization circuit is configured to control the resonance point of the resonant circuit using the direct current output from the second phase comparator. We devised a system that controls the voltage controlled oscillator by feeding back to the synchronous circuit to suppress tracking of phase fluctuations.

An example of a receiving device using such a carrier extraction circuit is shown in block diagram form in FIG.

Referring to the figure, a broadcast wave received by an antenna 1 is tuned in a high frequency amplification and intermediate frequency conversion stage 2 by operation of a tuning circuit, and combined with a local oscillation frequency from a local oscillator 3 to be intermediated. The signal is converted into a frequency, amplified by an intermediate frequency amplifier 4, and input to a demodulator.

Note that 5 is a signal strength meter. The configuration up to this point is the same as that of a conventional AM receiver. The demodulator includes the two phase-locked circuits PLL1 and PLL2 described above.

That is, the first phase synchronization circuit includes a first phase comparator 6 that receives an intermediate frequency signal as input, a low-pass filter and a DC amplifier 7 that extracts and amplifies the DC component of its output, and a frequency It consists of a VCO 8 which is controlled by a VCO 8, and a frequency divider 9 which divides its output and supplies it to a phase comparator. On the other hand, the second phase-locked circuit PLL2 includes resonant circuits 1 and 0 excited by the output of the frequency divider 9. ), a second phase comparison circuit 11 that compares the phases of the resonance output of this resonance circuit and the frequency divider output, and a second phase comparison circuit 11 that extracts the DC component of the output and sends it to the resonance circuit 10 as a control signal. The AC component of the second phase comparator 11 is supplied to the low-pass filter and DC amplifier 7 of the first phase locked circuit PLL via the AC amplifier 13. Negative feedback is provided to suppress phase fluctuations. Note that it is clear that the frequency divider 9 does not necessarily need to be provided here. However, in this example, it is also used for another purpose, as described below. If such a phase-locked circuit is used, if the capture range of the first phase-locked circuit PLLl is narrowed, even if the input signal is a composite of several frequencies, the target frequency will be reliably captured. In other words, since it has frequency selectivity, it is possible to obtain a carrier wave with a fixed phase (in this case, since the frequency divider 9 is used, it is an integer multiple of the carrier wave) as the output of the VCO 8. One information signal can be obtained as an audio component at the output of the phase comparator 6.

That is, the first phase comparator can be used as one demodulator. Then, by shifting the phase of the extracted carrier wave according to the phase of the carrier wave of the signal component containing the other information signal and performing multiplicative detection, the other information signal can be demodulated.

Here, we show the case where the broadcast wave is according to equation (1), so
A carrier wave signal that is shifted by 900 from the output from the frequency divider 9 to the first phase comparator 6, that is, has the same phase as the carrier wave of the input signal, is obtained, and the input signal is detected by the multiplier detector 14, Demodulating other information signals.

That is, the frequency divider 9 is used as a phase shifter. Therefore, the two information signals are similar to conventional stereo broadcasting.
Assuming (L+R) and (L-R) signals, respectively, the audio component (L+R) of the output of the phase comparator 6 is amplified by the audio amplifier 15, while the output of the multiplicative detector 14 (
L-R) is amplified by audio amplifiers 16 and 17 to produce (1
One of 6 and 17 is an inverting amplifier 5.

), these outputs are passed through the dematrix circuit 18,
Obtain L signal and R signal. and 1 power amplifier each
The signal is supplied to speakers 21 and 22 via 9 and 20. In this way, it is possible to receive AM-AM stereo broadcasts.
Note that the switches Sla and Slb are stereo/monaural changeover switches, and are interlocked, and the figure shows the time of stereo reception. In monaural mode, there is no (L-R) signal, so open switches S and a to cut off the input to audio amplifiers 16 and 17, and turn on switch Slb to change the gain of audio amplifier 15. That's what I do. The operation of the receiver shown in FIG. 1 will be explained in more detail below.

The operation of the receiving device shown in FIG. 1 will be explained.

A broadcast wave as shown in equation (1) is received at step 1, selectively amplified to a required level at step 2, and the frequency-converted broadcast wave is obtained at the Ti terminal.

If this signal is EI(t), it can be expressed as EI(t). However, o: amplitude of frequency-converted carrier wave ωo: intermediate angular frequency Components that are the same as in equation (1) are indicated by the same symbols.

The signal of equation (3), like the signal of equation (1), is accompanied by phase fluctuations due to modulation. In order to separate and detect the two pieces of information from equation (3), it is necessary to generate a demodulated carrier wave of a fixed phase that is locked to the carrier wave of equation (3) in a demodulator.

The PLL is a phase-locked loop that follows the phase fluctuations in the required frequency band of the signal of equation (3), and is designed to follow even relatively fast phase fluctuations.

Therefore, when a signal with a frequency difference between the free-running frequency of VCO 8 and the capture range is applied from Ti, the PL
Ll has the ability to quickly lock onto this signal. However, in order to improve the selectivity of the PLL, the capture range must be lower than (ωo/2π±15KHz), so if the signal from 9 and the signal input from Ti are multiplied by 6 and 14 and detected, the input signal When the frequency is not within the capture range and approaches the free-running frequency of the VCO, an audio frequency bead is generated at the outputs of 6 and 14 and is reproduced from 21 and 22.

The same applies when the PLL is unlocked. PLL
2 refers to the signal from 9 related to the output signal of the VCO of the PLL. This signal is still accompanied by phase fluctuations within the range in which the PLL follows the phase fluctuations of the input signal. 10 is excited with a loose couple with 9 (
・Because of this, the vibration of the resonant frequency is tried to be maintained by the effect of Q of 10.

Therefore, even if the phase of the signal from 9 changes, the phase of the vibration from 10 hardly changes. Therefore, a difference in phase fluctuation occurs between the input and output signals of 10 (however, the average frequencies are the same), and this difference is compared by 11 and converted into a voltage fluctuation. Of this voltage fluctuation, the DC component and the extremely low frequency component below the audible frequency are extracted by 12, and the resonance frequency of 10 is controlled, so that the average phase difference between the input signal and the output signal of 10 is always π/ 2. Frequency components other than the above are amplified to the required level according to 13, and 7
will be returned to. Due to this feedback signal, the frequency fluctuation of 8 is suppressed and the phases of 8 and 9 are fixed. As a result, the output signal 9 has an average phase difference of π/2 from the input signal having the same wave number and fixed phase as the Ti input signal.

This signal is the same as EOsω0t when equation (3) is the input signal.

Therefore, when this signal is multiplied by the input signal at 6 and 14, the information of equation (5) is obtained at the output of 6, and the information of equation (4) is obtained at the output of 14, respectively.

The response of the PLL 2 to the phase fluctuation of the reference signal is slower than that of the PLL because the 12 passbands are narrow.

The voltage corresponding to the information obtained at the outputs of 6 and 14 is 1
The signal is amplified in steps 5, 16, and 17, and calculated in step 18.

The outputs of 16 and 17 are arranged to have opposite phases.

At the output of 18, a plurality of audible frequency signals subjected to predetermined arithmetic processing are obtained, which are amplified at 19 and 20, and then sent to 21 and 2.
2 as an audio output.

In a receiving device that operates in this manner, it is necessary to tune and detune the broadcast waves. When such an operation is performed, as mentioned above, unnecessary bead sounds are emitted from 21 and 22, so the out-of-synchronization is detected, and the audio muting is performed to intermittent the signals to 21 and 22, and the lock-in time of the PLL is changed. It is necessary to vary the capture range of PLL1, and to prevent malfunctions due to interference. In the demodulator of FIG. 1, in a steady state where PLL1 is locked to the input signal, the response of the phase fluctuation of the demodulated carrier wave (output of 9) to the phase fluctuation of the input is extremely slow. This is because, as mentioned above, it is inevitable that the demodulated carrier wave cannot be obtained unless the average phase of the input signal is locked. This condition is maintained even when the PLL is unlocked. 1. Therefore, when selecting and tuning a broadcast wave by rotating variable capacitors 2 and 3, it takes a very long time even if the desired signal wave is obtained at Ti and the PLL1 is locked, and the speed of selection by variable capacitor operation is Since normal audio output is obtained from 21 and 22 after PLL1 is locked, this does not match.

Therefore, synchronization is almost impossible. 2.Beads are generated from 6 and 14 until PLL1 is locked, and bead sounds are emitted from 21 and 22, which gives an unpleasant feeling.

3. Furthermore, in order to accurately lock PLL1 to the average phase of the input signal, the frequency obtained by dividing the free-running frequency of 8 by 9 must match the frequency of the input signal.

Therefore, if the locking speed of the PLL is slow, it will not match the speed of this tuning operation, making tuning impossible. Moreover, since these PLL1 and PLL2 operate so as to repel the phase fluctuation of the input, a hysteresis phenomenon occurs, making it even more difficult. This hysteresis phenomenon is as follows.

In order to perform accurate tuning, use a tuning meter and perform tuning operations based on these instructions. A tuning meter usually indicates accurate tuning when the pointer is centered on the meter's scale. Therefore, when attempting to synchronize from out-of-synchronization, in the case of this PLL, , PLL2,
Even if the movement of the pointer due to this operation is originally performed in the direction of synchronization, once the movement of the pointer is stopped, the movement of the pointer will move in the opposite direction. This is a hysteresis phenomenon. 4 Furthermore, if the combination of PLL, PLL2 is configured to maintain a fixed phase against phase fluctuations of the input signal, when this is actually used in a receiving device, the frequency of the desired input signal will be very close to that of the desired input signal. In some cases, signals having different frequencies (with a difference of several Hz) interfere with each other, and this composite signal is referred to.

When such an interfering signal is mixed, the phase fluctuation based on the desired signal, the phase fluctuation of the interfering wave, and the phase fluctuation based on the frequency difference are superimposed on the phase fluctuation based on the desired signal. Therefore, if the output of 6 is used as the audio mutating detection signal and the control signal is output when the phase error signal of 6 exceeds a certain threshold, the voltage fluctuation will be larger than that caused by a single signal. , resulting in malfunction. This malfunction occurs periodically when the interfering signal level becomes no longer negligible compared to the desired signal level, and phase fluctuations based on the frequency difference and phase fluctuations based on the modulation of the interfering wave become dominant. A certain degree of selectivity can be obtained by making the capture range of the 5PLL narrower than the frequency arrangement of broadcast waves.

However, if it is narrowed from the time of detuning, the response speed of the PLL becomes slow, which has the drawback that it is difficult to tune.

In addition, in order to avoid this, if a method is used to widen the capture range to some extent when detuning and then narrow it after the PLL1 is locked, the free vibration of the signal being compared with the 6-wave frequency of the human input signal may be used. If the difference with the frequency is not below the capture range, the lock will be lost again. In order to prevent such a phenomenon, it is sufficient to narrow the capture range after accurate locking. Therefore, where to obtain this control signal is a serious problem. As mentioned above, the PLL in Figure 1,
, PLL2, there are various difficulties in receiving actual broadcasts, and it is necessary to solve these problems. Therefore, an object of the present invention is to utilize the advantages of a receiving apparatus having a demodulator equipped with the two phase-locked circuits PLL, , PLL2 described above, while
It is an object of the present invention to provide a receiving device that allows easy channel selection.

For this purpose, the present invention provides a receiving device for broadcast waves that is expressed as a composite signal of one carrier wave and a sideband wave in which a plurality of carrier waves having the same frequency and different phases are amplitude-modulated using a plurality of information signals. A high frequency amplification and frequency conversion stage equipped with a frequency selection circuit that selects a received broadcast wave, a demodulator that obtains a carrier wave for demodulation from an intermediate frequency signal output from the stage and demodulates each information signal, and a demodulator that demodulates each information signal. In the receiving device, the demodulator includes a voltage controlled oscillator, a phase comparator that compares the phases of the output of the voltage controlled oscillator and the intermediate frequency signal, and a phase comparator that compares the phases of the output of the voltage controlled oscillator and the intermediate frequency signal. and a first low-pass filter that extracts the signal and supplies it as a control signal to the voltage-controlled oscillator, and a variable frequency circuit that is excited by the output of the voltage-controlled oscillator and whose resonance point is controlled by the voltage signal. a resonant circuit, a second phase comparator that compares the phases of the resonant output of the variable resonant circuit and the output of the voltage controlled oscillator, and extracts a DC component from the output and supplies it to the variable resonant circuit as a control voltage signal. a second phase-locked circuit having a second low-pass filter, and a feedback circuit for feeding back and superimposing an alternating current component of the output of the second phase comparator into a control signal to the voltage-controlled oscillator during tuning. a demodulation carrier extraction section configured to obtain a fixed phase demodulation carrier wave from the output of the voltage controlled oscillator, the first phase comparator which detects and outputs one information signal component from the output, and the voltage oscillator. It is composed of a detection section consisting of a multiplier detector which obtains each information signal by multiplying and detecting the output of which the output is phase-shifted to be in phase with the respective carrier waves and the above-mentioned input intermediate frequency signal, and obtains each information signal. A DC and AC amplifier is provided on the second phase comparison output side, and a DC blocking capacitor is provided on the output side of the second phase comparison output side to supply an AC component to the feedback circuit, and to reduce the DC level difference between the input and output of the amplifier. A comparison circuit for detecting the presence or absence is provided, and a feedback amount control circuit is provided in the feedback circuit so that full feedback is applied when the level difference is zero at the output of the comparison circuit, and feedback is cut off when there is a level difference. The present invention is characterized in that the feedback amount control circuit is controlled.

According to such a configuration, when detuning occurs, the feedback of the alternating current component from the second phase-locked circuit to the first phase-locked circuit is cut off, so that the response speed of the first phase-locked circuit becomes faster. , synchronization can be easily performed.

Furthermore, when the first phase-locked circuit locks, the AC component is fed back from the second phase-locked circuit to the first phase-locked circuit, so the capture range of the first phase-locked circuit becomes narrower, and the synchronized broadcast Waves can be received stably. Note that the muting circuit detects the DC component in the output of the first phase comparator and turns on the signal when the DC component is within a certain level, positive or negative, centered around zero, and turns off when the level is above that level. a first DC level detector that generates a signal; and a second level detector that detects a DC component in the output of the multiplier detector and generates an OFF signal when the DC component is zero and an ON signal when there is a DC component. a muting signal generating means that receives the outputs of the first and second level detectors and generates a muting signal when at least one of them is an off signal; and a muting signal generating means that is provided in the speaker circuit and is turned off by the muting signal. By configuring it with a muting switch, muting is applied until the first phase-locked circuit is completely locked, so the audio output is automatically cut off until the desired station is selected, and the desired station is switched off. When a station is selected, audio output is automatically and quickly obtained, thereby allowing accurate tuning.

Furthermore, the receiving apparatus according to the present invention further includes a switch provided on the detection output side of the multiplicative detector, and an on/off switch for this switch.
A switch control circuit for controlling the switch off and a circuit for detecting the stereo pilot signal included in the selected received broadcast wave are added, and when the stereo pilot signal is detected, the switch is turned on and other switches are turned on. If you turn it off, you can automatically switch between stereo and monaural reception.

Hereinafter, the present invention will be explained in detail with reference to embodiments shown in the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.
Portions similar to those in the figures are omitted except for particularly relevant portions. 6, 7, 9, 11 and 14 with reference to FIG.
are the same parts as in Figure 1, 13', A-E, Sfa, S
By providing fb, the aforementioned drawbacks are solved.

Both procs A and B are DC level detectors, and proc A detects whether or not there is a DC component in the output of the multiplier detector 14, and generates a signal accordingly.

On the other hand, the DC level detector B detects the DC component in the output of the first phase comparator circuit 6, sends a signal corresponding to the level to the meter E for display, and also outputs a signal from the DC level detector A. generates an output signal under the control of That is, the output of the multiplier detector 14 has a DC component when the phase locked circuit PLL is locked.

Therefore, the reason why the DC level detector has a high output is due to the PLL.
, is locked. On the other hand, the phase comparison circuit 6
A DC component is generated when there is a phase difference between the input frequency and the output obtained by dividing the free-running oscillation frequency of the VCO by the frequency divider 9 even though the PLL1 is in a locked state. Therefore, the DC component of the output of the phase comparator 6 is zero and the multiplier detector 14
When there is a DC component of , it indicates that the PLL is locked and at the same time, the input signal and the output of the frequency divider 9 have the same frequency (that is, synchronization has been achieved).

Therefore, when the DC component of the output of the phase comparator 6 is approximately zero (within a certain minute level centered around zero), the DC level detector B detects that the output from the DC level detector A is When the output of the multiplier detector 14 indicates that there is a direct current, an output signal is generated, thereby obtaining a signal for canceling audio mutating. Incidentally, such an operation of the DC level detector B can be easily realized by using the DC level detector and an AND circuit.

Block 13'' is an amplifier that amplifies DC as well as AC, and was used in place of 13 in Figure 1. In order to block the DC component as a feedback signal, a capacitor CO is connected to the output side.
has been established.

PROC C is a DC voltage comparator circuit that compares the input DC voltage levels of the amplifier 13' and generates an output signal when the two are equal.

Block D is a circuit for controlling feedback from PLL2 to PLL1, and is designed to allow half feedback with the output signal from DC level detector B, and to allow full feedback with the output of DC voltage comparator circuit C.

This control circuit D is designed to control the charging/discharging circuit using signals from B and C as shown in FIG. PROC F is a time constant circuit that uses a signal from C to increase the time constant of the muting switches Sfa and Sfb.
This prevents muting from operating due to temporary fluctuations in the output signal from B. By adding the above A-F blocks, the above-mentioned 1 in the receiver of FIG.
We will explain how the disadvantages of ~5 are solved.

Measure 1 This problem is solved by doing the following.

As mentioned above, PLLl has a fast tracking speed. PLLl and P
In the state in which LL2 is coupled, that is, in the state in which feedback is applied from 13 to 7, it is extremely slow. Therefore, by utilizing this property, when detuning, the feedback from PLL2 to PLLl is cut off, and first, PLLl captures and locks the input signal at high speed.

When PLLl is locked, the resonant frequency of the resonant circuit of PLL becomes the output frequency of PLLl, and PLL2 operates to lock to this. Therefore, after PLLl is locked, it is sufficient to return from PLL2 to PLLl in this manner. However, since the PLL has a cap challenge, even if it locks, it does not necessarily mean that it is in an accurately synchronized state. Therefore, if feedback is applied from PLL2 to PLL immediately after PLLl is locked, if you try to tune accurately while checking the indication on the tuning meter 1, a phenomenon like 3 will occur and tuning will become impossible.

To solve this problem, the PLL must be
Multiplying the return from 2 will turn out to be a good thing. PLL2 is P
As mentioned above, the response is slower than LL1, but this can be used to advantage. That is, when the DC level difference between the input and output of PLL2 131 becomes near zero, it means that the tuning is accurate enough for reception, so this state is detected by C, and D Turn on the state so that feedback is applied from PLL2. Then, after a control signal to turn on D is output from C, D is actually turned on with a further delay (usually after 2 to 3 seconds), causing an average phase fluctuation as in the case of a tuning operation. When such a situation occurs, D is immediately turned off to cut off the return. By setting in this way, feedback can be applied after the PLL1 is accurately locked (tuned), and the phenomenon described in 3 does not occur, and tuning can be performed according to the instructions of the tuning meter E. It becomes extremely easy. Furthermore, when an operation is attempted to detun from tuning, D is immediately turned off as described above, and the PLL speeds up, so the lock is released at high speed. This shows that when the lock is released, the frequency 8 immediately returns to the free running frequency, so by appropriately setting the lock range, it is possible to reduce the bead at the time of detuning. Note that the signal entering C from PLL 2 that turns D on and off is extremely sensitive to fluctuations in the average phase.
Since the voltage gain of 131 is high, even if the input voltage to 13', which indicates a phase variation, changes slightly, a control signal is immediately generated to turn off D. Therefore, if the circuit of D is PL
If PLLl is configured to completely block the feedback signal from L2 even though it is locked, such a situation will occur even though audio output is being obtained, resulting in extremely distorted sound. As the sound becomes louder, the separation between the left and right channels deteriorates. Therefore, in this proposal, the following method is adopted for circuit D. That is, when PLL is unlocked (out of tune), the feedback signal from D'('PLL2 is completely cut off).

Then, PLL is locked (tuned) and operates by detecting a signal indicating the tuned state of PLL, that is, the difference between the frequency of the input signal of T1 and the free running frequency of the signal from 9.
When a control signal indicating that the frequency difference is within the allowable frequency difference range is obtained, audio muting is canceled and audio output is output, and the audio output does not experience any audible distortion or deterioration of separation. D operates so that a signal that does not interfere with the tuning operation is fed back to PLL1 from PLL2. After more accurate synchronization is achieved, P
When the output of C, which indicates the tuning state of LL2, reaches a state where D should be turned on, full feedback is applied. That is, D performs multi-stage feedback level switching which causes the tuning state. Conventionally, control signals were obtained only from PLL, but in this way, PLL1 and PLL1 were obtained.
A synergistic effect can be obtained by controlling by obtaining control signals from both LL2. As mentioned above, the cause of the bead generation is the capture range of the PLL and the pull-in speed.

This phenomenon appears when the capture range narrows, and even if the input signal frequency falls within the capture range,
If the transient state until the PLL locks on is long, a bead will be generated. This phenomenon is closely related to the manual tuning speed; if the PLL locking speed is slow and the tuning operation speed is fast, beads will be emitted at all positions where broadcast waves are present. As the capture range is narrowed, the pull-in speed becomes slower, so there is naturally a compromise in relation to the aforementioned PLL selectivity and pull-in speed. If the pull-in speed is kept slow and the control output from the first window comparator of the PLL, ie, B, is used for muting, if the tuning operation speed is fast, the speed at which this control output is generated will also drop, so no audio output will be obtained. Therefore, the presence of broadcast waves cannot be detected audibly. Countermeasure for No. 5 Therefore, in this proposal, this problem is solved by skillfully utilizing the properties of PLL1 and PLL2.

First, in an out-of-tune state, the capture range of PLLl is widened, but set to a range that does not impair selectivity with adjacent stations.

After the PLL is locked (tuned) and accurate tuning is performed, the capture range is narrowed at the same timing as the signal that turns on D obtained from PLL 2 or later. By doing this, it is possible to avoid a situation in which the lock is released during the process of narrowing the capture range. This is because by the time the capture range is narrowed, it has already been accurately tuned. If the signal from B is used, the tuning state may not be within this range during the process of narrowing the capture range, which is not preferable because there is a possibility that the lock will be lost. Furthermore, if the cap is out of tune while the capture range is narrow, the lock will be lost and a bead will occur when the gear is out of tune. Since the output signal of C operates extremely sensitively, such a phenomenon can be prevented. That is, when an attempt is made to detune, a control signal is immediately generated from C to widen the capture range, and along with this control of the capture range, the PL
A control signal indicating the tuning state of L is used to mute the audio output to prevent (Sf) bead failure. Explanation of muting and tuning First, when detuning, the PLL is in an unlocked state, so 1
The DC voltage output of No. 4 is zero and supplies a signal from A to turn off BVCSf.

The output of No. 6 is also zero, which means that B should issue a signal to turn on Sf, but since the signal from A has priority, Sf is off.

Next, when PLL1 is locked (tuned) and not in an accurate state of tuning, the DC voltage output of 14 appears and supplies the control signal to turn on Sf from A to B, but the output of 6 also has a DC voltage. A control signal is supplied from B to Sf to keep it in the off state, and since this is made to take priority over the signal from A, Sf is still off. At this time, a voltage indicating the detuned state is being supplied to E from B, and this instruction is being given. Tuning operations continue based on this instruction. When the tuning state falls within a predetermined accuracy range, a signal to turn on Sf is generated from B, and since the conditions of A and B match, Sf is turned on and an audio output appears. This is a muting operation, and a signal for controlling D is also supplied from B to D.

Even during detuning and tuning, when the tuning is inaccurate, a signal is sent from B to D to keep D completely off in the same manner as during muting described above.

When this falls within the tuning range of the predetermined accuracy, from B to D
A control signal is supplied indicating that it may be turned on. However, at this time, when an average phase fluctuation occurs during the tuning operation, a control signal is given from C to D to keep D in a half-feedback state. When the tuning operation is completed and the tuning is accurate, C emits a signal that brings D into the full feedback state within a certain short time. At this timing, a signal is also supplied from C to F, and the time constant of the control circuit of the mutating switch Sf is controlled to be increased, and the on/off signal of Sf, which is supplied from B to Sf, is changed to the above-mentioned 4. As described above, even if it changes periodically or randomly, the state where Sf is kept on is maintained, so no malfunction occurs. Once it enters the complete tuning state, this PL
Since L operates so that the internal phase fluctuation of the PLL is fixed, the phase fluctuation due to interference of the reference signal of PLL 2, that is, the signal from 9, is suppressed, and the output of 11 maintains a constant level, and the output of 13' Since the output is also held, the control signal from C to F does not change. Therefore, this signal is F
By using this as a control signal, the above-mentioned malfunction can be prevented. When tuned correctly, the DC output of 6 will be zero.

This final state is maintained in the listening state.
Detuning operation When the detuning operation is performed, a signal indicating a fluctuation in the average phase immediately appears at the output of 13/, and a control signal to turn off F and D almost simultaneously at the output of C, and to widen the capture range of 7 from narrow to wide. is emitted.

After F, D and the capture range have been switched in this manner, when a predetermined detuning state is reached, a signal to turn off Sf is issued from B and turned off, cutting off the audio output. (At this time, the PLL is still locked.) When it is further detuned and unlocked, that is, completely detuned, a signal is supplied from A to B to keep Sf off. At this time, a signal to turn on Sf is supplied from 6 to B, but A
Sf is kept off because the signal from .
These operations are repeated depending on the tuning and detuning operations.

In this way complete control is achieved.

A feature of this demodulator is that it is always in a mode that can demodulate stereo (that is, the demodulated carrier wave has a fixed phase) when tuning, regardless of whether the signal applied to T1 is a monaural signal or a stereo signal.

Therefore, if the input signal contains a pilot signal indicating that it is a stereo signal, this can be reliably detected. That is, in broadcasting where a stereo signal is converted into a signal as shown in equation (1), pilot signal information is generally inserted into the second term of equation (1).

Assuming that the pilot signal is, where α is the amplitude of the pilot signal and p is the angular frequency of the pilot signal, then it is a broadcast wave as shown below, so in reception, it is necessary to demodulate equation (7) and detect it.

However, when detecting the m: modulation degree pilot signal, care must be taken to ensure that it is detected in an accurately tuned state and that false alarms are not detected when external noise or adjacent interference signals are mixed in the input signal. That's true.

In the demodulator of FIG. 2, this tuned steady state signal is the same as the output of 9 in the steady state.

Therefore, the pilot signal detection and control system can be constructed as shown in FIG. In Figure 4, I is the pilot signal selection amplifier and DC voltage output converter, is the driver for switches Sla and b, is the reception mode indicator, is the broadcast wave transmission mode indicator, V is the driver for S3, and S2 is manual. The reception mode changeover switch, S3, is a switch controlled by the signal from C, and is the driver of S4.

The pilot signal is obtained from the output of 6.

That is, if the output signal of 9 is taken, then the equation (3) x the equation (9) can be obtained, and the information mαCOspt can be obtained.

Therefore, when S3 is on, selective amplification is performed at I and this magnitude is converted into a DC voltage. When the output of I is zero, it indicates that the pilot signal is not detected, so the broadcast is monaural, and indicates that the broadcast is monaural.

When there is an output, it indicates that stereo broadcasting is being performed, so it indicates that the broadcast is stereo broadcasting.
When S2 is at contact 1, the receiver is in stereo auto switching mode, and depending on the output state of I, it operates and Sl
a, b/) are switched phase-wise, and the reception mode is set to stereo or monaural.

When S2 is at contact 2, the reception mode is forced to be monaural.

If the broadcast is in stereo at this time, indicates that it is a stereo broadcast. S3 is turned on when it is determined that the receiver is correctly tuned due to C.

By doing this, automatic mode switching and instructions are performed after accurate tuning is achieved, thereby preventing malfunctions and ensuring accurate operation.

Note that when detuning, the signal from A is turned off, and when tuning, it is connected.Furthermore, by configuring I as shown in Figure 5, it is effective to prevent malfunctions due to interference. This is effective in the following cases.

When the pilot signal is not being sent on the broadcasting side, if there is interference in the T1 input signal with an undesired signal whose angular frequency differs from the desired signal's angular frequency by p, a signal with an angular frequency of p is generated at the output of 6. be done.

I determines this as a pilot signal and switches the mode. This is a complete malfunction. The circuit shown in FIG. 5 is designed to prevent such a phenomenon and to operate accurately only when a pilot signal is being sent during broadcasting. In Fig. 5, a is a pilot signal selection amplifier;
b is a phase shifter that shifts the phase by π/2 at the pilot signal frequency, c
is an adder, d is a subtracter, E, f, and g are DC converters, h is an exclusive NOR circuit, and q is an AND circuit.

If the pilot signal is off and the above-mentioned interference signal is present, 6
A bead signal with an angular frequency p is obtained at the output of 14.

These signals have a phase difference of π/2 from each other. Therefore, if one side (output 14 in Fig. 5) is further phase shifted by π/2,
Signals having the same phase or opposite phases are obtained for Na and Nb.

This phase changes depending on whether the frequency of the jamming signal is higher or lower than the tuning frequency. If the Na and Nb signals are in phase, the output of c appears, is converted by e, and is applied to h. If the phase is opposite, the output of d appears, is converted by f, and is applied to h. Said phase relationship exists only when interference is present. When there is interference like this, e or f
The output appears at h, and the output at h is zero. On the other hand, since there is a signal at Na, it is converted by g and its output is supplied to q.

Furthermore, it is applied to q from h. Since one input of q is zero and the other is 1, the output is zero, and it is determined that the system is not stereo. In this way, an erroneous mode switching signal will not be generated due to interference waves. Next, when a pilot signal is sent, a signal appears at Na, but since Nb is zero, the same level signals are output at the outputs of C and d, and these are converted by E and f, respectively. applied to h.

Since the inputs of h are both 1, the output is 1, and the output of g is also 1.
The output of q becomes 1, indicating stereo. This circuit is lΣKiFi(t)l=1ΣKjFj(t)1
And both resonant frequencies are equal to the pilot signal and mutually π/
It will not malfunction unless it is modulated with signals with two different phases.

Satisfying this condition almost never occurs in actual broadcasting, and if the transmitting side blocks the components of this frequency band of the modulated signal in order to transmit the pilot signal with an I-pass filter, it will definitely be possible. It doesn't happen. In this way, an extremely excellent pilot signal detector can be provided.

As described above, according to the present invention, it is possible to provide an extremely excellent receiving device for AM-AM stereo broadcasting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic circuit configuration of the receiving device of the present invention, FIG. 2 is a block diagram showing the main parts of the circuit in FIG. 1 with various control functions added, and FIG. One specific circuit of the block indicated by D in the figure, FIG. 4 is a block diagram showing an automatic stereo/monaural switching circuit, and FIG.
FIG. 5 is a block diagram showing an example of a part of FIG. 4; 6...First phase comparator, 7...Low pass filter and DC amplifier, 8...Voltage controlled oscillator (VCO), 9... Frequency divider, 10...
... Resonance circuit, 11 ... Second phase comparator, 12 ... Low pass filter 1, 13 ...
...AC amplifier, 13''...DC and AC amplifier, 14... Multiplying detector, 15, 16, 17
...Audio amplifier, 18... Dematrix circuit, 19,20... Power amplifier, 2L22 1''.

Claims (1)

[Scope of Claims] 1. A receiving device for broadcast waves expressed as a composite signal of one carrier wave and sideband waves obtained by amplitude-modulating a plurality of carrier waves having the same frequency and different phases using a plurality of information signals, , a high-frequency amplification and frequency conversion stage equipped with a frequency selection circuit that selects a received broadcast wave, a demodulator that obtains a carrier wave for demodulation from the output intermediate frequency signal and demodulates each information signal, and a speaker when detuning. In the receiving device, the demodulator includes a voltage controlled oscillator, a first phase comparator that compares the phases of the output of the voltage controlled oscillator and the intermediate frequency signal, and a first phase comparator that extracts a DC component from the output of the voltage controlled oscillator. a first phase-locked circuit having a first low-pass filter that extracts and supplies the extracted control signal to the voltage-controlled oscillator; a variable resonant circuit that is excited by the output of the voltage-controlled oscillator and whose resonance point is controlled by the voltage signal; , a second phase comparator that compares the phases of the resonant output of the variable resonant circuit and the output of the voltage controlled oscillator, and a second phase comparator that extracts a DC component from the output and supplies it to the variable resonant circuit as a control voltage signal. and a feedback circuit for feeding back and superimposing the alternating current component of the output of the second phase comparator on the control signal to the voltage controlled oscillator during tuning. a demodulation carrier extraction unit configured to obtain a fixed phase demodulation carrier wave from the output of the controlled oscillator;
The first phase comparator detects and outputs one information signal component as an output, and the output of the voltage controlled oscillator is transferred so as to be in phase with each of the carrier waves, and the input intermediate frequency signal is multiplied and detected. The detector consists of a multiplier detector that obtains each information signal, and furthermore, a DC and AC amplifier is provided on the output side of the second phase comparison, and a DC blocking capacitor is provided on the output side of the second phase comparison output side. In addition to supplying an alternating current component to the feedback circuit, a comparison circuit is provided to detect the presence or absence of a direct current level difference between the input and output of the amplifier, and a feedback amount control circuit is provided in the feedback circuit to supply the output of the comparison circuit. When the level difference is zero, full feedback is applied, and when there is a level difference, feedback is cut off.
A receiving device characterized in that the feedback amount control circuit is controlled. 2. In the receiving device according to claim 1, the muting circuit detects the DC component in the output of the first phase comparator and detects that the DC component is within a certain minute level in positive and negative directions around zero. a first DC level detector that generates an on signal when the level is higher than the on signal;
a second level detector that detects a DC component in the output of the multiplier detector and generates an OFF signal when the DC component is zero and an ON signal when there is a DC component; and the first and second level detectors. It is characterized by having a muting signal generating means that receives the output and generates a muting signal when at least one of the signals is an off signal, and a muting switch that is provided in the speaker circuit and is turned off by the muting signal. A receiving device that does 3. In the receiving device according to claim 1, the muting circuit detects the DC component in the output of the first phase comparator, and the DC component is within a certain minute level in positive and negative directions around zero. a first DC level detector that generates an on signal when the level is higher than that, and generates an off signal when the level is higher than that;
a second level detector that detects a DC component in the output of the multiplier detector and generates an OFF signal when the DC component is zero and an ON signal when there is a DC component; and the first and second level detectors. muting signal generating means that receives the output and generates a muting signal when at least one of the signals is off; a muting switch that is provided in the speaker circuit and is turned off by the muting signal; and a muting switch that detects the presence or absence of the DC level difference. 1. A receiving device comprising: a circuit for increasing the time constant of the muting switch with a zero level difference signal from a comparison circuit to be detected. 4. A receiving device for broadcast waves expressed as a composite signal of one carrier wave and a sideband wave obtained by amplitude-modulating a plurality of carrier waves having the same frequency but different phases with a plurality of information signals, which selects a received broadcast wave. a high-frequency amplification and frequency conversion stage equipped with a frequency selection circuit, a demodulator that obtains a carrier wave for demodulation from the output intermediate frequency signal and demodulates each information signal, and a muting circuit that cuts off the speaker circuit when detuning. and a circuit for automatically switching between stereo and monaural, wherein the demodulator includes a voltage controlled oscillator, and a first phase comparator that compares the phases of the output of the voltage controlled oscillator and the intermediate frequency signal; a first phase-locked circuit having a first low-pass filter that extracts a DC component from the output and supplies it as a control signal to the voltage-controlled oscillator, which is excited by the output of the voltage-controlled oscillator and controls a resonance point with a voltage signal; a second phase comparator that compares the phases of the resonant output of the variable resonant circuit and the output of the voltage controlled oscillator; a second phase-locked circuit having a second low-pass filter supplied to the circuit; and feedback for feedback-superimposing the alternating current portion of the output of the second phase comparator on the control signal to the voltage-controlled oscillator during tuning. a demodulation carrier extraction section configured of a circuit and configured to obtain a demodulation carrier wave of a fixed phase at the output of the voltage controlled oscillator; the first phase comparator that detects and outputs one information signal component at the output; It is composed of a detection section consisting of a multiplier detector which obtains each information signal by multiplying and detecting the voltage oscillator output phase-shifted so as to be in phase with each of the carrier waves and the above-mentioned input intermediate frequency signal, Moreover, the second
DC and AC amplifiers are provided on the phase comparison output side of the amplifier, and a DC cutoff capacitor is provided on the output side of the amplifier to supply an AC component to the feedback circuit, and the presence or absence of a DC level difference between the input and output of the amplifier is detected. A comparison circuit for detecting is provided, and a feedback amount control circuit is provided in the feedback circuit so that full feedback is applied when the level difference is zero at the output of the comparison circuit, and feedback is cut off when there is a level difference. The circuit is configured to control the feedback amount control circuit, and furthermore, the circuit for automatically switching between stereo and monaural is connected to a switch provided on the detection output side of the multiplier detector and an on/off switch of the switch. A receiving device comprising: a switch control circuit for controlling; and a circuit for detecting a stereo pilot signal included in the selected received broadcast wave and supplying a switch-on signal to the switch control circuit. 5. The receiving device according to claim 4, wherein the circuit for supplying the switch-on signal includes a first circuit for detecting a stereo pilot signal included in the output of the first phase comparator, and the multiplier detector. A second circuit that uses the output as an input and detects a signal with the same frequency as the stereo pilot signal.
circuit, a phase shift circuit that shifts the phase of the second detection circuit output by π/2, a sum circuit and a difference circuit that take the sum and difference between the first detection circuit output and the phase shift circuit output, and a sum circuit. First and second circuits that convert each of the output and difference circuit output into DC, a circuit that takes an exclusive OR of the outputs of the first and second DC conversion circuits, and converts the output of the first detection circuit into DC. 3rd to do
and a circuit that takes the AND of the outputs of the exclusive OR circuit and the third DC conversion circuit, and supplies the AND output to the switch control circuit to automatically switch between stereo and monaural. A receiving device characterized in that it is configured to switch.