JP2009005055A - Gain-variable amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a gain-variable amplifier of a CMOS process meeting a wide dynamic range and high linearity while keeping NF satisfactory. <P>SOLUTION: The gain-variable amplifier has: a plurality of initial stages LNA1-4 connected in parallel to one input terminal IN; the next stage LNA5 connected to the poststage; and a variable current source 20 that controls control currents IB1-IB4 allowed to flow to the initial stages LNA1-4 and keeps constant the total value of simultaneously flowing control currents. The output lines of the initial stages LNA1-4 preventing the control currents from flowing simultaneously are connected mutually to form a plurality of composite output lines L1, L2 and separately input them to a plurality of input ends of the next-stage amplifier 5. In the next-stage amplifier 5, each signal inputted from the plurality of input ends is amplified, and each amplified signal is added for output. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a variable gain amplifier, and is particularly suitable for use in a variable gain amplifier in which a plurality of amplifiers are connected to increase the variable gain range.

  Usually, in a radio communication apparatus such as a radio receiver, an AGC (Automatic Gain Control) circuit is provided to adjust the gain of a received signal. An RF (Radio Frequency) -AGC circuit provided in the high frequency stage adjusts the gain of a high frequency signal (antenna input signal) received by an antenna so as to keep the level of the received signal constant. RF-AGC can be realized by controlling the attenuation in the antenna damping circuit and the gain of LNA (Low Noise Amplifier) and the like.

  In particular, in a radio tuner mounted on a mobile body such as an in-vehicle device or a mobile phone, it is desired to increase the variable gain range (dynamic range) of the LNA in order to cope with a wide range of mobile reception power. For example, when the received power is small, high gain and low noise characteristics are required. On the other hand, when the received power is large, a high linearity is required in which the relationship between the AGC control voltage and the decibel gain controlled thereby is linear.

In order to satisfy these two requirements and obtain a wide dynamic range, four cascode amplifiers are connected in parallel, and these cascode amplifiers are continuously switched according to the received power. A noise amplifier has been proposed (see, for example, Non-Patent Document 1). The cascode amplifier itself is frequently used as an LNA because there is basically no feedback from output to input.
Sharp Technical Report No. 88: Published in April 2004 “One-segment tuner for terrestrial digital TV broadcasting for mobile devices” (Figs. 3-5)

  The variable gain low noise amplifier described in Non-Patent Document 1 employs a circuit format in which the amplifiers are continuously switched by controlling base currents I1, I2, I3, and I4 that flow through the four cascode amplifiers. Specifically, as the control voltage rises, the base current flowing through the cascode amplifier changes continuously at an appropriate ratio of I4 → I3 → I2 → I1, and the total value of the base current flowing simultaneously. Is always constant.

  For example, in FIG. 4 of Non-Patent Document 1, only the base current I4 flows in the region where the control voltage is less than 0.8 [V], and only one cascode amplifier operates. On the other hand, in the region where the control voltage is 0.8 [V] or more and less than 1.2 [V], the two base currents I4 and I3 flow at an appropriate ratio, and the two cascode amplifiers operate. Then, the output currents of the two cascode amplifiers that have been operated are converted into voltages using a resistive load, and the respective voltages are added and output as an amplified signal.

  The variable gain low noise amplifier of Non-Patent Document 1 is configured by a Bi-CMOS (Bipolar Complementary Metal Oxide Semiconductor) process. By using this Bi-CMOS process, an LNA having a voltage gain of about 20 [dB] and a noise figure of about 3 [dB] can be realized by a single-stage cascode amplifier. Since the output stage of the cascode amplifier is a resistive load, the output voltages of the respective cascode amplifiers can be added by connecting the output points of a plurality of cascode amplifiers.

  On the other hand, in order to meet the recent demands for higher speed, smaller size, and lower power consumption of transistors, a variable gain amplifier having a characteristic equivalent to or better than that of the amplifier of Non-Patent Document 1 is provided. It is desired that the semiconductor is miniaturized by a process. In this case, it is difficult to realize an LNA having a voltage gain of 20 [dB] or more and a noise figure of 3 [dB] or less with a single cascode amplifier. Therefore, a technique of connecting a plurality of cascode amplifiers in multiple stages is employed.

  However, when a general resistive load cascode amplifier is used as in Non-Patent Document 1, it is difficult to reduce the noise figure (NF) in the CMOS process, and a desired NF cannot be obtained. Causes the problem of worsening. Therefore, if a noise cancellation type cascode amplifier is used instead of a general cascode amplifier, NF can be reduced even in the CMOS process. However, in the case of this type of cascode amplifier, the output stage is in the form of a source follower, so that the output signals of the respective cascode amplifiers cannot be added at the output stage like a cascode amplifier of a resistive load. Therefore, it is not possible to secure a wide dynamic range while improving the NF by simply connecting a plurality of cascode amplifiers configured by a CMOS process in parallel and performing current control.

  The present invention has been made to solve such problems, and an object of the present invention is to provide a variable gain amplifier that can secure a wide dynamic range by a CMOS process and satisfies a good noise figure. .

  In order to solve the above-described problems, a variable gain amplifier according to the present invention includes a plurality of first-stage amplifiers connected in parallel to one input and performing an amplification operation by a control current flowing through each input, and a plurality of first-stage amplifiers. It has a next-stage amplifier connected to the subsequent stage, and a variable current source that controls the control current flowing to the plurality of first-stage amplifiers so that the total value of the control current flowing at the same time is constant, and the control current flows simultaneously. The output lines of the first-stage amplifier without a plurality are connected to form a plurality of combined output lines, and the plurality of combined output lines are separately input to the plurality of input terminals of the next-stage amplifier. Signals input from a plurality of input terminals are respectively amplified, and the amplified signals are added and output.

  In another aspect of the present invention, each of the plurality of first-stage amplifiers includes a first amplifier that inverts and amplifies the phase of the input signal, and a second amplifier that amplifies the input signal, and outputs the first amplifier. The signal and the output signal of the second amplifier are added and output.

  In still another aspect of the present invention, each of the plurality of first-stage amplifiers further comprises switch means for turning off the operation of the first amplifier and the second amplifier when the control current is not supplied from the variable current source. Yes.

  According to the present invention configured as described above, even if the output stage of the transistor constituting the first stage amplifier is of the source follower type, the first stage amplifier in which the control current does not flow simultaneously, that is, operates simultaneously. Since the output lines of the first-stage amplifiers having no signal are connected to each other, no signal is added to the connected combined output line. The addition of the output signals of the first stage amplifiers operating simultaneously is performed in the next stage amplifier in which the output signals are separately input via a plurality of combined output lines. Thus, a wide dynamic range can be ensured even in a CMOS process variable gain amplifier. In addition, since the total value of the control currents flowing through the plurality of first-stage amplifiers is controlled to be always constant, low noise characteristics and high linearity in the relationship between the control voltage and the gain can be ensured.

  According to another aspect of the present invention, noise generated in the first amplifier (inverting amplifier) of the first-stage amplifier is canceled by being added in reverse phase with the noise output from the second amplifier. Thereby, it is possible to suppress the deterioration of the noise figure in the variable gain amplifier of the CMOS process, and to obtain a good reception sensitivity.

  According to still another aspect of the present invention, the operation of the first amplifier and the second amplifier of the first stage amplifier to which no control current is supplied can be completely turned off by the switch means. As a result, noise can be prevented from being generated from the transistors of the first-stage amplifier that are not involved in the amplification operation, so that deterioration of the noise figure can be suppressed in the variable gain amplifier of the CMOS process, and good reception sensitivity can be obtained. Can do.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram illustrating a configuration example of the variable gain amplifier according to the present embodiment. As shown in FIG. 1, the variable gain amplifier of the present embodiment includes four first-stage LNAs 1 to 4, one next-stage LNA 5, three attenuators 11 to 13, and a variable current source 20. It is configured. All of these configurations are integrated on one IC chip by a CMOS process.

  The four first stage LNAs 1 to 4 correspond to a plurality of first stage amplifiers in the present invention. The four first-stage LNAs 1 to 4 are connected in parallel to one input terminal IN, and are input to the first-stage amplifiers 1 to 4 by the control currents IB1 to IB4 flowing from the variable current source 20 respectively. Amplifying operation is performed.

  The three attenuators 11 to 13 correspond to the level adjuster in the present invention. The three attenuators 11 to 13 are connected in parallel to one input terminal IN, and are connected to the input sides of the second to fourth first stage amplifiers 2 to 4 among the four first stage amplifiers 1 to 4. Has been. The three attenuators 11 to 13 adjust the level of a signal input from one input terminal IN so that the levels of signals input to the four first-stage LNAs 1 to 4 are different from each other. is there.

  Specifically, the attenuators 11 to 13 attenuate the signal input from one input terminal IN. The attenuation amounts of the attenuators 11 to 13 are different from each other, and are set so that the attenuation amount increases in the order of the first attenuator 11 <the second attenuator 12 <the third attenuator 13. For example, when the variable gain ranges of the four first-stage LNAs 1 to 4 are about 20 [dB], the attenuation amount of the first attenuator 11 is 20 [dB] and the attenuation amount of the second attenuator 12 is 40 [dB]. ], The attenuation amount of the third attenuator 13 can be set to 60 [dB].

  In this case, the first first-stage LNA 1 amplifies a signal input from one input terminal IN. The second first-stage LNA 2 amplifies a signal input from one input terminal IN and attenuated by 20 [dB] by the first attenuator 11. The third first-stage LNA 3 amplifies a signal input from one input terminal IN and attenuated by 40 [dB] by the second attenuator 12. The fourth first-stage LNA 4 amplifies a signal that is input from one input terminal IN and is attenuated by 60 [dB] by the third attenuator 13.

  Although an example in which three attenuators 11 to 13 are connected in parallel to one input terminal IN has been described here, the present invention is not limited to this. For example, three attenuators 11 to 13 are cascade-connected to one input terminal IN, and signals are taken out from output taps of the attenuators 11 to 13 of each stage to obtain second to fourth first stage LNAs 2 to 4. May be input respectively. In this case, for example, if the attenuation amount of each attenuator 11 to 13 is set to 20 [dB], a signal attenuated by 20 [dB] is taken out from the output tap of the first attenuator 11 and the output of the second attenuator 12 is output. From the tap, a signal attenuated by a total of 40 [dB] in two stages is extracted, and from the output tap of the third attenuator 13, a signal attenuated by a total of 60 [dB] is extracted.

  In addition, although the configuration in which the attenuators 11 to 13 are connected to some of the first stage LNAs 2 to 4 among the four first stage LNAs 1 to 4 has been described here, the present invention is not limited to this. For example, you may make it connect an attenuator with respect to all the first stage LNA1-4.

  The variable current source 20 receives a control voltage VAGC for gain adjustment from an AGC circuit (not shown) and, based on the control voltage VAGC, controls currents IB1 to IB4 and one next current to be passed through the four first-stage LNA1 to LNA4. A control current IB5 that flows through the stage LNA5 is generated. At this time, the variable current source 20 controls so that the total value of the control currents IB1 to IB4 flowing through the four first-stage LNAs 1 to 4 is always constant regardless of the magnitude of the control voltage VAGC.

  FIG. 4 is a diagram illustrating an example of the control currents IB1 to IB4 flowing in the four first-stage LNA1 to LNA4. As can be seen from FIG. 4, in the region where the control voltage VAGC is less than about 1.05 [V], only the fourth control current IB4 flows, and only the fourth first-stage LNA4 operates. In the region where the control voltage VAGC is about 1.05 [V] or more and less than about 1.4 [V], the fourth control current IB4 and the third control current IB3 flow at an appropriate ratio. The first-stage LNA 4 and the third first-stage LNA 3 operate. In the region where the control voltage VAGC is about 1.4 [V] or more and less than about 1.45 [V], only the third control current IB3 flows, and only the third first-stage LNA3 operates.

  Thus, depending on the value of the control voltage VAGC, there is a region where the fourth control current IB4 and the third control current IB3 flow simultaneously. Similarly, there is a region where the third control current IB3 and the second control current IB2 flow simultaneously, and there is a region where the second control current IB2 and the first control current IB1 flow simultaneously. On the other hand, the fourth control current IB4 and the first control current IB1 or the second control current IB2 do not flow simultaneously, and the third control current IB3 and the first control current IB1 flow simultaneously. There is nothing.

  Here, the variable current source 20 has a current amount when the first to fourth control currents IB1 to IB4 are individually supplied, and a current amount when the fourth control current IB4 and the third control current IB3 are simultaneously supplied. The total amount of current, the total amount of current when the third control current IB3 and the second control current IB2 are simultaneously flowed, and the time of simultaneously flowing the second control current IB2 and the first control current IB1 Control is performed so that the total amount of current is always the same when any control voltage VAGC is supplied.

  As described above, the signals input from one input terminal IN and the signals obtained by deeply attenuating them by 20 [dB] by the three attenuators 11 to 13 are amplified by the four first-stage LNAs 1 to 4. Thus, by controlling the control currents IB1 to IB4 flowing through the first-stage LNAs 1 to 4, the amplification by the first-stage LNAs 1 to 4 is continuously switched. Specifically, as the control voltage VAGC increases, control currents IB1 to IB4 flowing through the first-stage LNA1 to LNA4 are controlled to continuously change at an appropriate ratio of IB4 → IB3 → IB2 → IB1.

  By doing in this way, the dynamic range which can secure only about 20 [dB] with each of the first stage LNA1 to 4 is wide, and the wide dynamic range of about 80 [dB] as a whole of the four first stage LNA1 to 4 is provided. Can be secured. In addition, by making the total value of the control currents IB1 to IB4 flowing simultaneously through the four first-stage LNA1 to L4 always constant, low noise characteristics and high linearity can be ensured.

  The variable current source 20 also generates off-currents IB1A to IB4A indicating that when a part of the control currents IB1 to IB4 is not flowing to a part of the first stage LNA1 to 4, and outputs it to the first stage LNA1 to LNA4. . Specifically, the variable current source 20 generates the first off-current IB1A and the second control current IB2 as the second initial stage when the first control current IB1 does not flow through the first initial stage LNA1. When not flowing through the LNA2, the second off-current IB2A is generated. When the third control current IB3 is not passed through the third first stage LNA3, the third off-current IB3A is generated, and when the fourth control current IB4 is not passed through the fourth first stage LNA4, the fourth Off current IB4A.

  The next stage LNA 5 corresponds to the next stage amplifier according to the present invention, and is connected to the subsequent stage of the four first stage LNAs 1 to 4. Here, among the four first-stage LNAs 1 to 4, the output lines of the first-stage LNAs in which the control currents IB1 to IB4 do not flow simultaneously are connected to form a plurality of combined output lines L1 and L2, The combined output lines L1 and L2 are separately input to the plurality of input terminals IN1 and IN2 of the next stage LNA5.

  Specifically, the first combined output line L1 is formed by connecting the output lines of the first initial stage LNA1 and the third initial stage LNA3 in which the control currents IB1 and IB3 do not flow simultaneously. Further, the second combined output line L2 is formed by connecting the output lines of the second initial stage LNA2 and the fourth initial stage LNA4 in which the control currents IB2 and IB4 do not flow simultaneously. Then, the two combined output lines L1 and L2 are separately input to the plurality of input terminals IN1 and IN2 of the next stage LNA5. The next-stage LNA 5 amplifies the signals input from the two input terminals IN1, IN2, respectively, adds the amplified signals, and outputs the result.

  Next, the circuit configuration of the first-stage LNAs 1 to 4 according to the present embodiment will be described. Since the first-stage LNAs 1 to 4 have the same circuit configuration, the configuration of the first first-stage LNA 1 will be described below as a representative. FIG. 2 is a circuit diagram showing a configuration example of the first first-stage LNA 1.

  In FIG. 2, the pMOS transistor P1 and the nMOS transistor N1 connected to the input terminal IN constitute an inverting amplifier. The inverting amplifiers P1 and N1 invert and amplify the phase of the signal input from the input terminal IN. The amplified signal is output to the next stage via the coupling capacitor C1. The nMOS transistor N4 connected to the next stage of the coupling capacitor C1 is a source follower buffer amplifier. The inverting amplifiers P1, N1 and the buffer amplifier N4 constitute the first amplifier 50 of the present invention.

  The nMOS transistors N2 and N3 connected in parallel with the inverting amplifiers P1 and N1 with respect to the input terminal IN are cascode amplifiers and correspond to the second amplifier 60 of the present invention. The nMOS transistor N2 corresponding to the preceding stage of the cascode connection is a common source amplifier, and the nMOS transistor N3 corresponding to the subsequent stage of the cascode connection is a grounded gate amplifier. The second amplifier 60 amplifies a signal input from the input terminal IN. The nMOS transistors N5 and N6 are bias circuits for applying a bias for grounding the gate to the transistor N3 corresponding to the subsequent stage of the cascode connection of the second amplifier 60.

  Here, the output of the first amplifier 50 (source of the transistor N4) and the output of the second amplifier 60 (drain of the transistor N3) are connected and connected to the output terminal OUT1 of the first first stage LNA1. As for the first amplifier 50, the input signal is amplified in reverse phase by the inverting amplifiers P1 and N1, and the amplified signal is output in phase (no amplification) to the output terminal OUT1 by the source follower of the buffer amplifier N4. For this reason, the signal output to the output terminal OUT1 is out of phase with the input signal. On the other hand, with respect to the second amplifier 60, the input signal is amplified in reverse phase by the common source amplifier N2, and the amplified signal is output in phase (no amplification) to the output terminal OUT1 through the common gate amplifier N3. For this reason, the signal output to the output terminal OUT1 is out of phase with the input signal. Thus, since the signal amplified by the first amplifier 50 and the signal amplified by the second amplifier 60 are in phase at the output terminal OUT1 of the first stage LNA1, they are not canceled out from each other.

  On the other hand, the noise generated at the sources and drains of the inverting amplifiers P1 and N1 is output in phase to the output terminal OUT1 of the first stage LNA1 through the coupling capacitor C1 and the buffer amplifier N4 (no amplification). On the other hand, the noise that is divided (attenuated) by the resistor R1 and the signal source resistor (not shown) and output in phase to the input terminal IN is amplified in reverse phase by the common source amplifier N2. For this reason, the phase of noise generated in the inverting amplifiers P1 and N1 and output to the output terminal OUT1 through the buffer amplifier N4 is opposite to the phase of noise output to the output terminal OUT1 through the second amplifier 60. The noise generated in the inverting amplifiers P1 and N1 can be canceled at the output terminal OUT1. For this reason, the noise is lower than that of a conventional cascode amplifier in which bipolar transistors are simply cascode-connected.

  The nMOS transistors N7 and N8 are current mirror circuits, and the control current IB1 is input to the drain on one transistor N7 side as a reference current, and the same control current IB1 flows to the drain on the other transistor N8 side. The pMOS transistors P2 to P5 also constitute a current mirror circuit, and the control current IB1 output from the nMOS transistor N8 is input to the drain on one transistor P5 side as a reference current, and the other transistors P2 to P4 side are input. A current proportional to the control current IB1 flows through the drain.

  As described above, the current proportional to the control current IB1 is supplied to the first amplifier 50, the second amplifier 60, and the bias circuits N5 and N6 by the combination of the two current mirror circuits N7 to N8 and P2 to P5. Yes. That is, the control current IB1 input from the variable current source 20 passes through the two current mirror circuits N7 to N8 and P2 to P5, and the current proportional to the control current IB1 is the first amplifier 50, the second amplifier 60, and the bias. This is supplied to the circuits N5 and N6. Thereby, the gain of the first stage LNA1 is controlled by the control current IB1.

  The inverters INV1, INV2, the pMOS transistor P6, and the nMOS transistors N9 to N10 constitute the switch means of the present invention. This switch means is for completely turning off the operations of the first amplifier 50 and the second amplifier 60 when the control current IB1 is not supplied from the variable current source 20.

  The two inverters INV1 and INV2 are connected in cascade, and the off-current IB1A is input to the first-stage inverter INV1. The output terminal of the previous inverter INV1 is connected to the gate of the pMOS transistor P6. The drain of the pMOS transistor P6 is connected to the gates of the pMOS transistors P2 to P5 constituting the current mirror circuit. Note that the sources of the pMOS transistors P2 to P6 are all connected to the power supply voltage VDD.

  On the other hand, the output terminal of the subsequent inverter INV2 is connected to the gates of the nMOS transistors N9 and N10. The drain of the nMOS transistor N9 is connected to the gate of the transistor N4 constituting the first amplifier 50, and the drain of the nMOS transistor N10 is connected to the gate of the transistor N3 constituting the second amplifier 60. The sources of the nMOS transistors N9 and N10 are connected to the ground.

  The input terminal of the previous inverter INV1 is connected to the drain of the nMOS transistor N11. The gate of the nMOS transistor N11 is connected to the input ends (input ends of the control current IB1) of the current mirror circuits N7 and N8, and the source is connected to the ground.

  Here, the operation of the switch means configured as described above will be described. When the control current IB1 is not supplied from the variable current source 20 (the control current IB1 is at a low level), the off-current IB1A is supplied from the variable current source 20. Then, the off-current IB1A whose phase has been inverted by the previous inverter INV1 is supplied to the gate of the pMOS transistor P6. At this time, the output terminal of the inverter INV1 in the previous stage is at a low level, and the pMOS transistor P6 is turned on.

  As a result, a high level signal output from the drain of the pMOS transistor P6 is supplied to the gates of the pMOS transistors P2 to P5 constituting the current mirror circuit. Accordingly, the pMOS transistors P2 to P5 are all turned off. By turning off the pMOS transistors P2 to P5, the first amplifier 50 (inverting amplifiers P1 and N1), the second amplifier 60, and the bias circuits N5 and N6 can be completely disconnected from the power supply voltage VDD.

  On the other hand, the off-current IB1A whose phase has been restored by the subsequent inverter INV2 is supplied to the gates of the nMOS transistors N9 and N10. As a result, a high level signal output from the inverter INV2 is supplied to the gates of the nMOS transistors N9 and N10. Therefore, both the nMOS transistors N9 and N10 are turned on. Therefore, both the transistors N3 and N4 are completely turned off because the gates are at a low level.

  As described above, when the control current IB1 is not supplied from the variable current source 20, the first amplifier 50, the second amplifier 60, and the bias circuits N5 and N6 are completely disconnected from the power supply voltage VDD. Further, both the transistor N4 constituting the first amplifier 50 and the transistor N3 constituting the second amplifier 60 are completely turned off. Thereby, the operation of the first amplifier 50 and the second amplifier 60 can be completely turned off.

  When the control current IB1 is supplied from the variable current source 20 to the first-stage LNA1, the nMOS transistor N11 is turned on, and the off-current IB1A is drawn to the ground GND through the nMOS transistor N11.

  Next, the circuit configuration of the next-stage LNA 5 according to the present embodiment will be described. FIG. 3 is a circuit diagram showing a configuration example of the next-stage LNA 5. In FIG. 3, C21 and C22 are coupling capacitors connected to the two combined output lines L1 and L2. A cascode amplifier is connected to each of the two coupling capacitors C21 and C21.

  The cascode amplifier connected to the first composite output line L1 via the coupling capacitor C21 is composed of two nMOS transistors N21 and N23 connected in cascode. Further, the cascode amplifier connected to the second composite output line L2 via the coupling capacitor C22 includes two cascode-connected nMOS transistors N22 and N23.

  The nMOS transistor N23 is a two-stage amplifier of a cascode amplifier that amplifies the signal supplied from the first combined output line L1, and a two-stage cascode amplifier that amplifies the signal supplied from the second combined output line L2. It also serves as an eye amplifier. A load resistor RL is connected to the drain side of the nMOS transistor N23, that is, the output stage of the cascode amplifier (the output terminal OUT side of the next stage LNA5).

  That is, the next-stage LNA 5 includes a signal supplied from the first combined output line L1 through one input terminal IN1, and a signal supplied from the second combined output line L2 through the other input terminal IN2. Are respectively amplified by two cascode amplifiers, and the amplified signals are added and output from the output terminal OUT.

  The nMOS transistors N24 and N25 are transistors for applying a bias for grounding the gate to the nMOS transistor N23 corresponding to the latter stage of the cascode connection. The nMOS transistor N26 is one transistor constituting a current mirror circuit, and constitutes a current mirror circuit together with the nMOS transistors N21 and N22 corresponding to the previous stage of cascode connection.

  That is, the control current IB5 is input as a reference current to the drain of the nMOS transistor N26, and a current proportional to the control current IB5 flows through the drains of the nMOS transistors N21 and N22 corresponding to the previous stage of the cascode amplifier. That is, a current proportional to the control current IB5 input from the variable current source 20 to the nMOS transistor N26 is supplied to the two cascode amplifiers connected to the nMOS transistor N26 in a current mirror connection. Thereby, the gain of the next stage LNA5 is controlled by the control current IB5.

  As described above in detail, in the present embodiment, the first stage LNA1 to 4 and the next stage LNA5 have a two-stage configuration, and the control currents IB1 to IB4 do not flow simultaneously, that is, operate simultaneously. The output lines of the first stage LNA1 to LNA4 that are not to be connected are connected to each other, and the combined output lines L1 and L2 are respectively input to the next stage LNA5. Then, the addition of the output signals of the first stage LNA 1 to 4 operating simultaneously is performed in the next stage amplifier 5.

  As a result, even in a CMOS process variable gain amplifier in which the output stage is a source follower, the output signals of the first stage amplifiers 1 to 4 operating at the same time can be added in the next stage amplifier 5, so that a wide dynamic range can be obtained. Can be secured. In addition, since the total value of the control currents IB1 to IB4 flowing through the plurality of first-stage LNAs 1 to 4 is controlled to be always constant, low noise characteristics and high linearity in the relationship between the control voltage and the gain are ensured. be able to.

  Further, according to the present embodiment, the noise generated in the inverting amplifiers P1 and N1 of the first stage LNA1 to LNA4 is opposite to the noise output from the second amplifier 60 connected in parallel to the inverting amplifiers P1 and N1. It is offset by adding in phase. Thereby, the deterioration of the noise figure can be suppressed in the first stage LNA1 to LNA4 of the CMOS process.

  Furthermore, according to the present embodiment, the operations of the first amplifier 50 and the second amplifier 60 of the first stage LNA1 to LNA1 to which the control currents IB1 to IB4 are not supplied can be completely turned off by the switch means. As a result, noise can be prevented from being generated from the transistors of the first-stage LNAs 1 to 4 that are not involved in the amplification operation, so that deterioration of the noise figure can be suppressed in the first-stage LNAs 1 to 4 of the CMOS process.

In general, the overall noise figure NF when the amplifiers are cascaded is given by the following equation.
NF = NF1 + (NF2-1) / G1 + (NF3-1) / G1 * G2 +.
Here, NF1 is the noise figure of the first stage amplifier, NF2 is the noise figure of the second stage amplifier, and NF3 is the noise figure of the third stage amplifier. G1 is the gain of the first-stage amplifier, and G2 is the gain of the second-stage amplifier.

As can be seen from the above equation, to reduce the noise figure NF of the entire amplifier:
(1) Reduce the noise figure NF1 of the first-stage amplifier. (2) Increase the gain G1 of the first-stage amplifier. In this embodiment, it is particularly required to reduce the noise figure of the first stage amplifiers 1 to 4. On the other hand, in this embodiment, since the noise figure of the first stage amplifiers 1 to 4 can be reduced as described above, the noise figure of the entire variable gain amplifier can be reduced and good reception sensitivity can be obtained. Can do.

  In the above embodiment, the number of the first-stage LNAs 1 to 4 is four, but this is only an example. In the above embodiment, the outputs of the two first-stage LNAs are connected to form a combined output line, but this is also merely an example. That is, as long as the first stage LNAs in which control currents flow simultaneously, the outputs of three or more first stage LNAs may be connected to form a combined output line.

  In the above embodiment, an example in which at most two control currents of the four control currents IB1 to IB4 are simultaneously supplied has been described. However, the present invention is not limited to this. For example, when the number of first stage LNAs is more than four, there may be a case where three or more control currents are simultaneously supplied.

  The variable gain amplifier of the above embodiment is suitable for use in, for example, an RF-AGC circuit of a radio tuner, but can be applied to other than an RF-AGC circuit. When applied to other than the RF-AGC circuit, an amplifier may be connected instead of connecting the attenuators 11 to 13 to the input stages of the second to fourth first stage LNAs 2 to 4. That is, in the above embodiment, an example in which a dynamic range of 80 [dB] is secured in total by attenuating the input signal by 20 [dB] has been described. Therefore, a dynamic range of 80 [dB] may be secured. In this case, the amplifier used instead of the attenuators 11 to 13 constitutes the level adjuster of the present invention.

  Further, in the above-described embodiment, the example in which the switching means is configured by the inverters INV1 and INV2, the pMOS transistor P6, and the nMOS transistors N9 to N10 illustrated in FIG. 2 is described, but this is only an example. For example, the switching means may be constituted by the inverters INV1, INV2 and the pMOS transistor P6. In this case, at least when the control currents IB1 to IB4 are not supplied from the variable current source 20, the first amplifier 50, the second amplifier 60, and the bias circuits N5 and N6 can be completely disconnected from the power supply voltage VDD. Since the control currents IB1 to IB4 are not supplied, the amplification operation is not performed. In that case, however, the deterioration of the noise figure can be suppressed by completely disconnecting the transistor from the power supply voltage VDD.

  Alternatively, the nMOS transistors N9 to N10 may constitute switch means. In this case, at least the transistor N4 constituting the first amplifier 50 and the transistor N3 constituting the second amplifier 60 are all turned off because the gate is at a low level. Thereby, when the control currents IB1 to IB4 are not supplied from the variable current source 20, it is possible to suppress the deterioration of the noise figure by completely turning off the operations of the first amplifier 50 and the second amplifier 60. it can.

  In the above-described embodiment, an example in which signals are added in the output stage of the previous-stage transistor in the cascode connection in the two cascode amplifiers constituting the next-stage LNA 5 has been described. However, the present invention is not limited to this. For example, signals may be added at the output stage of the rear stage transistor in the cascode connection.

  In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. In other words, the present invention can be implemented in various forms without departing from the spirit or main features thereof.

  The present invention is useful for a variable gain amplifier in which a plurality of amplifiers are connected to increase the variable gain range. For example, the variable gain amplifier of the present invention is suitable for use in a radio tuner mounted on a mobile body such as an in-vehicle device or a mobile phone.

It is a figure which shows the structural example of the variable gain amplifier by this embodiment. It is a circuit diagram which shows the structural example of the first stage LNA by this embodiment. It is a circuit diagram which shows the structural example of the next stage LNA by this embodiment. It is a figure which shows the example of the control current which flows into four first stage LNAs.

Explanation of symbols

1-4 First-stage LNA
5th stage LNA
11-13 attenuator 20 variable current source 50 first amplifier 60 second amplifier P1, N1 inverting amplifier N4 buffer amplifier N2, N3 cascode amplifier INV1, INV2 inverter constituting switch means P6 pMOS transistor constituting switch means N9-N10 switch NMOS transistors N21 to N23 constituting two sets of cascode amplifiers

Claims (3)

A plurality of first-stage amplifiers connected in parallel to one input and performing an amplification operation by a control current flowing through each of the inputs;
A level adjuster that is connected to the input side of the first-stage amplifier for at least some of the plurality of first-stage amplifiers, and that adjusts the levels of signals input to the first-stage amplifiers to be different from each other;
A next-stage amplifier connected to a subsequent stage of the plurality of first-stage amplifiers;
A variable current source for controlling the control current flowing through the plurality of first-stage amplifiers, and making the total value of the control current flowing simultaneously constant;
Among the plurality of first-stage amplifiers, output lines of the first-stage amplifiers in which the control current does not flow simultaneously are connected to form a plurality of combined output lines, and the plurality of combined output lines are connected to the plurality of first-stage amplifiers. To be input separately at the input end of
The next-stage amplifier amplifies signals input from the plurality of input terminals, adds the amplified signals, and outputs the result. Each of the plurality of first stage amplifiers is
A first amplifier for inverting and amplifying the phase of the input signal;
A second amplifier for amplifying the input signal,
2. The variable gain amplifier according to claim 1, wherein the output signal of the first amplifier and the output signal of the second amplifier are added and output. Each of the plurality of first stage amplifiers is
3. The variable gain according to claim 2, further comprising switch means for turning off the operations of the first amplifier and the second amplifier when the control current is not supplied from the variable current source. amplifier.