WO2008156156A1

WO2008156156A1 - Variable gain amplifier

Info

Publication number: WO2008156156A1
Application number: PCT/JP2008/061285
Authority: WO
Inventors: Kazuhisa Ishiguro
Original assignee: Nsc Co., Ltd.
Priority date: 2007-06-21
Filing date: 2008-06-13
Publication date: 2008-12-24
Also published as: JP2009005055A

Abstract

A variable gain amplifier is provided with a plurality of first stages (LNA1-4) connected in parallel with each other for one input terminal (IN), a next stage (LNA5) connected with them at a later stage, a variable electric current source (20), which controls control electric currents (IB1-IB4) flowing through the first stages (LNA1-4) and makes the total value of concurrently flowing control electric currents constant. Output lines of the first stages (LNA1-4) through which control electric currents do not concurrently flow are connected with each other to form a plurality of synthesized output lines (L1, L2). These are made to separately input to a plurality of input terminals of a next stage amplifier (5). The next stage amplifier (5) amplifies signals input from the plurality of input terminals, respectively, adds each amplified signal, and outputs it.

Description

Variable gain amplifier

Technical field

The present invention relates to a variable gain amplifier, and is particularly suitable for use in a variable gain amplifier in which a plurality of amplifiers are connected to increase the variable gain range.

Background art

book

Normally, a radio communication device such as a radio receiver uses an AGC (Automatic Gain Control) circuit to adjust the gain of the received signal. RF (Radio Frequency) installed in the high-frequency stage — The AGC circuit adjusts the gain of the high-frequency signal (antenna input signal) received by the antenna to keep the received signal level constant. . R F — A G C can be realized by controlling the attenuation in the antenna damping circuit and the gain of L N A (Low Noise Amplifier).

In particular, in radio tuners mounted on mobile units such as in-vehicle devices and mobile phones, it is desirable to increase the LNA gain variable width (dynamic range) in order to support a wide range of mobile reception power. It is. For example, when the received power is small, high gain and low noise characteristics are required. On the other hand, when the received power is large, a high linearity is required in which the relationship between the control voltage of AGC and the decibel gain controlled thereby is linear.

In order to satisfy these two requirements and to obtain a wide dynamic range, four cascode amplifiers are connected in parallel, and these cascode amplifiers are used by switching them continuously according to the received power. A variable gain low noise amplifier configured as described above has been proposed (see Non-Patent Document 1, for example). Power The code amplifier itself has essentially no feedback from output to input, so L

It is frequently used as NA.

Non-Patent Document 1: Sharp Technical Bulletin No. 88: Issued in April 2004 “One-segment tuner for terrestrial digital TV broadcasting for mobile devices j (Figures 3 to 5)

In this variable gain low-noise amplifier described in Non-Patent Document 1, the amplifiers are continuously controlled by controlling the base currents I 1, 1 2, 1 3, and I 4 flowing through the four cascode amplifiers. A circuit format that switches automatically is adopted. Specifically, as the control voltage increases, the base current flowing through the cascode amplifier is continuously changed at an appropriate ratio from I 4 → I 3 → I 2 → I 1. In this way, the total value of the base current that flows simultaneously is always constant.

For example, in Fig. 4 of Non-Patent Document 1, only the base current I4 flows in the region where the control voltage is less than 0.8 [V], and only one force cord amplifier operates. On the other hand, in the region where the control voltage is 0.8 [V] or more and less than 1.2 [V], two base currents I4 and I3 flow at an appropriate ratio, and the two cascode amplifiers operate. . Then, the output currents of the two force-scoring amplifiers that have been operated are converted into voltages using a resistive load, and the respective voltages are added and output as an amplified signal. Disclosure of the invention

The variable gain low noise amplifier of Non-Patent Document 1 is formed by a Bi_CMOS (Bipolar Complementary Metal Oxide Semiconductor) process. Using this Bi-CMOS process, LNA with a voltage gain of about 20 [dB] and a noise figure of about 3 [dB] can be realized with a single-stage cascode amplifier. Also, since the output stage of the cascode amplifier is a resistive load, By connecting the output points of multiple cascade amplifiers, the output voltage of each force 3-K amplifier can be added.

On the other hand, in order to meet the recent demands for faster transistors, smaller size, and lower power consumption, the variable gain has the same or better characteristics than the amplifier of Non-Patent Document 1. When it is desired that the amplifier is composed of a semiconductor miniaturized by a CMOS process, the voltage gain is 20 [dB] or more and the noise figure is 3 [dB] or less. However, it is difficult to realize NA with a single-stage cascode amplifier. Therefore, a technique of connecting a plurality of force cord amplifiers in multiple stages is used.

However, as in Non-Patent Document 1, it is difficult to reduce the noise figure (NF) in the field σ using a general resistive load cascode amplifier and the CMOS process. Since the NF cannot be obtained, the reception sensitivity deteriorates, resulting in a la problem. Therefore, if a noise cell type power code amplifier is used instead of a general cascode amplifier, ΝF can be reduced even in the C Moss process. In the case of this type of cascode amplifier, the output stage is in the form of a soot port, so the output of each cascode amplifier is the same as that of a resistive load. The signals cannot be added at the output stage. Therefore, it is not possible to secure a wide dynamic range while improving NF by simply connecting multiple force-stage amplifiers composed of CMOS processes in parallel and controlling the current.

The present invention has been made to solve such problems, and provides a variable gain amplifier that can secure a wide dynamic range in a CMOS process and satisfies a good noise figure. Objective.

In order to solve the above-described problems, the variable gain amplifier of the present invention is connected in parallel to one input, and performs an amplification operation by a control current flowing through each input. Control the control current that flows to the multiple first-stage amplifiers, the next-stage amplifier that is connected to the subsequent stage of the multiple first-stage amplifiers, and the constant value of the control current that flows simultaneously. A variable current source is connected, and the output lines of the first-stage amplifier that do not allow the control current to flow simultaneously are connected together to form multiple composite output lines, and the multiple composite output lines are connected to the multiple inputs of the next-stage amplifier. The next stage amplifier amplifies signals input from a plurality of input terminals, adds the amplified signals, and outputs the result.

In another aspect of the present invention, each of the plurality of first-stage amplifiers includes a first amplifier that inverts and amplifies the phase of the input signal, and a second amplifier that amplifies the input signal. The output signal and the output signal of the second amplifier are added and output.

In yet another aspect of the present invention, each of the plurality of first-stage amplifiers is a switch for turning off the operation of the first amplifier and the second amplifier when no control current is supplied from the variable current source. H further means.

According to the present invention configured as described above, even if the output stage of the transistors constituting the first stage amplifier is in the form of a source follower, the first stage amplifier, that is, the control current does not flow simultaneously. Thus, since the output lines of the first-stage amplifiers that do not operate simultaneously are connected, no signal is added on the connected combined output line. The addition of the output signals of the first-stage amplifiers operating simultaneously is performed in the next-stage amplifier in which the output signals are input separately via a plurality of combined output lines. As a result, a wide dynamic range can be secured even in the variable gain amplifier of the CMOS process. In addition, since the total value of the control currents flowing through the multiple first-stage amplifiers is controlled to be constant at all times, low noise characteristics and high linearity in the relationship between control voltage and gain can be ensured. . According to another aspect of the present invention, the first amplifier (inverting amplifier) of the first stage amplifier The noise generated in step 1 is canceled out by adding it in reverse phase to the noise output from the second amplifier. As a result, it is possible to suppress the deterioration of the noise figure in the variable gain amplifier of the CMOS process, and to obtain good reception sensitivity.

Further, according to still another aspect of the present invention, the operation of the first amplifier ^ and the second amplifier of the first stage amplifier to which no control current is supplied can be completely turned off by the switch means. Monkey. As a result, it is possible to prevent noise from being generated from the transistor of the first-stage amplifier that is not involved in the amplification operation, so that it is possible to suppress the deterioration of the noise figure in the variable gain amplifier of the CMOS process. You can get a good reception sensitivity. Brief Description of Drawings

FIG. 1 is a diagram illustrating a configuration example of the variable gain amplifier according to the present embodiment. FIG. 2 is a circuit diagram showing a configuration example of the first-stage LNA according to the present embodiment. FIG. 3 is a circuit diagram showing a configuration example of the next-stage LNA according to the present embodiment. FIG. 4 is a diagram showing an example of the control current flowing through the four first-stage LNAs. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a variable gain amplifier according to this embodiment. As shown in FIG. 1, the variable gain amplifier of the present embodiment includes four first-stage LNA 1 to 4, one next-stage LNA 5, three attenuators 11 to 1; 1 3 and variable. All these configurations, which are configured with a current source 20, are integrated on a single IC chip by a CMOS process.

The four first stage LNAs 1 to 4 correspond to a plurality of first stage amplifiers in the present invention. These four first-stage LNA 1 to 4 are connected to one input terminal IN. Control current I connected in parallel to each other and flown from variable current source 20 to each

A signal input to the first stage amplifier 14 is amplified by B 1 to I B 4.

The three attenuators 11 to 13 correspond to the Revenore g sizing device according to the present invention. These three attenuators 11 to 13 are connected in parallel to one input terminal IN, and the second of the four first stage amplifiers 1 to 4 is the second one.

To 4th first stage amplifier 2 to 4 are connected to the input side. The three attenuators 1 1 to 1 3 are the signals input from the-input terminal IN so that the levels of the signals input to the four first-stage LNAs 1 to 4 are different. To adjust the level of

Specifically, attenuators 1 1 to 1; 1 3 attenuate the signal input from one input terminal IN. Ο Attenuators 1 1 to 1 3 have different attenuation amounts. Actuator 1 1 <Second attenuator 1 2 <First

Attenuator of 3 1 Attenuation is set so that the magnitude is smaller in the order of 3

. For example, the variable gain range of 4 first stage L N A 1 to 4 is 2 0 [dB

], The attenuation of the first attenuator 1 1 is 2 0 [dB], the attenuation of the second attenuator 1 2 is 4 0 [dB], and the third attenuator 1 3 The attenuation can be set to 6 0 [dB].

The first first stage L NA 1 amplifies the signal input from one input terminal IN.-3 o The second first stage L NA 2 is input from the input terminal IN of the first input. Attenuator 1 1 2 0 [d B] Amplifies the attenuated signal o The third first stage NA 3 is input from one input terminal IN and the second attenuator 1 2 4 0 [d B] Amplifies the attenuated signal. The fourth first stage

L N A 4 amplifies the signal input from one input terminal I N and attenuated 60 [dB] by the third attenuator 1 3.

In ^-, three attenuators 1 1 to 1 3 are connected to one input terminal IN. However, the present invention is not limited to this example. For example, three attenuators 1 1 to 1 3 are cascade-connected to one input terminal IN, and signals are extracted from the output taps of the attenuators 11 to 13 of each stage. Input may be made to 2nd to 4th first stage LNAs 2 to 4, respectively. In this case, for example, if the attenuation of each of the attenuators 11 to 13 is set to 20 [dB], the output tap of the first attenuator 11 will be attenuated by 20 [dB]. The output signal of the second attenuator 12 is extracted from the output tab of the second attenuator 1 2 in a total of 2 stages, and is attenuated by 40 [dB]

Attenuator of 3 1 3 A total of 6 0 [dB] attenuated signal is extracted from the output tap of 3

Further, here, the configuration in which the attenuators 11 to 13 are connected to some of the first stages L N A 2 out of the four first stages N A 1 to 4 is not limited thereto. For example, connect attenuators to all first-stage L N A 1 to 4 or set them to 0.

The variable current source 20 receives a control voltage V A G C for gain adjustment from an A G C circuit (not shown), and four initial stages based on the control voltage V A G C

A control current I B 1 to I B 4 flowing through L N A 1 to 4 and a control current I B 5 flowing to one next stage L N A 5 are generated. At this time, the variable current source 20 is set so that the total value of the control currents IB 1 to IB 4 flowing in the four first-stage LNAs:! To 4 is always constant regardless of the magnitude of the control voltage VAGC. Control. FIG. 4 is a diagram illustrating an example of the control currents I B 1 to I B 4 flowing in the four first-stage L N A1 to L N A1 to L N Al. As can be seen from Figure 4, the control voltage V A G C is about 1.

In the region below 0 [V], only the fourth control current I B 4 flows and the fourth first stage

Only the LNA 4 operates. Also, in the region where the control voltage VAGC is higher than about 105 [V] and lower than about 1.4 [V], the fourth control current IB4 and the third control current IB3 Flows at an appropriate ratio, the 4th first stage LNA 4 and the 3rd first Stage LNA 3 operates. In the region where the control voltage VAGC is about 1.4 [V] or more and less than about 1.45 [V], only the third control current IB3 flows, and only the third first stage LNA3 operates. .

Thus, depending on the value of the control voltage V A G C, there is a region where the fourth control current I B 4 and the third control current I B 3 flow simultaneously. Similarly, there is a region where the third control current I B 3 and the second control current I B 2 flow simultaneously, and there is a region where the second control current I B 2 and the first control current I B 1 flow simultaneously. On the other hand, the fourth control current IB 4 and the first control current IB 1 or the second control current IB 2 do not flow at the same time, and the third control current IB 3 and the first control current IB 2 do not flow simultaneously. IB 1 does not flow at the same time.

Here, the variable current source 20 has the amount of current when the first to fourth control currents IB 1 to IB 4 individually flow, the fourth control current IB 4 and the third control current IB. 3 and the third control current IB 3 and the second control current IB 2 at the same time, and the second control current IB 2 Control is performed so that the total amount of current when the first control current IB 1 is supplied simultaneously is always the same regardless of what control voltage VAG C is supplied.

As described above, four first stage L NA 1 signals input from one input terminal IN and signals attenuated deeply by 2 0 [dB] by 3 attenuators 1 1 to 1 3 Amplification is performed at ~ 4, and by controlling the control currents IB1 ~ IB4 flowing to the first stage LNA1 ~ 4, the amplification by the first stage LNA1 ~ 4 can be switched continuously. I am doing it. Specifically, as the control voltage V AG C increases, the control current flowing in the first-stage LNA 1 to 4 IB 1 to IB 4 forces IB 4 → IB 3 → IB 2 → IB 1 continuously at an appropriate ratio Control to change to.

In this way, one of the first-stage LNA 1 to 4 is 2 0 [d B] A wide dynamic range of about 80 [dB] can be secured for the four first-stage LNAs 1-4 as a whole, compared to a dynamic range that can only be secured to a certain extent. In addition, low noise characteristics and high linearity can be secured by making the total value of the control currents IB 1 to IB 4 flowing simultaneously through the four first-stage LNAs 1 to 4 always constant.

The variable current source 2 0 also transfers a part of the control currents I B 1 to I B 4 to the first stage L N A

OFF current I B 1 A indicating that it is not flowing in a part of 1-4

~ Generates I B 4 A and outputs it to the first stage L N A 1 to 4. Specifically, the variable current source 20 generates the first off-current IB 1 A when the first control current IB 1 is not flowing through the first first-stage LNA 1, and the second control current IB When 2 is not passed through the second first-stage LNA 2, a second off-current IB 2 A is generated. Also, when the third control current IB 3 is not flowing to the third first-stage LNA 3, a third off-current IB 3 A is generated, and the fourth control current IB 4 is allowed to flow to the fourth first-stage LNA 4. If not, a fourth off-current IB 4 A is generated.

The next stage L N A 5 corresponds to the next stage amplifier according to the present invention, and is connected to the subsequent stages of the four first stage L N A 1 to 4. Here, 4 first stage L N A

From 1 to 4, control currents IB 1 IB 4 do not flow at the same time. The output lines of the first-stage LNA are connected to form multiple combined output lines L 1 and L 2, and the multiple combined Output lines L 1 and L 2 are connected to multiple input terminals of next-stage LNA 5

Input separately to I N 1 and I N 2

Specifically, the control currents I B 1 and I B 3 do not flow at the same time.

The first combined output line L 1 is formed by connecting the output lines of the first first-stage LNA 1 and the third first-stage LNA 3 together. Also, the second combined output line L 2 is formed by connecting the output lines of the second first stage NA 2 and the fourth first stage LNA 4 where the control currents IB 2 and IB 4 do not flow simultaneously. To do. And the two The combined output lines LI and L 2 are separately input to the multiple input terminals INI and IN 2 of the next-stage LNA 5. The next-stage LNA 5 amplifies the signals input from the two input terminals INI and IN 2, adds the amplified signals, and outputs them. Next, the circuit configuration of the first-stage LNAs 1 to 4 according to this embodiment Will be explained. Since the first-stage LNAs 1 to 4 all have the same circuit configuration, the configuration of the first first-stage LNA 1 will be described below as a representative. FIG. 2 is a circuit diagram showing a configuration example of the first first-stage LNA 1.

In FIG. 2, the p MO S transistor P I and the n MO S transistor N 1 connected to the input terminal I N constitute an inverting amplifier. The inverting amplifiers P 1 and N 1 invert the phase of the signal input from the input terminal I N and amplify it. The amplified signal is output to the next stage via the coupling capacitor C1. The n MOS transistor N 4 connected to the next stage of the coupling capacitor C 1 is a buffer amplifier with a so-called mouth port. The inverting amplifiers P 1 and N 1 and the bass amplifier N 4 constitute the first amplifier 50 of the present invention.

N M connected in parallel with inverting amplifiers P 1 and 1 to input terminal I N

OS 卜 transistors N 2, 3 are force n-amplifiers and correspond to the second amplifier 60 of the present invention. The nMOS transistor N2 that corresponds to the front stage of the force score K connection is a grounded source amplifier, and the nMOS transistor N3 that corresponds to the subsequent stage of the force cord connection is a grounded gate amplifier. This second amplifier

60 amplifies the signal input from the input terminal I N. The n MOS transistors N 5 and N 6 are bias circuits for giving a gate grounding noise to the transistor N 3 which is the latter stage of the power amplifier connection of the second amplifier 60.

, And the output of the first amplifier 50 (the source of the transistor N 4) and the second The output of the amplifier 60 (the drain of the transistor N 3) is connected to the output terminal OU T 1 of the first first-stage LNA 1. For the first amplifier 50, the input signal is amplified in reverse phase by the inverting amplifiers PI and N 1, and the amplified signal is output in the same way (no amplification) to the output terminal OUT 1 by the source follower of the buffer amplifier N 4 . For this reason, the signal output to output terminal OUT 1 is out of phase with the input signal. On the other hand, with respect to the second amplifier 60, the input signal is amplified in reverse phase by the grounded source amplifier N2, and the amplified signal is output to the output terminal OUT1 through the grounded gate amplifier N3 (no amplification). Has been. For this reason, the signal output to output terminal OUT 1 is out of phase with the input signal. In this way, the signal amplified by the first amplifier 50 and the signal amplified by the second amplifier 60 are in phase with each other at the output terminal OUT 1 of the first stage L NA 1, and therefore cancel each other. It will never be done.

In contrast, the noise generated at the source and drain of the inverting amplifiers PI and N 1 is output in phase to the output terminal OU T 1 of the first stage L NA 1 through the coupling capacitor C 1 and the buffer amplifier N 4. (No amplification). On the other hand, the noise that is divided (attenuated) by the resistor R 1 and the signal source resistor (not shown) and output in phase to the input terminal I N is amplified in reverse phase by the common source amplifier N 2. Therefore, the phase of the noise generated at the inverting amplifier PI, N 1 and output to the output terminal OUT 1 through the buffer amplifier N 4 and the noise output to the output terminal OU T 1 through the second amplifier 60 Since the phase is reversed, the noise generated by the inverting amplifiers PI and N 1 can be canceled at the output terminal OUT 1. For this reason, the noise is lower than that of a conventional cascode amplifier in which bipolar transistors are simply cascode-connected.

n MOS transistors N 7 and N 8 are current mirror circuits, and reference current Control current IB 1 is input to the drain of one transistor N7 side.

As the same control current IB 1 flows to the drain on the other transistor N 8 side, the PMOS transistors P 2 to P 5 also constitute a current mirror circuit. n MOS 卜 Transistor N 8 power, control current output

Input I B 1 as the reference current to the drain of one transistor P 5

Make sure that the current proportional to the control current I B 1 flows through the drains of the other transistors P 2 to p 4.

In this way, the combination of the two current circuit circuits N 7 to N 8 and P 2 to P 5 provides the first amplifier 50, the second amplifier 60, and the bias circuit N 5.

, N 6 is supplied with a current proportional to the control current I B 1. That is, the control current IB 1 input from the variable s flow source 20 passes through the two current mirror circuits N 7 N 8 P 2 P 5 and the current proportional to the control current IB 1 is the first Amplifier 50, second amplifier 60 and bias circuit N5

, Supplied to N 6 Ό. As a result, the gain of the first stage L N A 1 becomes the control current I B

It is configured to be controlled by 1.

Inverter I N V 1, I N V 2, p M O S Transistor P 6 and n

The MOS transistors N9 to N10 constitute the switch means of the present invention. This switch means is used to completely turn off the operation of the first amplifier 50 and the second amplifier 60 when the control current IB 1 is not supplied from the variable current source 20.

The two inverters INV 1 and INV 2 are connected in cascade, and the off-current IB 1 A is input to the first-stage inverter INV 1. The output terminal of the inverter INV 1 in the previous stage is connected to the gate of the PMOS transistor P 6. The drain of the PMOS transistor P 6 is connected to the gates of the PMOS transistors P 2 to P 5 constituting the current mirror circuit. Note that the source of the p MOS transistors P2 to P6 is the power supply voltage. Connected to VDD.

On the other hand, the output terminal of the subsequent stage inverter I NV 2 is connected to the gates of the n MOS transistors N 9 and N 10. The drain of the n MO S transistor N 9 is connected to the gate of the transistor N 4 constituting the first amplifier 50, and the drain of the n MO S transistor N 10 is the second. It is connected to the gate of transistor N 3 that composes amplifier 60. The sources of n MOS transistors N 9 and 10 are connected to ground. The input terminal of the inverter I N V 1 in the previous stage is an n MO S transistor! ^ 1 Connected to 1 drain. n The gate of the MOS transistor N l 1 is connected to the input terminals of the current mirror circuits N 7 and N 8 (the input terminal of the control current IB 1), and the source is connected to the ground. Yes.

Here, the operation of the switch means generated as described above will be described. When the control current I B 1 is supplied from the variable current source 2 0, the control current I B 1

When 1 is low level), the off current I B 1 A is supplied from the variable current source 20. Then, the off-current I B 1 A whose phase has been inverted by the preceding inverter I N V 1 is supplied to the gate of the P M Osh transistor P 6. At this time, the output terminal of the inverter I N V 1 at the previous stage becomes a mouth-opener, and p M

OS transistor P6 is turned on.

As a result, the high-level signal output from the K-line of PMOS transistor P6 is the pMOS transistor that forms the current mirror circuit! ^Three

From 2 to P5, it will be supplied to the paddy. Therefore, the p MOS transistors P2 to P5 are the only PMOS transistors P2 to P5

By turning off P5, the first amplifier 50 (inverting amplifiers P1, N1

), The second amplifier 60 and the noise circuit N 5, N 6 can be completely disconnected from the power supply voltage V DD.

On the other hand, the off-state current whose phase was restored by the inverter INV 2 at the rear stage IB 1 A is supplied to the gate of n MOS 卜 transistor N 9, 10, so that the noise level signal output from the inverter INV 2 is

, N O S transistor N 9, 10 will be supplied to the gate

. Therefore, both n M o S 卜 transistors N 9 and N 1 0 are turned on.

. For this reason, both transistors N 3 and N 4 are completely turned off.

As described above, when the control current I B 1 is not supplied from the variable current source 20, the first amplifier 50, the second amplifier 60, and the gravity bias circuit N 5

, 6 are completely disconnected from the supply voltage V D D. Also, the first amplifier 5

The transistor N 4 constituting the zero and the transistor N 3 constituting the second amplifier 60 are all turned off. As a result, the operations of the first amplifier 50 and the second amplifier 60 can be completely turned off.

When the control current I B 1 is supplied from the variable current source 20 to the first stage N A 1, the n M O S 卜 transistor N 1 1 is turned on and the off current I

B 1 A is pulled into ground GND through n MO S h transistor N 1 1.

Next, the circuit configuration of the next stage LNA 5 according to this embodiment will be described. Figure 3

FIG. 6 is a circuit diagram showing a configuration example of the next stage L N A 5. In Figure 3, C 2

1 and C 2 2 are coupling capacitors connected to the two combined output lines L 1 and L 2. A force cord amplifier is connected to each of the two coupling capacitors C 2 1 and C 2 1.

The cascade amplifier connected to the first composite output line L 1 via the coupling capacitor c 2 1 has two n MOs connected in cascade.

S transistors are composed of N 2 1 and N 2 3. The cascode amplifier connected to the second composite output line L 2 via the force-splitting capacitor C 2 2 is composed of two n-type MOS transistors N connected in a force cord. Composed of 2 2 and N 2 3

The n MOS transistor N 2 3 is supplied from the second-stage amplifier of the cascode amplifier that amplifies the signal supplied from the first combined output line L 1 and from the second combined output line L 2 It also serves as the second stage amplifier of the cascode amplifier that amplifies the signal. A load resistor R L is connected to the drain side of the n MOS transistor N 2 3, that is, to the output stage of the cascade amplifier (the output terminal O U T side of the next stage L N A 5).

That is, the next-stage LNA 5 receives a signal supplied from the first combined output line L 1 through one input terminal IN 1 and the second combined output line 2 through the other input terminal IN 2. The signals supplied are amplified by two cascade amplifiers, and the amplified signals are added and output from the output terminal OUT.

n MOS transistors N 2 4 and N 2 5 are transistors for providing a gate grounding noise to the n MOS transistor N 2 3, which is the latter stage of the cascode connection fee. It is. n MO S transistor N 2 6 is one of the transistors that make up a current mirror circuit, and it forms a current error circuit with n MO S transistors N 2 1 and N 2 2, which is the preceding stage of the Casco connection.

That is, the control current IB 5 is input as a quasi-current to the drain of the n MOS transistor N 2 6, and the n MOS transistors N 2 1 and N 2 2 corresponding to the front stage side of the power cord amplifier are input. Ensure that a current proportional to the control current IB 5 flows through the drain. In other words, the current proportional to the control current I B 5 input to the n M o S transistor N 26 from the variable current source 20 is the n M O

S transistor N 2 6 is supplied to two cascaded amplifiers connected in a current mirror. As a result, the gain of the next-stage LNA 5 is controlled by the control current IB 5. As described above in detail, in the present embodiment, the first-stage LNA 1 to 4 and the next-stage LNA 5 have a two-stage configuration, and the control currents IB 1 to IB 4 do not flow simultaneously. ~ 4, that is, connect the output lines of the first stage LNA 1 ~ 4 that cannot operate at the same time, and input the combined output lines LI and L2 to the next stage LNA 5 respectively. Yes. The next stage amplifier 5 adds the output signals of the first stage LNA 1 to 4 operating simultaneously.

As a result, even in the variable gain amplifier of the CMOS process in which the output stage is a source follower, the output signals of the first stage amplifiers 1 to 4 operating simultaneously can be added in the next stage amplifier 5. Therefore, a wide dynamic range can be secured. In addition, since the total value of the control currents IB 1 to IB 4 flowing through the multiple first-stage LNAs 1 to 4 is controlled to be always constant, low noise characteristics and the relationship between control voltage and gain High linearity can be secured.

Further, according to the present embodiment, the noise generated in the inverting amplifiers PI, 1 of the first-stage LNAs 1 to 4 is transmitted from the second amplifier 6 0 connected in parallel to the inverting amplifiers P 1 and N 1. It is canceled out by adding in the opposite phase to the output noise. As a result, noise figure deterioration can be suppressed in the first stage LNA 1 to 4 of the CMO S process.

Furthermore, according to the present embodiment, the operation of the first amplifier 50 and the second amplifier 60 of the first stage LNA 1 to 4 where the control currents IB 1 to IB 4 are not supplied is completely performed by the switch means. Can be off. As a result, it is possible to prevent noise from the transistors in the first stage LNA 1 to 4 that are not involved in the amplification operation, so that deterioration of the noise figure is suppressed in the first stage LNA 1 to 4 of the CMOS process. You can.

In general, the overall noise figure NF when amplifiers are cascaded is It is given by the formula.

NF = NF 1 + (NF 2-1) / G 1 + (NF 3-1) / G 1 * G 2 + where NF 1 is the noise figure of the first stage amplifier and NF 2 is the second stage NF 3 is the noise figure of the third stage amplifier. G 1 is

The gain of the first stage amplifier, G 2 is the gain of the second stage amplifier.

As can be seen from the above equation, to reduce the noise figure N F of the entire amplifier,

(1) Reduce the noise figure N F 1 of the first stage amplifier

(2) Increase the gain G1 of the first stage amplifier

This is necessary. In this embodiment, it is particularly required to reduce the noise figure of the first stage amplifiers 1 to 4. In contrast, in the present embodiment, the noise figure of the first stage amplifiers 1 to 4 can be reduced as described above.

As a result, the noise figure of the entire variable gain amplifier can be reduced, and good mouth sensitivity can be obtained.

In the above embodiment, the number of first-stage LNAs 1 to 4 is four, but this is merely an example. In the above embodiment, the outputs of the two first-stage L N A are connected to form a composite output line, but this is also merely an example. That is, as long as the first stage L NAs that simultaneously flow control currents, the output of three or more first stage L NAs may be connected to form a composite output line.

Further, in the above-described embodiment, the description has been given of the example in which two control currents are simultaneously supplied, and many of the four control currents I B 1 to I B 4 <, but the present invention is not limited to this. For example, if the number of first stage L N A is more than four, there may be a case where three or more control currents flow simultaneously.

The variable gain amplifier of the above embodiment is, for example, a radio tuner R Although it is suitable for use in the F-AGC circuit, it can be applied to other than the RF-AGC circuit. RF—When applied to other than AGC circuits, an amplifier can be connected instead of connecting the attenuators 11 to 13 to the input stages of the 2nd to 4th first stage LNA 2 to 4. In other words, in the above embodiment, the input signal is attenuated by 20 [dB] by one step, and an example in which a dynamic range of 80 [dB] is ensured by one-to-one is described. Input signal 2

By amplifying each 0 [dB], a total dynamic range of 80 [dB] may be secured. In this case, Attenuator 1

The amplifier used instead of 1 to 13 constitutes the Revenore regulator of the present invention. In the above embodiment, the inverters I N V 1 and I N V 2 shown in FIG.

In the above description, the switch means is composed of the p MO S transistor P 6 and the n M Os transistors N 9 to N 10, but this is only an example. For example, the switch means may be constituted by the inverters I N V 1, I N V 2 and the p MOS transistor P 6. In this case, at least when the control currents IB 1 to IB 4 are not supplied from the variable current source 20, the first amplifier 50, the second amplifier 60, and the bias circuit N 5, N 6 Can be completely disconnected from the power supply voltage VDD. Since the control currents I B 1 to I B 4 are not supplied, the amplification operation is not performed. In that case, the noise figure can be prevented from deteriorating by completely disconnecting the transistor from the power supply voltage V DD.

Alternatively, the switch means may be constituted by n MOS transistors N 9 to N 10. In this case, at least, the transistor N 4 constituting the first amplifier 50 and the transistor constituting the second amplifier 60 are both at the low level and completely turned off. . As a result, control currents IB 1 to IB 4 are not supplied from variable current source 20 Sometimes, by turning off the operations of the first amplifier 50 and the second amplifier 60 completely, it is possible to suppress the deterioration of the noise figure.

In the above embodiment, an example has been described in which signals are added at the output stage of the upstream transistor in the cascade connection in the two cascode amplifiers constituting the next-stage LNA 5, but the present invention is not limited to this. Not. For example, the signals may be added at the output stage of the rear stage transistor in the cascode connection.

In addition, each of the above-described embodiments is merely an example of the embodiment for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereby. is there. That is, the present invention can be implemented in various forms without departing from the spirit or the main features thereof. Industrial applicability

The present invention is useful for a gain variable amplifier in which a plurality of amplifiers are connected to increase the gain variable range. For example, the variable gain amplifier of the present invention is suitable for use in a radio tuner mounted on a mobile body such as an in-vehicle device or a mobile phone.

Claims

The scope of the claims

1. a plurality of first stage amplifiers connected in parallel to one input and performing an amplification operation by a control current flowing through each of them;

Level adjustment that is connected to the input side of the first-stage amplifier for at least some of the plurality of first-stage amplifiers, and adjusts so that the levels of signals input to the plurality of first-stage amplifiers are different. And

'A next-stage amplifier connected to the subsequent stage of the plurality of first-stage amplifiers;

A variable current source that controls the control current flowing through the plurality of first-stage amplifiers so that the total value of the control current flowing simultaneously is constant, and the control currents of the plurality of first-stage amplifiers are simultaneously The output lines of the first stage amplifier that does not flow are connected to form a plurality of combined output lines, and the plurality of combined output lines are separately input to the plurality of input terminals of the next stage amplifier. And

The next-stage amplifier amplifies signals input from the plurality of input terminals, adds the amplified signals, and outputs the amplified signals.

2. Each of the above first-stage amplification koto is

A first amplifier for inverting and amplifying the phase of the input signal;

A second amplifier for amplifying the input signal,

2. The gain variable amplifier according to claim 1, wherein the output signal of the first amplifier and the output signal of the second amplifier are added and output.

3. Each of the multiple first stage amplifiers is

Switch means for turning off the operation of the first amplifier and the second amplifier when the control current is not supplied from the variable current source The variable gain amplifier according to claim 2, further comprising: