JP2011151771A - Electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress deterioration of a noise factor in an amplification circuit. <P>SOLUTION: The electronic circuit includes a transmission switch SW1 for sending a transmission signal received from a transmission terminal Tx to a common terminal ANT, an amplification circuit 90 for amplifying the signal received from the common terminal and outputting it to a reception terminal Rx, a first reception switch SW2 for sending the signal received from the common terminal to the amplification circuit not via the other switches, and a second reception switch SW3 connected in parallel to the first reception switch between the common terminal and the reception terminal to send the reception signal received from the common terminal to the reception terminal via another route different from the amplification circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electronic circuit, and more particularly to an electronic circuit having a switch.

  As described in Patent Document 1, an electronic circuit in which a reception switch is connected between a common terminal connected to an antenna and a reception terminal and a transmission switch is connected between the common terminal and the transmission terminal is known. It has been. The transmission switch connects the transmission signal input from the transmission terminal to the common terminal. The reception switch connects the reception signal input from the common terminal to the reception terminal. When transmitting a transmission signal from the antenna, the transmission switch is turned on and the reception switch is turned off. On the other hand, when receiving a reception signal from the antenna, the reception switch is turned on and the transmission switch is turned off. Thereby, interference with a received signal and a transmitted signal can be suppressed. These switches are composed of, for example, FET (Field Effect Transistor).

JP 2007-28178 A

  However, when an amplifier circuit and a path that bypasses the amplifier circuit are integrated between the transmission switch and the transmission terminal, the noise figure (NF) of the reception amplifier circuit deteriorates. An object of the present invention is to suppress degradation of a noise figure of an amplifier circuit.

  The present invention relates to a transmission switch for connecting a transmission signal input from a transmission terminal to the common terminal, an amplification circuit for amplifying a reception signal input from the common terminal and outputting the signal to the reception terminal, and other devices from the common terminal. A first receiving switch for connecting the received signal inputted without passing through the switch to the amplifier circuit, and the first receiving switch connected in parallel between the common terminal and the receiving terminal, and the common terminal And a second reception switch for connecting the reception signal input from the reception circuit to the reception terminal through a path different from that of the amplification circuit. According to the present invention, it is possible to suppress the degradation of the noise figure of the amplifier circuit.

  In the above configuration, a control circuit may be provided that turns on one of the transmission switch, the first reception switch, and the second reception switch and turns off the other.

  In the above configuration, an amplifier circuit output side switch for connecting the amplifier circuit and a node between the second reception switch and the reception terminal may be provided.

  In the above configuration, the amplifier circuit output side switch may be configured to be non-conductive when the second reception switch is conductive.

  In the above configuration, the first reception switch and the second reception switch are configured by FETs, and the gate width of the FET configuring the second reception switch is smaller than the gate width of the FET configuring the first reception switch. be able to.

  In the above configuration, the transmission switch may be configured by an FET, and the gate width of the FET configuring the first reception switch may be smaller than the gate width of the FET configuring the transmission switch.

  In the above configuration, the number of stages of the amplifier circuit output side switch may be smaller than the number of stages of the transmission switch, the first reception switch, and the second reception switch.

  In the above configuration, a series switch connected in series to the path between the second reception switch and the reception terminal, and a node between the second reception switch and the series switch and a ground. And a shunt switch.

  In the above configuration, a series switch connected in series to the path between the second reception switch and the reception terminal, and a node between the second reception switch and the series switch and a ground. A shunt switch, and the control circuit turns off the series switch and turns on the shunt switch when the first reception switch is turned on, and turns on the series switch when the second reception switch is turned on. The shunt switch can be turned on and turned off.

  According to the present invention, it is possible to suppress the deterioration of the noise figure of the receiving amplifier circuit.

FIG. 1 is a circuit diagram of an electronic circuit according to a comparative example. FIG. 2 is a circuit diagram of the electronic circuit according to the first embodiment. FIG. 3 is a diagram illustrating a result of measuring the NF with respect to the frequency of the electronic circuit according to the comparative example and the first embodiment. FIG. 4 is a circuit diagram of an electronic circuit according to the second embodiment. FIGS. 5A to 5C are diagrams showing simulation results of the LNA gain with respect to the frequency, the isolation S12 of the amplifier circuit, and the stability coefficient K. FIG.

  First, a comparative example will be described. In the comparative example, an amplifier circuit and a bypass path are provided in parallel between the reception switch and the reception terminal. When the received signal is a small signal, the amplifier circuit amplifies the received signal, and the amplified received signal is output to the receiving terminal. On the other hand, when the received signal is a relatively large signal, the received signal bypasses the amplifier circuit, and the unamplified received signal is output to the receiving terminal.

  FIG. 1 is a circuit diagram of an electronic circuit according to a comparative example. Referring to FIG. 1, the electronic circuit 102 mainly includes a transmission switch SW1 and a reception switch SW2, a bypass switch SW5, an amplifier circuit 90, and switches SW4 and SW6. The transmission switch SW1 connects the transmission signal input from the transmission terminal Tx to the common terminal ANT. The reception switch SW2 connects the reception signal input from the common terminal ANT to the reception terminal Rx. An amplifier circuit 90 is connected between the reception switch SW2 and the reception terminal. The amplifier circuit 90 amplifies the reception signal input from the common terminal ANT and outputs the amplified signal to the reception terminal Rx. The bypass switch SW5 is provided to bypass the amplifier circuit 90 between the node N2 between the reception switch SW2 and the amplifier circuit 90 and the node N1 between the reception terminal Rx and the amplifier circuit 90. The switch SW4 is connected between the node N1 and the amplifier circuit 90, and the switch SW6 is connected between the node N2 and the amplifier circuit 90.

  The transmission switch SW1 is composed of, for example, a two-stage FET 10, the reception switch SW2 is composed of a two-stage FET 20, the bypass switch SW5 is composed of a single-stage FET 50, the switch SW4 is composed of a single-stage FET 40, and the switch SW6 is composed of a single-stage FET 60. A signal V1 is applied to the gate of the FET 10 constituting the transmission switch SW1 via the resistor R1. A signal V2 is applied to the gate of the FET 20 constituting the first reception switch SW2 via the resistor R2. A signal V5 is applied to the gate of the FET 50 constituting the bypass switch SW5 via the resistor R5. Signal V4 is applied to the gates of switches SW4 and SW6 via resistors R4 and R6, respectively.

  The amplifier circuit 90 is a low noise amplifier (LNA), and includes an input matching circuit 80, FETs 84 and 86, and an output matching circuit 82. The input matching circuit 80 is a circuit that matches the input impedance of the amplifier circuit 90. The output matching circuit 82 is a circuit that matches the output impedance of the amplifier circuit 90. A reception signal whose impedance is matched by an input matching circuit is input to the gate of the FET 84. Further, the gate bias Vg1 is applied to the gate of the FET 84 via the resistor Rg1. The source of the FET 84 is grounded. The drain of the FET 84 is connected to the source of the FET 86. The gate of the FET 86 is grounded via the capacitor C2, and a gate bias Vg2 is applied via the resistor Rg2. The drain of the FET 86 is connected to the output matching circuit 82. The power source voltage Vdd is applied to the drain of the FET 86 through the choke coil L1. A DC cut capacitor C1 is connected between the amplifier circuit 90 and the switch SW6. A DC cut capacitor C3 is connected between the amplifier circuit 90 and the switch SW4.

  The signal at the terminal T01 is applied to the transmission switch SW1 as the signal V1. The signal at the terminal T02 is applied to the reception switch SW2 as the signal V2. The signal at the terminal T03 is applied as a signal V4 to the switches SW4 and SW6. The signal at the terminal T03 is inverted through the inverting circuit 88 and applied to the bypass switch SW5 as the signal V5. Each switch is turned on when the signal is at a high level and turned off when the signal is at a low level.

Table 1 is a table showing the state of each terminal during each operation of the electronic circuit 102.

  As shown in Table 1, when transmitting a transmission signal from the antenna, the terminal T01 is set to the high level, and the terminals T02 and T03 are set to the low level. As a result, the transmission signal passes from the transmission terminal Tx to the common terminal ANT. Since the terminals T02 and T03 are at a low level, the reception switch SW is turned off. Thereby, it can suppress that a transmission signal reaches the receiving terminal Rx side. Furthermore, since the switches SW4 and SW6 are off, it is possible to suppress the leakage signal from the reception switch SW2 and the signal from the reception terminal Rx from reaching the amplifier circuit 90.

  When the reception signal is received from the antenna and the reception signal is a small signal (in the case of reception (LNA)), the terminal T01 is at a low level and the terminals T02 and T03 are at a high level. Since the transmission switch SW1 is turned off, the reception signal can be prevented from reaching the transmission terminal Tx. Reception switch SW2, switches SW4 and SW6 are turned on, and bypass switch SW5 is turned off. As a result, the received signal is amplified by the amplifier circuit 90 and output from the receiving terminal Rx.

  When the received signal is received from the antenna and the received signal is a relatively large signal (in the case of reception (bypass)), the terminals T01 and T03 are at a low level and the terminal T02 is at a high level. Since the transmission switch SW1 is turned off, the reception signal can be prevented from reaching the transmission terminal Tx. The reception switch SW2 and the bypass switch SW5 are turned on, and the switches SW4 and SW6 are turned off. As a result, the reception signal bypasses the amplifier circuit 90 and is output from the reception terminal Rx. Since the switches SW4 and SW6 are off, the reception signal can be prevented from leaking to the amplifier circuit 90.

  In the comparative example, there is a problem that the noise figure (NF: Noise Figure) of the amplifier circuit 90 is bad. As shown in FIG. 1, a reception switch SW2 and a switch SW6 are connected in series between the amplifier circuit 90 and the common terminal ANT. Therefore, when the reception switch SW2 and the switch SW6 are turned on, the on-resistance of the reception switch SW2 and the on-resistance of the switch SW6 are connected in series between the amplifier circuit 90 and the common terminal ANT. The received signal component is attenuated by these resistance components, and the relative ratio with noise components such as thermal noise is deteriorated. This degrades the noise figure.

  Hereinafter, examples for solving the above-described problems will be described.

  FIG. 2 is a circuit diagram of the electronic circuit according to the first embodiment. As shown in FIG. 2, in the electronic circuit 100, the first reception switch SW2 and the second reception switch SW3 are connected in parallel between the common terminal ANT and the reception terminal Rx. The first reception switch SW2 connects the reception signal input from the common terminal ANT without passing through another switch to the amplifier circuit 90. The second reception switch SW3 bypasses the reception signal input from the common terminal ANT through a path different from that of the amplifier circuit 90 and connects the reception signal to the reception terminal Rx. The first reception switch SW2 and the second reception switch SW3 are composed of FETs 20 and 30, respectively. In the first reception switch SW2, the sources and drains of the plurality of FETs 20 are connected in series, a signal is input to the source of the first stage FET, and a signal is output from the drain of the final stage FET. A signal V2 is applied to the gate of the FET 20 via the resistor R2. The FET 10 and the FET 30 of the transmission switch SW1 and the second reception switch SW3 are similarly connected. A signal V3 is applied to the gate of the FET 30 via the resistor R3.

  The electronic circuit 100 according to the first embodiment is not provided with the bypass switch SW5 and the switch SW6. The electronic circuit 100 includes a decoder 70 and bias circuits 72 and 74. Other configurations are the same as those of the comparative example shown in FIG.

  The decoder 70 receives digital signals from terminals T1 and T2, and outputs signals V1 to V4 to switches SW1 to SW4, respectively. Terminal T 1 is also connected to bias circuits 72 and 74. The bias circuits 72 and 74 apply gate biases Vg1 and Vg2 to the gates of the FETs 84 and 86, respectively, according to the state of the terminal T1.

Table 2 shows the inputs and outputs of the decoder 70 during each operation.

  As shown in Table 2, the signal at the terminal T1 indicates whether a path for amplifying the received signal by the amplifier circuit 90 is selected or another path (transmission or reception (bypass) path) is selected. When the terminal T1 is at a high level, the decoder sets the signals V2 and V4 to a high level according to the logic, and the logic at the terminal T1 is also input to the bias circuits 72 and 74. The bias circuits 72 and 74 are activated by receiving a high level input from the terminal T1, and output gate biases Vg1 and Vg2. As a result of the above operation, the amplifier circuit 90 becomes conductive, and the reception signal passing through the first reception switch SW2 is amplified by the amplifier circuit 90 and output from the reception terminal Rx. When the terminal T1 is at a low level, the bias circuits 72 and 74 are inactive. As described above, since the bias circuits 72 and 74 are activated only when a path through the amplifier circuit 90 is selected, the power consumption of the amplifier circuit 90 can be reduced. Further, the logic of the terminal T1 is changed to a logic indicating whether to select a path for amplifying the received signal by the amplifier circuit 90 or to select another path (transmission or reception (bypass) path). The circuits 72 and 74 have an effect that the activation control can be performed only by the logic of the terminal T1, without requiring the logic of the terminal T2.

  The signal at the terminal T2 indicates whether the transmission signal is transmitted or the signal is received via reception (bypass). When the signal at the terminal T2 is at a high level, a transmission signal is transmitted. When the signal at the terminal T2 is low level, the signal is received via reception (bypass).

  When transmitting a transmission signal from the antenna, the terminal T1 is at a low level and the terminal T2 is at a high level. As for the output of the decoder 70, the signal V1 is at a high level and the signals V2 to V4 are at a low level. As a result, the transmission switch SW1 is turned on, and the first reception switch SW2, the second reception switch SW3, and the amplifier circuit output side switch SW4 are turned off. Therefore, the transmission signal is suppressed from reaching the reception terminal Rx side.

  When the reception signal is received from the antenna and the reception signal is a small signal (in the case of reception (LNA)), the terminal T1 is at a high level and the terminal T2 is at a low level. As for the output of the decoder 70, the signals V2 and V4 are at a high level, and the signals V1 and V3 are at a low level. As a result, the transmission switch SW1 and the second transmission switch SW3 are turned off, and the first reception switch SW2 and the switch SW4 are turned on. Therefore, the reception signal passes through the first reception switch SW2, is amplified by the amplifier circuit 90, passes through the switch SW4, and is output from the reception terminal Rx.

  When the reception signal is received from the antenna and the reception signal is a large signal (in the case of reception (bypass)), the terminal T1 is at a low level and the terminal T2 is at a low level. As for the output of the decoder 70, the signal V3 is at a high level, and the signals V1, V2, and V4 are at a low level. As a result, the transmission switch SW1, the first reception switch SW2, and the switch SW4 are turned off, and the second reception switch SW3 is turned on. Therefore, the received signal passes through the second receiving switch SW3 and is directly output from the receiving terminal Rx without passing through the amplifier circuit 90. In this way, the decoder 70 (control circuit) turns on one of the transmission switch SW1, the first reception switch SW2, and the second reception switch SW3, and turns off the others.

  As described above, according to the first embodiment, as in the comparative example, when the received signal is a small signal, the amplifier circuit 90 amplifies the received signal and outputs the amplified received signal to the receiving terminal Rx. Can do. On the other hand, when the received signal is a relatively large signal, the amplifying circuit 90 can be bypassed, and a received signal that is not amplified can be output to the receiving terminal Rx.

  Further, the first reception switch SW2 and the second reception switch SW3 are connected in parallel between the common terminal ANT and the reception terminal Rx. Thereby, the switch connected between the amplifier circuit 90 and the common terminal ANT is the first reception switch SW2. Therefore, the resistance between the amplifier circuit 90 and the common terminal ANT can be reduced by the ON resistance of the switch SW6 as compared with the comparative example. Therefore, the noise figure can be improved. FIG. 3 is a diagram illustrating a result of measuring the NF with respect to the frequency of the electronic circuit according to the comparative example and the first embodiment. As shown in FIG. 3, in Example 1, NF is improved over the comparative example.

  Further, the switch SW4 connects between the amplifier circuit 90 and the node N1 between the second reception switch SW3 and the reception terminal Rx. By turning off the switch SW4 when the second reception switch SW3 is turned on, it is possible to prevent the reception signal from flowing back to the amplifier circuit 90.

  In the first embodiment, the gate widths of the FETs constituting the switches SW1 to SW3 may be the same. However, it is preferable that the gate widths of the FETs constituting the switches SW1 to SW3 have the following relationship. Here, the gate width of the FET is the sum of the gate widths of the unit FETs, that is, the gate when one FET is configured by a parallel structure of a plurality of unit FETs (for example, a parallel structure of a source, a gate and a drain) Indicates the total width extension.

  Even if the FET is turned off, there is a slight leakage current. Therefore, when the gate width is reduced, the isolation characteristic of the switch can be improved. However, if the gate width is small, the on-resistance increases and insertion loss increases.

  The received signal when the first receiving switch SW2 is turned on is a small signal using the amplifier circuit 90. Therefore, it is preferable to reduce the ON resistance of the first reception switch SW2 in order to reduce the insertion loss. On the other hand, the received signal when the second receiving switch SW3 is turned on is a relatively large signal. Therefore, the on-resistance of the second reception switch SW3 may be larger than that of the first reception switch SW2. Therefore, the gate width Wg2 of the first reception switch SW2 is preferably large in order to reduce the on-resistance, and the gate width Wg3 of the second reception switch SW3 is preferably small in order to improve the isolation characteristics. Thus, the gate width Wg3 of the FET constituting the second reception switch SW3 is preferably smaller than the gate width Wg2 of the FET constituting the first reception switch SW2. In Example 1, the gate width Wg2 is 1 mm, and the gate width Wg3 is 0.5 mm.

  The transmission switch SW1 handles a very large signal compared to the reception signal. Therefore, in order to reduce the insertion loss, it is preferable that the gate width Wg1 of the transmission switch SW1 is large. That is, the gate width Wg2 of the FET constituting the first reception switch SW2 is preferably smaller than the gate width Wg1 of the FET constituting the transmission switch SW1. In Example 1, the gate width Wg1 is 1.2 mm.

  Further, since the transmission switch SW1, the first reception switch SW2, and the second reception switch SW3 are directly connected to the common terminal ANT, it is preferable that the isolation is large. Therefore, a multi-stage configuration is preferable (a two-stage configuration is used in FIG. 2 of Embodiment 1). On the other hand, the switch SW4 may have an isolation characteristic that suppresses the reception signal from the second reception switch SW3 from entering the amplifier circuit 90. Therefore, the number of stages of the switch SW4 is preferably smaller than the number of stages of the transmission switch SW1, the first reception switch SW2, and the second reception switch SW3. Note that in the case where the switch has a multi-stage configuration, if the gate width is different in each stage, the voltage is concentrated in a stage having a small gate width, so that the exceptional gate width is preferably the same. Originally, when considering isolation, a configuration as in the comparative example (transmission switch, reception switch SW2) is preferable. In the electronic circuit of the first embodiment, as described above, the gate width of each of the transmission switch SW1, the first reception switch SW2, and the second reception switch SW3 is set to a desired size (Wg1> Wg2> Wg3). Isolation equivalent to that of the comparative example can be obtained, and deterioration of the noise figure of the receiving amplifier circuit can be suppressed.

  Example 2 is an example having a series switch and a shunt switch. FIG. 4 is a circuit diagram of an electronic circuit according to the second embodiment. As shown in FIG. 4, the switch SW7 (series switch) is connected in series to the path between the second reception switch SW3 and the reception terminal Rx. The switch SW7 is composed of an FET 62. A signal V3 is applied to the gate of the FET 62 via the resistor R7. A switch SW8 (shunt switch) is connected between the node N3 between the second reception switch SW3 and the series switch SW7 and the ground. The switch SW8 is composed of an FET 64. A signal V2 is applied to the gate of the FET 64 via the resistor R8. Other configurations are the same as those of the first embodiment shown in FIG.

  The signal V3 applied to the switch SW7 is common to the second reception switch SW3, and the signal V2 applied to the switch SW8 is common to the first reception switch SW2. Therefore, as shown in Table 2, when the first reception switch SW2 is turned on, the decoder 70 turns off the switch SW7 and turns on the switch SW8. When the second reception switch SW3 is turned on, the switch SW7 is turned on and the switch SW8 is turned off.

  FIGS. 5A to 5C are diagrams showing simulation results of the LNA gain with respect to the frequency, the isolation S12 of the amplifier circuit 90, and the stability coefficient K. FIG. This is a simulation when the first reception switch SW2 is on and the second reception switch SW1 is off. The simulated parameters are as follows. In the transmission switch SW1, two FETs 10 having a gate width Wg1 of 1 mm are connected in series. The first reception switch SW2 includes two FETs 20 having a gate width Wg2 of 1 mm connected in series. The second reception switch SW3 has two FETs 30 with a gate width Wg3 of 0.5 mm connected in series. The switch SW4 includes one FET 40 having a gate width Wg4 of 0.5 mm. The switch SW7 includes one FET 62 having a gate width Wg7 of 0.5 mm. The switch SW8 includes one FET 64 having a gate width Wg8 of 0.2 mm. Each FET is a HEMT (High Electron Mobility Transistor) having AlGaAs as an electron supply layer and InGaAs as an electron transit layer, and has a gate length of 0.5 μm. In the first embodiment, as shown in FIG. 2, the switch SW7 and the switch SW8 are not provided.

  As shown in FIG. 5A, the gain of the LNA is almost the same between the first embodiment and the second embodiment. As illustrated in FIG. 5B, the second embodiment has a smaller S12 indicating feedback from the node N1 to the first reception switch SW1 than the first embodiment. As shown in FIG. 5C, the stability k of the second embodiment is smaller than that of the first embodiment.

  In the first embodiment, for example, when the frequency is increased, the isolation is deteriorated due to the off-capacitance even if the second reception switch SW3 is turned off. For this reason, as shown in FIG. 5B, when the first reception switch SW2 is on and the second reception switch SW1 is off, the node N1 passes the second reception switch SW3 to the input side of the first reception switch SW2. The signal is fed back. Therefore, as shown in FIG. 5C, in Example 1, the stability coefficient k is deteriorated.

  According to the second embodiment, by providing the switch SW7 and the switch SW8, when the first reception switch SW2 is on as shown in FIG. 5B, the input of the first reception switch SW2 from the node N1. The feedback signal to the side can be suppressed. As a result, the stability coefficient k can be improved as shown in FIG. On the other hand, when the second reception switch SW3 is on, the output of the second reception switch SW3 can be output to the node N1 by turning on the series switch SW7 and turning off the shunt switch SW8.

  In the first and second embodiments, the circuit using the FETs 84 and 86 is described as an example of the amplifier circuit 90. However, the amplifier circuit may be a circuit having another configuration. Although a description has been given of a switch configured by an FET as an example, a configuration using another transistor or the like may be used.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

SW1 transmission switch SW2 first reception switch SW3 second reception switch SW4 amplifier circuit output side switch SW7 series switch SW8 shunt switch 90 amplifier circuit

Claims (9)

A transmission switch for connecting a transmission signal input from a transmission terminal to the common terminal;
An amplification circuit that amplifies the reception signal input from the common terminal and outputs the amplified signal to the reception terminal;
A first receiving switch for connecting the received signal input from the common terminal without passing through another switch to the amplifier circuit;
The first reception switch is connected in parallel between the common terminal and the reception terminal, and the reception signal input from the common terminal is connected to the reception terminal through a path different from the amplification circuit. 2 receiving switches,
An electronic circuit comprising:   The electronic circuit according to claim 1, further comprising a control circuit that turns on one of the transmission switch, the first reception switch, and the second reception switch and turns off the other.   The electronic circuit according to claim 1, further comprising: an amplifier circuit output side switch that connects the amplifier circuit and a node between the second reception switch and the reception terminal.   4. The electronic circuit according to claim 3, wherein the amplifier circuit output side switch is turned off when the second receiving switch is turned on.   The first reception switch and the second reception switch are configured by FETs, and a gate width of the FETs configuring the second reception switch is smaller than a gate width of the FETs configuring the first reception switch. The electronic circuit according to any one of 1 to 4.   6. The electronic circuit according to claim 5, wherein the transmission switch is constituted by an FET, and a gate width of the FET constituting the first reception switch is smaller than a gate width of the FET constituting the transmission switch.   The electronic circuit according to any one of claims 1 to 6, wherein the number of stages of the amplifier circuit output side switch is smaller than the number of stages of the transmission switch, the first reception switch, and the second reception switch. A series switch connected in series to the path between the second receiving switch and the receiving terminal;
A shunt switch connected between a node between the second receiving switch and the series switch and the ground;
The electronic circuit according to claim 1, further comprising: A series switch connected in series to the path between the second receiving switch and the receiving terminal;
A shunt switch connected between a node between the second receiving switch and the series switch and the ground;
Comprising
The control circuit turns off the series switch and turns on the shunt switch when the first reception switch is turned on, and turns on the series switch and turns off the shunt switch when the second reception switch is turned on. The electronic circuit according to claim 2.

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