JP2008532132A5 - - Google Patents

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Publication number
JP2008532132A5
JP2008532132A5 JP2007556650A JP2007556650A JP2008532132A5 JP 2008532132 A5 JP2008532132 A5 JP 2008532132A5 JP 2007556650 A JP2007556650 A JP 2007556650A JP 2007556650 A JP2007556650 A JP 2007556650A JP 2008532132 A5 JP2008532132 A5 JP 2008532132A5
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JP
Japan
Prior art keywords
pitch
resized
transistor
routing
initial
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JP2007556650A
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English (en)
Japanese (ja)
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JP2008532132A (ja
JP4773466B2 (ja
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Priority claimed from US11/066,041 external-priority patent/US7287237B2/en
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Publication of JP2008532132A publication Critical patent/JP2008532132A/ja
Publication of JP2008532132A5 publication Critical patent/JP2008532132A5/ja
Application granted granted Critical
Publication of JP4773466B2 publication Critical patent/JP4773466B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007556650A 2005-02-24 2006-02-17 配列された論理セル格子及び相互接続ルーティング構造 Expired - Fee Related JP4773466B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/066,041 2005-02-24
US11/066,041 US7287237B2 (en) 2005-02-24 2005-02-24 Aligned logic cell grid and interconnect routing architecture
PCT/GB2006/000573 WO2006090126A2 (en) 2005-02-24 2006-02-17 Aligned logic cell grid and interconnect routing architecture

Publications (3)

Publication Number Publication Date
JP2008532132A JP2008532132A (ja) 2008-08-14
JP2008532132A5 true JP2008532132A5 (https=) 2010-06-17
JP4773466B2 JP4773466B2 (ja) 2011-09-14

Family

ID=36927791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007556650A Expired - Fee Related JP4773466B2 (ja) 2005-02-24 2006-02-17 配列された論理セル格子及び相互接続ルーティング構造

Country Status (5)

Country Link
US (1) US7287237B2 (https=)
EP (1) EP1861801A2 (https=)
JP (1) JP4773466B2 (https=)
TW (1) TWI413213B (https=)
WO (1) WO2006090126A2 (https=)

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US20060281221A1 (en) * 2005-06-09 2006-12-14 Sharad Mehrotra Enhanced routing grid system and method
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7917879B2 (en) 2007-08-02 2011-03-29 Tela Innovations, Inc. Semiconductor device with dynamic array section
US8448102B2 (en) * 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US7401310B1 (en) * 2006-04-04 2008-07-15 Advanced Micro Devices, Inc. Integrated circuit design with cell-based macros
US7735041B2 (en) * 2006-08-03 2010-06-08 Chipx, Inc. Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101903975B1 (ko) 2008-07-16 2018-10-04 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8607180B2 (en) * 2012-05-09 2013-12-10 Lsi Corporation Multi-pass routing to reduce crosstalk
US10541243B2 (en) 2015-11-19 2020-01-21 Samsung Electronics Co., Ltd. Semiconductor device including a gate electrode and a conductive structure
KR102661932B1 (ko) * 2016-12-16 2024-04-29 삼성전자주식회사 멀티플 패터닝 리소그래피를 위한 집적 회로, 집적 회로의 설계를 위한 컴퓨팅 시스템 및 컴퓨터 구현 방법
US10916498B2 (en) 2018-03-28 2021-02-09 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect structure for logic circuit
KR102373540B1 (ko) 2018-04-19 2022-03-11 삼성전자주식회사 표준 셀들을 포함하는 집적 회로, 이를 제조하기 위한 방법 및 컴퓨팅 시스템
US10796061B1 (en) * 2019-08-29 2020-10-06 Advanced Micro Devices, Inc. Standard cell and power grid architectures with EUV lithography
US11755808B2 (en) * 2020-07-10 2023-09-12 Taiwan Semiconductor Manufacturing Company Limited Mixed poly pitch design solution for power trim

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US5341310A (en) * 1991-12-17 1994-08-23 International Business Machines Corporation Wiring layout design method and system for integrated circuits
US5754826A (en) 1995-08-04 1998-05-19 Synopsys, Inc. CAD and simulation system for targeting IC designs to multiple fabrication processes
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US6629308B1 (en) * 2000-07-13 2003-09-30 Xilinx, Inc. Method for managing database models for reduced programmable logic device components
TW451457B (en) * 2000-07-17 2001-08-21 Taiwan Semiconductor Mfg Method to optimize the placement design by adjusting the reference routing
US7073154B1 (en) * 2002-05-21 2006-07-04 Altera Corporation Apparatus and methods for interconnect zones and associated cells in integrated circuits
JP2004342757A (ja) * 2003-05-14 2004-12-02 Toshiba Corp 半導体集積回路及びその設計方法

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