JP2008512942A5 - - Google Patents

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Publication number
JP2008512942A5
JP2008512942A5 JP2007531178A JP2007531178A JP2008512942A5 JP 2008512942 A5 JP2008512942 A5 JP 2008512942A5 JP 2007531178 A JP2007531178 A JP 2007531178A JP 2007531178 A JP2007531178 A JP 2007531178A JP 2008512942 A5 JP2008512942 A5 JP 2008512942A5
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JP
Japan
Prior art keywords
message
received
data memory
communication controller
message object
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007531178A
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English (en)
Japanese (ja)
Other versions
JP4860620B2 (ja
JP2008512942A (ja
Filing date
Publication date
Priority claimed from US10/936,421 external-priority patent/US8060668B2/en
Application filed filed Critical
Publication of JP2008512942A publication Critical patent/JP2008512942A/ja
Publication of JP2008512942A5 publication Critical patent/JP2008512942A5/ja
Application granted granted Critical
Publication of JP4860620B2 publication Critical patent/JP4860620B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP2007531178A 2004-09-08 2005-08-15 低遅延のデータパケット受信及び処理 Expired - Fee Related JP4860620B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/936,421 US8060668B2 (en) 2004-09-08 2004-09-08 Low latency data packet reception and processing
US10/936,421 2004-09-08
PCT/US2005/028838 WO2006028656A2 (en) 2004-09-08 2005-08-15 Low latency data packet reception and processing

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2011167338A Division JP2011239469A (ja) 2004-09-08 2011-07-29 低遅延のデータパケット受信及び処理

Publications (3)

Publication Number Publication Date
JP2008512942A JP2008512942A (ja) 2008-04-24
JP2008512942A5 true JP2008512942A5 (enExample) 2008-10-02
JP4860620B2 JP4860620B2 (ja) 2012-01-25

Family

ID=35997490

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2007531178A Expired - Fee Related JP4860620B2 (ja) 2004-09-08 2005-08-15 低遅延のデータパケット受信及び処理
JP2011167338A Pending JP2011239469A (ja) 2004-09-08 2011-07-29 低遅延のデータパケット受信及び処理

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2011167338A Pending JP2011239469A (ja) 2004-09-08 2011-07-29 低遅延のデータパケット受信及び処理

Country Status (5)

Country Link
US (1) US8060668B2 (enExample)
EP (1) EP1810117B1 (enExample)
JP (2) JP4860620B2 (enExample)
CN (1) CN101052938B (enExample)
WO (1) WO2006028656A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8060668B2 (en) * 2004-09-08 2011-11-15 Fisher-Rosemount Systems, Inc. Low latency data packet reception and processing
JP5527512B2 (ja) * 2009-09-28 2014-06-18 ソニー株式会社 バスプロトコル変換装置及びバスプロトコル変換方法
EP2595351A1 (de) * 2011-11-15 2013-05-22 Eaton Industries GmbH Vorrichtung zur Verwendung in einem digitalen Übertragungssystem, digitales Übertragungssystem und Verfahren zur Datenübertragung
US8812466B2 (en) * 2012-02-10 2014-08-19 International Business Machines Corporation Detecting and combating attack in protection system of an industrial control system
EP2974237B1 (en) * 2013-03-14 2024-03-06 Rosemount Inc. Communications unit for an industrial process network
JP5943022B2 (ja) * 2014-03-25 2016-06-29 横河電機株式会社 プロセス制御システム
JP6354387B2 (ja) 2014-06-30 2018-07-11 富士通株式会社 情報処理装置、情報処理システム及び割込装置制御方法
EP4095705A1 (en) * 2021-05-28 2022-11-30 Cetitec GmbH Communication node for data networks and busses
CN120492396B (zh) * 2025-07-16 2025-09-26 苏州元脑智能科技有限公司 通信方法、装置、系统、设备及介质

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4942515A (en) 1986-03-31 1990-07-17 Wang Laboratories, Inc. Serial communications controller with FIFO register for storing supplemental data and counter for counting number of words within each transferred frame
US4914652A (en) 1988-08-01 1990-04-03 Advanced Micro Devices, Inc. Method for transfer of data between a media access controller and buffer memory in a token ring network
US6304934B1 (en) * 1995-10-13 2001-10-16 Smar Research Corporation Computer to fieldbus control system interface
US5828851A (en) * 1996-04-12 1998-10-27 Fisher-Rosemount Systems, Inc. Process control system using standard protocol control of standard devices and nonstandard devices
US6564268B1 (en) 1999-03-17 2003-05-13 Rosemount Inc. Fieldbus message queuing method and apparatus
EP1041485A1 (en) * 1999-03-31 2000-10-04 Sony Service Center (Europe) N.V. Object with polymorphism
US6658596B1 (en) * 2000-03-13 2003-12-02 International Business Machines Corporation Automated queue recovery using element- based journaling
CN1210907C (zh) * 2000-06-29 2005-07-13 中兴通讯股份有限公司 一种通讯系统中基于系统相关性的初始化方法
US6799229B1 (en) * 2000-09-05 2004-09-28 Lsi Logic Corporation Data-burst-count-base receive FIFO control design and early packet discard for DMA optimization
US6871265B1 (en) * 2002-02-20 2005-03-22 Cisco Technology, Inc. Method and apparatus for maintaining netflow statistics using an associative memory to identify and maintain netflows
US7234084B2 (en) * 2004-02-18 2007-06-19 Emerson Process Management System and method for associating a DLPDU received by an interface chip with a data measurement made by an external circuit
US7496099B2 (en) * 2004-07-30 2009-02-24 Fisher-Rosemount Systems, Inc. Communication controller for coordinating transmission of scheduled and unscheduled messages
US7251759B2 (en) * 2004-08-16 2007-07-31 Broadcom Corporation Method and apparatus to compare pointers associated with asynchronous clock domains
US8060668B2 (en) * 2004-09-08 2011-11-15 Fisher-Rosemount Systems, Inc. Low latency data packet reception and processing

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