JP2008311551A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a plurality of stacked semiconductor chips wherein the distributed arrangement of pads on a wiring substrate is made possible, and large and small semiconductor chips can be stacked without the use of relay chips. <P>SOLUTION: The semiconductor device includes a wiring substrate 38 where a plurality of external connection terminals 46 are provided at one side and pads 38a, 38b in electrical connection with each of the external connection terminals 46 are provided at the other side, at least a pair of semiconductor chips 34, 36 arranged to be stacked up and down on the wiring substrate 38, and wires 42b, 42c for electrical connection between electrodes 34a, 36a on each of the semiconductor chips 34, 36 and the pads 38a, 38b on the wiring substrate 38. At least a pad 38b on the wiring substrate 38 corresponding to an electrode 36a on a lower semiconductor chip 36 of a pair of semiconductor chips 34, 36 is positioned immediately below an upper semiconductor chip 34. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  In the present invention, a plurality of external connection terminals are provided on one side, and a wiring board provided with pads that are in electrical communication with each external connection terminal on the other side, and disposed on the wiring board so as to overlap vertically. The present invention relates to a semiconductor device including at least one set of semiconductor chips and wires that electrically connect electrodes of each semiconductor chip and pads of a wiring board.

  Each of Patent Documents 1 to 3 discloses a ball grid array (BGA) type semiconductor device in which a plurality of semiconductor chips are stacked (stacked) on a wiring board.

FIG. 3 is a diagram showing a configuration of the semiconductor device (stacked die package) described in Patent Document 1. In FIG. FIG. 3A is a schematic perspective view from the upper surface of the semiconductor device, and FIG. 3B is a schematic cross-sectional view taken along line 4B-4B.
In the semiconductor device described in Patent Document 1, a plurality of solder balls (external connection terminals) 212 are provided on one surface (lower surface) 203 of a carrier (wiring substrate) 202 as shown in FIGS. The other surface (upper surface) 201 is provided with a pad (not shown) in electrical communication with each solder ball 212. A plurality of dies (semiconductor chips) 206 and 208 are stacked on the carrier 202. A spacer 220 is provided between the first die 206 and the second die 208, and a gap is formed between them. The sizes of the first die 206 and the second die 208 are substantially the same or exactly the same. The bonding pads (electrodes) 222 of the dies 206 and 208 are provided around the first die 206 and the second die 208, respectively. The bonding pad 222 of each die 206 and 208 and the pad (not shown) of the carrier 202 are electrically connected by a conductive wire (wire) 210. The mold compound (resin material) 214 is formed so as to cover the upper surface 201 of the carrier 202, and encapsulates the spacer 220, the first die 206, and the second die 208 (see Patent Document 1, paragraphs 0012 and 0014).

FIG. 4 is a cross-sectional view showing a configuration of the semiconductor device described in Patent Document 2. 4A is a schematic cross-sectional view of the semiconductor device 100, and FIG. 4B is a perspective view from the top surface of the semiconductor device 100.
In the semiconductor device 100 described in Patent Document 2, solder balls (external connection terminals) 16 are formed on one surface (back surface) of the substrate (wiring substrate) 2 as shown in FIGS. In addition, leads 18 penetrating the surface of the substrate 2 are provided at portions of the back surface of the substrate 2 that are in contact with the solder balls 16. A lower semiconductor chip 4 and a dummy chip 8 are mounted on the substrate 2, and an upper semiconductor chip 6 is mounted on the upper part of both so as to straddle both. The upper semiconductor chip 6 is shifted from the lower semiconductor chip 4 so as not to overlap the bonding pads (electrodes) 28 of the lower semiconductor chip 4. The bonding pads 28 and 30 of each semiconductor chip 4 and 6 and the leads 18 of the substrate 2 are electrically connected by wires 10 and 12. In this state, the semiconductor chips 4 and 6 are sealed with a synthetic resin (resin material) 14 (see paragraphs 0013-0022 of Patent Document 2).

  Patent Documents 1 and 2 describe a technique in which semiconductor chips having substantially the same size are provided in an overlapping manner. Generally, as shown in FIG. In many cases, smaller semiconductor chips 36 are provided in an overlapping manner. In such a case, as shown in FIG. 5B, the distance between the electrode 36a of the upper semiconductor chip 36 and the pad 38a on the wiring board 38 may become long. If the length of the wire is too long in accordance with this, there is a risk that a deformation (so-called wire flow) of the wire due to the mold resin will occur during resin sealing, which may cause problems such as contact between the wires. As shown in (b), the relay chip 40 is provided on the lower semiconductor chip 32, and each wire between the electrode 36 a of the upper semiconductor chip 36 and the pad 38 a on the wiring substrate 38 is connected to the relay chip 40. In some cases, it is necessary to divide the wire into two wires 42d and 44 by relaying to shorten the length of each wire.

JP 2002-57272 A JP 2004-71947 A Utility Model Registration No. 3096721

  In the conventional semiconductor device described above, it is necessary to dispose all pads on the wiring board side corresponding to the electrodes of all the stacked semiconductor chips on the outer peripheral portion of the semiconductor chip mounting region on the wiring board. For this reason, when the number of electrodes is large, for example, as shown in the region X of FIG. 5 (b) (indicated by a broken line), the pads are concentrated on a part of the wiring board, and the density of the pads is increased. Since it is also necessary to provide the wires to be densely arranged, there is a problem that it is technically difficult to perform wire bonding so as not to cause a short circuit or the like. This also hinders high integration.

  In addition, when a smaller semiconductor chip is mounted on a larger semiconductor chip, it may be necessary to use a relay chip as described above, and there is a problem that design and manufacturing costs may increase.

  The present invention has been made to solve the above-mentioned problems, and its main purpose is to make it possible to disperse the arrangement of pads on a wiring board in a semiconductor device having a plurality of stacked semiconductor chips. A secondary purpose thereof is to make it possible to stack large and small semiconductor chips without using relay chips.

In order to solve the above problems, a semiconductor device according to the present invention has the following configuration. That is, a wiring board provided with a plurality of external connection terminals on one surface and a pad electrically connected to each external connection terminal on the other surface, and at least disposed on the wiring board so as to overlap vertically A pair of semiconductor chips, and wires that electrically connect the electrodes of the semiconductor chips and the pads of the wiring board, and correspond to the electrodes of the lower semiconductor chip of the set of semiconductor chips Further, at least a part of the pads of the wiring board is provided so as to be located immediately below the upper semiconductor chip.
According to this, a part of the pads on the wiring board is provided at a position overlapping the mounting position of the upper semiconductor chip, so that the arrangement of the pads on the wiring board can be dispersed. In addition, since a pad is provided directly under the semiconductor chip, a smaller semiconductor chip is disposed below the large semiconductor chip, and the electrode of the small semiconductor chip on the lower side and the pad directly below the large semiconductor chip are connected at a short distance. Bonding is also possible, and a design without a relay chip is possible.

  Furthermore, at least a part of the electrodes of the lower semiconductor chip corresponding to the pads positioned immediately below the upper semiconductor chip are provided so as to be positioned immediately below the upper semiconductor chip. To do.

Further, the upper semiconductor chip is disposed on a spacer material or another semiconductor chip provided so that the upper end surface is higher than the upper surface of the lower semiconductor chip, so that the pair of semiconductor chips A gap is formed in the vertical direction between the wires, and a wire connected to a pad located immediately below the upper semiconductor chip is provided through the gap.
According to this, a wire can be provided through the gap.

Furthermore, the upper semiconductor chip is arranged between a plurality of the spacer materials or the other semiconductor chips.
According to this, the upper semiconductor chip can be stably disposed.

  Furthermore, at least a part of the pads located immediately below the upper semiconductor chip is disposed between the plurality of spacer materials or other semiconductor chips.

  Further, the lower semiconductor chip is disposed between the plurality of spacer materials or other semiconductor chips.

  Further, at least one of the spacer material and the other semiconductor chip is arranged on the lower semiconductor chip.

  According to the semiconductor device of the present invention, it is possible to disperse the arrangement of the pads on the wiring board, and it is possible to provide a large and small semiconductor chip in an overlapping manner without using a relay chip.

  The best mode for carrying out a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings.

1A and 1B are explanatory views showing a configuration of a semiconductor device A according to Embodiment 1 of the present invention, in which FIG. 1A is a cross-sectional view and FIG. 1B is a plan view seen from above.
As illustrated in FIG. 1, the semiconductor device A according to the first embodiment includes a wiring board 38 and a plurality of semiconductor chips 32, 34, and 36.

  A plurality of solder balls 46 as a plurality of external connection terminals are provided on one surface (lower surface) of the wiring board 38 (see FIG. 1A). On the other surface (upper surface) of the wiring board 38, pads 38a and 38b that are in electrical communication with the solder balls 46 by a wiring pattern (not shown) in the wiring board 38 are provided (see FIG. 1B).

A plurality (three) of semiconductor chips 32, 34, and 36 are stacked and disposed on the other surface (upper surface) of the wiring substrate 38 so as to overlap vertically. In the first embodiment, the first semiconductor chip 32 is disposed on the top, the second semiconductor chip 34 having a planar area larger than that of the first semiconductor chip 32 is disposed on the lower side, and further the plane is disposed on the lower side. A third semiconductor chip 36 having the smallest area is arranged.
In FIG. 1 (b), the broken line portion is a perspective view of the first and second semiconductor chips 32 and 34, and the components on the lower side thereof are displayed.

The present invention relates to a semiconductor device including at least one set (that is, two or more) of semiconductor chips arranged so as to overlap each other, and at least one of a combination of arbitrary semiconductor chips in an upper and lower stacked relationship. A set that falls within the configuration of the “lower semiconductor chip” and the “upper semiconductor chip” in the present invention is included in the technical scope of the present invention.
Hereinafter, the second semiconductor chip 34 in Example 1 is referred to as an “upper semiconductor chip” according to the present invention, and the third semiconductor chip 36 is referred to as a “lower semiconductor chip” according to the present invention. Give an explanation.

As shown in FIG. 1A, an upper end surface is formed on the other surface (upper surface) of the wiring substrate 38 so as to be higher than the upper surface of the lower semiconductor chip (third semiconductor chip) 36. A first spacer material 48 is provided. That is, the thickness of the first spacer material 48 is formed to be thicker than the thickness of the lower semiconductor chip (third semiconductor chip) 36.
On the lower semiconductor chip (third semiconductor chip) 36, a second spacer material 50 having an upper end surface formed at the same height as the upper surface of the first spacer material 48 is provided. That is, the thickness of the second spacer material 50 is formed such that the sum of the thickness of the lower semiconductor chip (third semiconductor chip) 36 is equal to the thickness of the first spacer material 48.
The upper semiconductor chip (second semiconductor chip) 34 is disposed across the two spacer members 48 and 50.
With the above configuration, a gap 52 is formed in the vertical direction between the pair of semiconductor chips (the second semiconductor chip 34 and the third semiconductor chip 36).

  Adjacent semiconductor chips 32, 34, 36, spacer materials 48, 50 and wiring board 38 are provided by being bonded with an adhesive.

The spacer materials 48 and 50 are not particularly limited, but are configured as dummy chips made of silicon, for example.
Other semiconductor chips can be used instead of the spacer material (dummy chip). For example, instead of the spacer material 48, another semiconductor chip thicker than the third semiconductor chip 36 may be employed. In this case, the electrodes of the other semiconductor chips are exposed to the outside of the second semiconductor chip 34 (when viewed in plan) without overlapping the second semiconductor chip 34 above the other semiconductor chip. These electrodes are also provided so that wire bonding can be performed.
Similarly, other semiconductor chips may be employed in place of the second spacer material 50 on the third semiconductor chip 36. In this case, similarly, the electrodes of the other semiconductor chips are provided so as to be exposed outside the second semiconductor chip 34 without overlapping the second semiconductor chip 34 thereon. Further, if necessary, for example, the electrode 36a of the third semiconductor chip 36 is placed on the other spacer than the other semiconductor chip so that the electrode 36a of the third semiconductor chip 36 does not overlap with the other semiconductor chip thereon. It is preferable to arrange it so as to be exposed on the side of the material 48 (right side in FIG. 1) (the third semiconductor chip 36 is arranged in the direction opposite to the left and right in FIG. 1).

In the semiconductor device A according to the first embodiment, the lower semiconductor chip (third semiconductor chip) 36 and some pads 38b of the wiring board 38 corresponding to the electrodes 36a of the lower semiconductor chip 36 are provided. The upper semiconductor chip (second semiconductor chip) 34 is located immediately below.
In the present application, “directly below the upper semiconductor chip” refers to a portion that overlaps the upper semiconductor chip in the vertical direction (the stacking direction of the semiconductor chips or the direction perpendicular to the wiring board surface). In other words, it is a location included in an image projected onto the wiring substrate of the upper semiconductor chip.

The semiconductor device A also includes wires 42a, 42b, and 42c that connect the electrodes 32a, 34a, and 36a of the semiconductor chips 32, 34, and 36 to the pads 38a and 38b of the wiring board 38, respectively. Among these, the wire 42c connected to the pad 38b located immediately below the upper semiconductor chip (second semiconductor chip) 34 is between the pair of semiconductor chips (second semiconductor chip 34 and third semiconductor chip 36). (See FIG. 1A).
The thickness of the first and second spacer members 48 and 50 is provided so as to ensure a gap 52 sufficient to pass the wire 42c. Although not particularly limited, if the width of the gap 52 is set to 60 to 80 μm or more, the wire 42c can be sufficiently passed.

  Further, the semiconductor device A includes the other surface (upper surface) of the wiring board 38, the first to third semiconductor chips 32, 34, 36, the first to second spacer members 48, provided on the surface. 50 and a sealing resin 54 for sealing the wires 42a, 42b, and 42c.

Next, the configuration of the semiconductor device B according to the second embodiment of the present invention will be described. 2A and 2B are explanatory views showing the configuration of the semiconductor device B according to the second embodiment of the present invention, where FIG. 2A is a cross-sectional view and FIG. 2B is a plan view seen from above. In FIG. 2B, the broken line portion is a perspective view of the components below the first and second semiconductor chips 32 and 34.
In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof is omitted, and differences from the first embodiment are described.

  In the second embodiment, unlike the configuration of the second spacer member 50 of the first embodiment, as shown in FIG. 2A, the second spacer member 51 is a lower semiconductor chip (third semiconductor chip). It is provided on the upper surface of the wiring board 38, not directly on the board 36, but directly attached.

The first spacer material 48 and the second spacer material 51 are provided so that the upper end surfaces are higher than the upper surface of the lower semiconductor chip (third semiconductor chip) 36. That is, the thickness of the first spacer material 48 and the second spacer material 51 is formed to be thicker than the thickness of the lower semiconductor chip (third semiconductor chip) 36.
The upper semiconductor chip (second semiconductor chip) 34 is disposed across the two spacer members 48 and 51.
With the above configuration, a gap 53 is formed in the vertical direction between the pair of semiconductor chips (second semiconductor chip 34 and third semiconductor chip 36).
The thickness of the first and second spacer members 48 and 51 is provided so as to ensure a gap 53 sufficient to pass the wire 42c. Although not particularly limited, if the width of the gap 53 is set to 60 to 80 μm or more, the wire 42c can be sufficiently passed.

  The lower semiconductor chip (third semiconductor chip) 36 is disposed between the first spacer material 48 and the second spacer material 51. Further, as shown in FIG. 2B, the pad 38b corresponding to the electrode 36a of the lower semiconductor chip (third semiconductor chip) 36 is also located immediately below the upper semiconductor chip (second semiconductor chip) 34. At the same time, it is disposed between the first spacer material 48 and the second spacer material 51.

According to the semiconductor devices A and B according to the first and second embodiments, since some pads 38b of the wiring board 38 are provided at positions where they overlap the mounting positions of the upper semiconductor chip 34, all of them are conventionally provided. Compared to the configuration in which the pads are arranged on the outer peripheral portion of the mounting position of the semiconductor chip, the arrangement of the pads on the wiring board can be dispersed.
Also, a smaller semiconductor chip 36 is disposed below the larger semiconductor chip 34, and the electrodes 36a of the lower smaller semiconductor chip 36 and the pads 38b immediately below the larger semiconductor chip 34 are wire-bonded at a short distance. Therefore, it is possible to design without using a relay chip as in the prior art.

  When manufacturing the semiconductor devices A and B according to the first and second embodiments, the lower semiconductor chip (third semiconductor chip) 36 is first bonded onto the wiring substrate 38, and the electrodes 36a and 36 The pads 38b on the wiring board 38 are wire-bonded. Subsequently, the first and second spacer members 48 and 50 (51) are provided on the wiring substrate 38 or on the lower semiconductor chip (third semiconductor chip) 36, and the second semiconductor chip 34 is bonded thereon. Further, the first semiconductor chip 32 is bonded onto the second semiconductor chip 34. Then, the electrodes 32a and 34a of the first and second semiconductor chips 32 and 34 and the pads 38a on the wiring board 38 are wire-bonded.

Subsequently, the other surface (upper surface) of the wiring board 38, and the first to third semiconductor chips 32, 34, and 36, and the first to second spacer members 48 and 50 (51) provided on the other surface. The wires 42a, 42b, and 42c are sealed with resin to form a sealing resin 54.
In this resin sealing process, if the transfer molding method is used, the tunnel-shaped gap formed between the upper semiconductor chip 34 and the wiring substrate 38 may not be completely filled with the resin. It is desirable to use

In the first and second embodiments, the entire lower semiconductor chip (third semiconductor chip) 36 is directly below the upper semiconductor chip (second semiconductor chip) 34. It is not limited to. For example, the lower semiconductor chip may be provided off the upper semiconductor chip, and at least a part of the pads corresponding to the electrodes of the lower semiconductor chip may be provided immediately below the upper semiconductor chip. Further, the lower semiconductor chip may be disposed so that only a part of the electrode is located directly below the upper semiconductor chip.
Further, the wiring board and the pads corresponding to the electrodes of the lower semiconductor chip are not necessarily limited to the configuration in which all of them are provided directly below the upper semiconductor chip. That is, only a part of the pads corresponding to the electrodes of the lower semiconductor chip is disposed immediately below the upper semiconductor chip, and the other pads are disposed at positions away from directly below the upper semiconductor chip. Also good.

BRIEF DESCRIPTION OF THE DRAWINGS It is explanatory drawing which shows the semiconductor device which concerns on Example 1 of this invention, (a) is sectional drawing, (b) is a top view. It is explanatory drawing which shows the semiconductor device which concerns on Example 2 of this invention, (a) is sectional drawing, (b) is a top view. It is explanatory drawing which shows the conventional semiconductor device, (a) is a top view, (b) is sectional drawing. It is explanatory drawing which shows the conventional semiconductor device, (a) is sectional drawing, (b) is a top view. It is explanatory drawing which shows the conventional semiconductor device, (a) is sectional drawing, (b) is a top view.

Explanation of symbols

A, B Semiconductor device 32 First semiconductor chip 34 Second semiconductor chip (upper semiconductor chip)
36 Third semiconductor chip (lower semiconductor chip)
32a, 34a, 36a Electrode 38 Wiring board 38a Pad 38b Pad (pad just below the upper semiconductor chip)
42a, 42b, 42c Wire 46 Solder ball (external connection terminal)
48, 50, 51 Spacer material 52, 53 Gap 54 Sealing resin

Claims (7)

A wiring board provided with a plurality of external connection terminals on one surface and pads provided on the other surface in electrical communication with each external connection terminal;
On the wiring board, at least one set of semiconductor chips disposed so as to overlap vertically, and
A wire for electrically connecting the electrode of each semiconductor chip and the pad of the wiring board;
At least a part of the pads of the wiring board corresponding to the electrodes of the lower semiconductor chip of the set of semiconductor chips is provided so as to be located immediately below the upper semiconductor chip. Semiconductor device.   The at least part of the electrode of the lower semiconductor chip corresponding to the pad positioned immediately below the upper semiconductor chip is provided so as to be positioned immediately below the upper semiconductor chip. Item 14. A semiconductor device according to Item 1. The upper semiconductor chip is arranged on a spacer material or another semiconductor chip provided so that the upper end surface is higher than the upper surface of the lower semiconductor chip, so that the upper semiconductor chip is interposed between the pair of semiconductor chips. Has a gap in the vertical direction,
3. The semiconductor device according to claim 1, wherein a wire connected to a pad located immediately below the upper semiconductor chip is provided through the gap.   4. The semiconductor device according to claim 3, wherein the upper semiconductor chip is disposed between a plurality of the spacer materials or the other semiconductor chips.   5. The semiconductor device according to claim 4, wherein at least a part of the pads located immediately below the upper semiconductor chip is disposed between the plurality of spacer materials or other semiconductor chips.   6. The semiconductor device according to claim 4, wherein the lower semiconductor chip is disposed between the plurality of spacer materials or other semiconductor chips.   6. The semiconductor device according to claim 3, wherein at least one of the spacer material and the other semiconductor chip is disposed on the lower semiconductor chip.

Images