JP2008300672A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize a semiconductor device having a plurality of built-in semiconductor elements stacked. <P>SOLUTION: The semiconductor device 10A is provided with a first semiconductor element 12 fixed on a first island 16 and a second semiconductor element 14 fixed on a second island 18, wherein the first island 16, the first semiconductor element 12, the second island 18 and the second semiconductor element 14 are disposed so as to be superimposed. Further, the first semiconductor element 12 is disposed on the upper surface of the first island 16 and the second semiconductor element 14 is disposed on the lower surface of the second island 18. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a plurality of semiconductor elements arranged in a stacked manner.

  In general, a semiconductor device using a lead frame has an island and a plurality of leads each having one end provided around the island. A semiconductor element is fixed to the upper surface of the island, and a bonding pad and a lead of the semiconductor element are connected by a thin metal wire (for example, Patent Document 1). Furthermore, the island, the lead, the semiconductor element, and the fine metal wire are sealed with an insulating resin so that the end portion of the lead is exposed. Here, in the lead, a portion sealed with the insulating resin is referred to as an inner lead, and a portion exposed from the insulating resin is referred to as an outer lead. The outer lead is bent as necessary, and the other end of the lead is mounted on a printed circuit board or the like by solder or the like.

A stack-type semiconductor device in which a plurality of chips are stacked on an island has also been realized. In this case, a child chip having a size smaller than that of the parent chip is stacked on the parent chip, and both the parent chip and the child chip are electrically connected by a thin metal wire.
JP 2007-5569 A

  However, the semiconductor device having the above-described configuration can be reduced in size by the recent thin, thin and small technology. However, the upper surface of the child chip is arranged at a higher position from the surface of the island than the upper surface of the parent chip. Therefore, when a thin metal wire is connected to the upper surface of the child chip, there is a problem that the top of the thin metal wire becomes higher and the thickness of the semiconductor device, that is, the thickness of the package becomes thicker.

  Further, it is possible to arrange the semiconductor elements in the horizontal direction inside the semiconductor device, but there is a problem that the semiconductor device is increased in size when the number of built-in semiconductor elements is increased.

  Accordingly, an object of the present invention is to provide a small semiconductor device in which a plurality of chips are stacked and arranged.

  The semiconductor device of the present invention is a semiconductor device having a plurality of semiconductor elements arranged in a stacked manner, and leads that are electrically connected to the semiconductor elements and partially exposed to the outside, the first island, A first semiconductor element fixed to the first island; a first lead exposed continuously from the first island; a second island; a second semiconductor element fixed to the second island; A second lead continuously exposed from the second island to the outside, wherein the first island, the first semiconductor element, the second island, and the second semiconductor element are arranged to overlap each other. Features.

  According to the present invention, since a plurality of islands and semiconductor elements are arranged so as to overlap with each other, a semiconductor device in which a plurality of semiconductor elements are stacked can be made smaller.

  Furthermore, according to the present invention, the distance between the first island and the second island on which both semiconductor elements are mounted is shortened by reversing the direction of the surface on which the first semiconductor element and the second semiconductor element are mounted. (See FIG. 2). Therefore, the thickness of the semiconductor device can be reduced, and heat generated from one semiconductor element can be favorably released to the outside through both the first island and the second island.

  Furthermore, referring to FIG. 5, according to the present invention, the first semiconductor element is mounted on the upper surface of the first island, and the second semiconductor element is mounted on the upper surface of the second island. That is, both semiconductor elements are mounted on the upper surface of the island. This eliminates the need to reverse the lead frame on which the semiconductor element is mounted in the manufacturing process for assembling the semiconductor device, thereby simplifying the manufacturing process and improving the yield.

  Furthermore, referring to FIG. 6, when both semiconductor elements are mounted on the lower surfaces of both islands, the semiconductor elements can be accommodated in the space formed by the inclined portions of the leads, so that the semiconductor device can be further reduced in size. Can be made.

  Furthermore, referring to FIG. 7, according to the present invention, in addition to a plurality of islands and semiconductor elements, lead connection portions are also arranged so as to overlap, so that the semiconductor device can be further miniaturized.

  The configuration of the semiconductor device of the present embodiment will be described with reference to FIGS. 1 to 4 are views showing a semiconductor device 10A. 5 to 7 are diagrams each showing the structure of another form of semiconductor device.

  First, the configuration of a semiconductor device 10A that is a basic form of the present embodiment will be described with reference to FIGS. 1A is a perspective view of the semiconductor device 10A, FIG. 1B is a plan view of the semiconductor device 10A viewed from above, and FIG. 1C is a plan view of the semiconductor device 10A viewed from below. It is. 2 is a cross-sectional view of the semiconductor device 10A, and FIGS. 3 and 4 are perspective views showing a part of leads constituting the semiconductor device 10A.

  Referring to FIG. 1A, a semiconductor device 10A has a substantially cubic shape or a substantially rectangular parallelepiped outer shape, the upper surface and the lower surface are parallel flat surfaces, and the upper side of the side surface is lower than the lower side. It consists of an inclined surface that inclines inward. Then, end portions of the plurality of leads electrically connected to the built-in semiconductor element protrude to the outside from the lower portion of the side surface of the sealing resin 23 that integrally seals the whole. These leads protrude outside from two opposing sides of the sealing resin 23. Further, the lower surface of the lead exposed to the outside and the lower surface of the sealing resin 23 are located on the same plane. The mounting of the semiconductor device 10A is performed in a reflow process in which a solder cream (not shown) attached to the exposed leads is heated and melted in the solder.

  1A and 1B, a schematic configuration of a semiconductor device 10A includes a first semiconductor element 12 fixed to an upper surface of a first island 16 and a second semiconductor element fixed to a lower surface of a second island 18. 14, leads that are electrically connected to each semiconductor element and led out to the outside, and a sealing resin 23 that covers and integrally supports these leads. Furthermore, the first island 16, the second island 18, the first semiconductor element 12, and the second semiconductor element 14 are arranged so as to overlap in the thickness direction of the semiconductor device 10 </ b> A.

  A planar configuration of the semiconductor device 10A viewed from above will be described with reference to FIG. 1B. A substantially quadrangular first island 16 is disposed near the center of the semiconductor device 10A. Then, two leads 20G and 20F are continuously led out from the lower side of the first island 16 on the paper surface. These two leads 20G and 20F may be electrically connected to the back electrode (for example, the drain electrode of the MOSFET) of the first semiconductor element 12 or may not be connected.

  Further, two leads 20D and 20H are arranged close to the left side of the first island. A lower portion of the lead 20D on the paper surface is a bonding portion 22, and this portion is connected to the electrode 32 of the first semiconductor element 12 through a thin metal wire 30A. The upper portion of the lead 20H is a bonding portion 24, and this portion is connected to the two electrodes 32 of the first semiconductor element 12 via the two thin metal wires 30B and 30C.

  As described above, the fine metal wires 30A and the like function as connecting means for electrically connecting the electrodes 32 of the first semiconductor element 12 and the bonding portions 22 of the leads 20D. The fine metal wires 30A and the like are made of a metal material such as gold or aluminum having a diameter of about several tens of μm. Here, as the connection means, it is possible to employ other than the metal thin wire, and as an example, a single metal plate formed into a predetermined shape can be employed as the connection means.

  For example, when the first semiconductor element 12 is a MOSFET, one gate electrode (control electrode: electrode 32 here) provided on the upper surface of the first semiconductor element 12 is bonded to the lead 20D via the metal thin wire 30A. The unit 22 is connected. Further, two other electrodes 32 that are source electrodes (main electrodes) are connected to the bonding portion 24 of the lead 20H via the two thin metal wires 30B and 30C. Since the source electrode of the MOSFET is the main electrode through which a relatively large current passes, the electrical resistance of the fine metal wire is reduced by connecting it to the lead using a larger number of fine metal wires than the gate electrode that is the control electrode. As a result, the on-resistance can be reduced. The back surface of the first semiconductor element 12 is electrically connected to the upper surface of the first island 16 as a drain electrode (main electrode), for example. Further, by making the bonding portion 24 of the lead 20H longer (the area is larger) than the bonding portion 22 of the lead 20D, it is possible to facilitate the connection of the fine metal wires.

  The sealing resin 23 has a function of covering each semiconductor element and the lead frame and integrally supporting them. As the resin material of the sealing resin 23, a thermosetting resin (for example, epoxy resin) formed by transfer molding or a thermoplastic resin (for example, acrylic resin) formed by injection molding is employed. In addition, a resin material filled with a filler such as a metal oxide may be used as the sealing resin 23 for the purpose of lowering thermal resistance. Here, the sealing resin 23 integrally covers leads, islands, semiconductor elements, and fine metal wires. Furthermore, the end portion of each lead is exposed to the outside from the sealing resin 23, and this portion functions as a terminal for external connection.

  Referring to FIG. 1C, a second semiconductor element 14 is fixed to the center of the lower surface of the second island 18, and the electrode provided on the upper surface of the second semiconductor element 14 is a fine metal wire. It is electrically connected to the lead 20A etc. via 31A etc. Specifically, the lower portion of the lead 20A on the paper surface is a bonding portion 26, and the upper portion of the lead 20E is a bonding portion 28. The upper surface of the bonding portion 26 of the lead 20A is electrically connected to the electrode 36 of the second semiconductor element 14 via the metal thin wire 31A. On the other hand, the bonding portion 28 of the lead 20E is connected to the electrode 36 of the second semiconductor element 14 via the two fine metal wires 31B and 31C.

  As the second semiconductor element 14, various semiconductor devices can be adopted in the same manner as the first semiconductor element. Here, when the second semiconductor element 14 is a MOSFET, the gate electrode on the upper surface is connected to the bonding portion 26 of the lead 20A via one metal thin wire 31A. The other two source electrodes (electrodes 32) of the second semiconductor element 14 are connected to the bonding portion 28 of the lead 20E via the two thin metal wires 31B and 31C.

  Further, the two leads 20C and 20B are led out from the upper side of the second island 18 on the paper surface until they reach the outside.

  The first island 16 and the second island 18 may be arranged so that their outer edges overlap (that is, both overlap completely or almost completely), or are arranged so that a part of them overlaps. May be. Furthermore, the first semiconductor element and the second semiconductor element may also be arranged so that their outer edges overlap, or may be overlapped so that a part of both is arranged.

  As a combination of the two semiconductor elements, a combination of ICs, discrete transistors, a combination of discrete transistors and ICs, and the like can be considered. Here, as the discrete transistor, for example, a MOSFET, an IGBT, a bipolar transistor, or the like can be considered. Furthermore, a diode may be employed as a semiconductor element.

  Referring to FIGS. 1B and 1C, leads and lands (first lead frames) that are densely hatched are portions that contribute to mounting and connection of the first semiconductor element 12. On the other hand, leads and lands (second lead frames) that are roughly hatched are parts that contribute to mounting and connection of the second semiconductor element 14. Referring to FIG. 1B, the first lead frame includes a first island 16 and leads 20D and 20H, which are located on the same plane. Referring to FIG. 1C, the second lead frame includes a second island 18 and leads 20A and 20E, which are located on the same plane. 1A, the first lead frame connected to the first semiconductor element 12 is located above the second lead frame connected to the second semiconductor element 14.

  Here, the first lead frame described above is shown in FIG. 3, and the second lead frame is shown in FIG.

  Here, in the manufacturing process, the first lead frame and the second lead frame described above are prepared separately. That is, in the semiconductor manufacturing process, a die bonding process for fixing the semiconductor element to the island and a wire bonding process for connecting the semiconductor element and the conductive member with a fine metal wire are required. In this embodiment, the die bonding process and the wire bonding process are individually performed on the first lead frame and the second lead frame, and then both are superimposed to perform resin sealing. In this way, a semiconductor device in which a plurality of semiconductor elements and islands are stacked in one package can be manufactured by a relatively simple process.

  Next, a sectional configuration of the semiconductor device 10A will be described with reference to each sectional view of FIG. 2A is a cross-sectional view taken along the line AA ′ in FIG. 1A, and FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG. It is.

  Referring to FIG. 2A, the first island 16 and the bonding portion 24 are located on the same plane in the upper part inside the sealing resin 23. The first semiconductor element 12 is fixed to the upper surface of the first island 16 via a conductive adhesive such as solder. Here, if the back surface of the first semiconductor element 12 does not require conduction, the back surface of the first semiconductor element 12 is fixed to the upper surface of the first island 16 with an insulating adhesive such as epoxy resin. May be. And the electrode provided in the upper surface of the 1st semiconductor element 12 is connected with the upper surface of the bonding part 24 via the metal fine wire 30B.

  On the other hand, the second island 18 and the bonding part 28 are located on the same plane in the lower part inside the sealing resin 23. The related configuration of the second island 18, the bonding part 28, and the second semiconductor element 14 is the same as that of the first island 16, the bonding part 24, and the first semiconductor element 12, and only the vertical direction is reversed.

  Specifically, the second semiconductor element 14 is fixed to the lower surface of the second island 18 via a fixing agent. And the electrode provided in the lower surface of the 2nd semiconductor element 14 is connected with the lower surface of the bonding part 28 via the metal fine wire 31B.

  With reference to FIG. 2B, the lead 20C is exposed to the outside from the inclined portion 40 (continuous portion) inclined continuously downward to the outside continuously with the first island 16, and from the sealing resin 23, and The lower surface is composed of an exposed portion 42 located on the same plane as the lower surface of the sealing resin 23. This configuration is the same for other leads. Here, the inclined portion 40 is formed so as to protrude in a direction (downward here) in which the second semiconductor element 14 is fixed to the second island 18. The inclined portion 40 may have a linear shape or a curved shape. The inclined portion 40 is formed into a predetermined shape by punching using a mold.

  In this embodiment, the first semiconductor element 12, the first island 16, the second semiconductor element 14, and the second island are arranged so as to overlap each other. As a result, a semiconductor device in which a large number of semiconductor elements are stacked in a package can be reduced in size.

  Further, referring to FIG. 2A, the first semiconductor element 12 is mounted on the upper surface of the first island 16, and the second semiconductor element 14 is mounted on the lower surface of the second island 18. As a result, the lower surface of the first island 16 and the upper surface of the second island 18 can be brought very close to each other. Therefore, the thickness required for stacking the semiconductor elements and the islands can be shortened, so that the semiconductor device 10A can be made thinner.

  Further, since the first island 16 and the second island 18 are very close to each other inside the sealing resin 23, the heat generated from one semiconductor element is released to the outside via both islands. Can do. For example, the heat generated from the first semiconductor element 12 can be released to the outside via the first island 16 and the second island 18 (finally via leads led out from both islands to the outside). it can.

  Next, with reference to FIGS. 5 to 7, the configuration of another form of semiconductor device 10B will be described. FIG. 5 is a diagram showing another semiconductor device 10B, FIG. 6 is a diagram showing another semiconductor device 10C, and FIG. 7 is a diagram showing another semiconductor device 10D. The configurations of the other semiconductor devices shown in these drawings are basically the same as those of the semiconductor device 10A described above, and will be described below with a focus on the differences.

  FIG. 5 shows a configuration of another form of semiconductor device 10B. Here, FIG. 5A corresponds to a cross-sectional view taken along line AA ′ shown in FIG. 1A, and FIG. 5B is a cross-sectional view taken along line BB ′ in FIG. It corresponds to the figure.

  Referring to FIGS. 5A and 5B, the difference between the semiconductor device 10A and the semiconductor device 10B described above is that the semiconductor element is mounted on the island. Here, both semiconductor elements are fixed to the upper surface of the island. That is, the first semiconductor element 12 is fixed to the upper surface of the first island 16, and the second semiconductor element 14 is also fixed to the upper surface of the second island 18.

  With reference to FIG. 5B, the direction in which the two semiconductor elements are fixed will be further described. In the direction in which the first semiconductor element 12 and the second semiconductor element are fixed to the island, the inclined portion 40 of the lead 20C has a thickness. It is opposite to the direction extending (protruding) in the direction.

  In this way, by fixing both semiconductor elements to the upper surface of each island, it is not necessary to reverse the island on which the semiconductor elements are mounted in the manufacturing process, thereby simplifying the manufacturing process and increasing the yield. Be improved.

  6A and 6B, here, both semiconductor elements are fixed to the lower surface of the island. That is, the first semiconductor element 12 is mounted on the lower surface of the first island 16, and the second semiconductor element 14 is fixed to the lower surface of the second island 18. Referring to FIG. 6B, both semiconductor elements are accommodated in a space surrounded by the inclined portion of the lead. Therefore, with this configuration, it is possible to further reduce the thickness of the semiconductor device 10C in which the superimposed semiconductor elements are stored. In other words, in this case, the direction in which the two semiconductor elements are fixed to the two islands is the same as the direction in which the inclined portion of the lead protrudes.

  Although not shown, the first semiconductor element 12 may be mounted on the lower surface of the first island 16 and the second semiconductor element 14 may be fixed to the upper surface of the second island 18.

  With reference to FIG. 7, the configuration of another form of semiconductor device 10D will be described. FIG. 7A is a plan view of the semiconductor device 10D, and FIG. 7B is a cross-sectional view of the semiconductor device 10D.

  Referring to FIGS. 7A and 7B, a feature of the configuration of semiconductor device 10D is that lead connection portions partially overlap each other.

  The schematic configuration of the semiconductor device 10D will be described. The first island 16 to which the first semiconductor element 12 is fixed and the second island 18 to which the second semiconductor element 14 is fixed are arranged so as to overlap each other. Two leads 20A and 20C are led out from the left side of the first island 16 to the outside. Further, two leads 20B and 20D are led out from the left side of the second island 18 to the outside.

  Further, the electrode on the upper surface of the first semiconductor element is connected to the upper surface of the connection portion A1 (bonding portion) of the lead 20H via the fine metal wire 30A. Then, the other electrode on the upper surface of the first semiconductor element is connected to the connection portion A3 of the lead 20F via the thin metal wire 30D. Further, although not shown, each of the electrodes of the second semiconductor element is connected to the connecting portion A2 of the lead 20G and the connecting portion A4 of the lead 20E via the thin metal wire 30B and the thin metal wire 30C.

  Referring to FIG. 7A, a plurality of leads 20H and the like are arranged on the right side of the semiconductor device 10D, and the connection portion A1 of the lead 20H and the connection portion A2 of the lead 20G partially overlap each other. Here, the connection part A1 electrically connected to the first semiconductor element 12 is positioned above the connection part A3 connected to the second semiconductor element 14, and both are partially overlapped.

  Since the lead connection portions are partially overlapped with each other in this manner, even when a large number of leads are built in the semiconductor device 10D, there is no need to separate the connection portions of the leads in a plan view. The planar size of can be reduced.

  Here, referring to FIG. 7B, the first semiconductor element 12 is fixed to the upper surface of the first island 16, and the second semiconductor element 14 is fixed to the lower surface of the second island 18. May be secured to the other surface of each island. That is, the first semiconductor element 12 may be fixed to the lower surface of the first island 16, and the second semiconductor element 14 may be fixed to the upper surface of the second island 18.

  Next, a method for manufacturing the semiconductor device 10A having the above-described configuration will be described with reference to FIGS. In this embodiment, die bonding and wire bonding are individually performed on two lead frames (the lead frame 50 shown in FIG. 8 and the lead frame 60 shown in FIG. 9), and both are laminated, and then resin sealing is performed. Manufactures semiconductor devices.

  The configuration of the lead frame 50 will be described with reference to FIG. FIG. 8A is a plan view partially showing the lead frame 50, and FIG. 8B is an enlarged perspective view showing the unit 52.

  Referring to FIG. 8A, the lead frame 50 is made of a metal such as copper and is formed into a predetermined shape by processing (etching or punching) a single conductive foil having a thickness of about 0.5 mm. It is a thing. Here, the lead frame 50 has a roughly strip shape. An outer frame 54 is provided in a frame shape on the four sides of the lead frame 50, and a connecting portion 58 extends in a lattice shape inside the outer frame 54.

  Further, a guide hole 56 is provided through the outer frame 54 in the thickness direction. The guide hole 56 is used for conveyance and positioning in each process. Further, the guide hole 56 provided in the lead frame 50 shown in FIG. 8A and the guide hole 66 of the lead frame 60 shown in FIG. Accurate alignment is possible.

  With reference to FIG. 8B, a unit 52 is provided inside the connecting portion 58. The unit 52 is an element unit constituting one semiconductor device. Here, one unit 52 corresponds to a portion where dense hatching is applied in FIG. Specifically, three leads (lead 20H, lead 20G, and lead 20F) extend inward from the connecting portion 58 on the back side of the paper. The lead 20G and the lead 20F are continuous with the first island 16. A bonding portion 22 is provided at the tip of the lead 20D. Then, one lead 20 </ b> D having the bonding portion 24 at the distal end extends from the connecting portion 58 on the front side of the drawing to the inside. Further, each lead includes the inclined portion 40 and the exposed portion 42 shown in FIG. Further, the leading end portion inside the unit 52 of each lead and the first island 16 are located on the same plane above other portions (the outer frame 54 and the connecting portion 58) of the lead frame 50.

  Here, as described above, in this embodiment, one semiconductor device is configured by superimposing the lead frame 50 and the lead frame 60 (see FIG. 9). Here, when viewing the manufactured semiconductor device 10A (see FIG. 1), the lower surface of the exposed portion of each lead is located on the same plane. Therefore, pressing may be performed so that each lead protrudes upward (in the thickness direction) at a joint portion between each lead of the lead frame 50 and the connecting portion 58. As a result, the end portion of the lead included in the lead frame 50 and the end portion of the lead included in the lead frame 60 can be positioned on the same plane. The same applies to the lead frame 60 whose structure will be described in detail below.

  The configuration of the lead frame 60 will be described with reference to FIG. FIG. 9A is a plan view of the lead frame 60, and FIG. 9B is a perspective view showing the unit 62. Here, the lead frame 60 is a portion subjected to rough hatching shown in FIG. Furthermore, the lead frame 50 shown in FIG. 8 is different from the lead frame 60 shown here only in the internal configuration of the unit 62, and the other configurations are basically the same.

  Referring to FIG. 9A, the lead frame 60 has a shape in which connecting portions 68 are provided in a lattice shape on the inner side from the outer frame 64. Two units 62 are arranged in one opening surrounded by the connecting portion 68. Again, a guide hole 66 is provided through the outer frame 64 of the lead frame 60 in the thickness direction.

  Referring to FIG. 9B, one lead 20E extends inward from the connecting portion 68 at the back, and the tip portion is a flat bonding portion. Furthermore, three leads 20C, 20B, and 20A extend inward from the connecting portion 68 on the front side. The tips of the two leads 20C and 20B are continuous with the second island 18. Further, the leading end portion of the lead 20 </ b> A is a bonding portion 26.

  Referring to FIGS. 8B and 9B, unit 52 and unit 62 are different in the shape of the island and the direction in which the leads protrude in the thickness direction. Further, in the unit 52 shown in FIG. 8B, the leads protrude in the direction in which the semiconductor elements are mounted (upward on the paper surface). On the other hand, in the unit 62 shown in FIG. 9B, the leads protrude in the direction opposite to the direction in which the semiconductor elements are mounted (upward on the paper surface). Further, the first island 16 and the second island 18 have a point-symmetric shape that becomes the same shape when rotated 180 degrees around a certain point.

  Next, the steps of die bonding and wire bonding will be described with reference to FIG. This figure is a perspective view showing the unit 52 of the lead frames 50 and 60 after both processes are completed.

  Referring to FIG. 10A, in the unit 52 of the lead frame 50, the first semiconductor element 12 is fixed to the upper surface of the first island 16, and the first semiconductor element 12 and the bonding portions 22, 24 are connected. It is connected via a thin metal wire. This process is performed collectively for all the units 52 included in the lead frame 50.

  Referring to FIG. 10B, the second semiconductor element 14 is mounted on the lower surface of the second island 18 of the lead frame 60. Furthermore, each electrode provided on the lower surface of the second semiconductor element 14 is connected to the lower surface of the bonding portion 26 or the bonding portion 28 via a thin metal wire (not shown). Actually, this step is performed with the lead frame 60 turned upside down (that is, with the surface on which the second semiconductor element 14 is mounted facing up).

  After the above process is completed, the lead frame 50 and the lead frame 60 are overlapped and integrated. As a result, each unit of the combined lead frame is configured as shown in FIG. Further, each unit of the lead frame is individually housed in a mold and a resin sealing process is performed. Specifically, in the resin sealing step, the semiconductor elements, islands, metal wires and leads of each unit are sealed with a sealing resin. Furthermore, a step of depositing a plating film on the surface of the lead exposed from the sealing resin, a step of individually separating each resin-sealed unit from the lead frame, a step of measuring the quality and electrical characteristics of each unit, Through the stamping process and the like, the semiconductor device 10B having the configuration shown in FIG. 1 is completed.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device of this invention, (A) is a perspective view, (B) and (C) are top views. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device of this invention, (A) and (B) are sectional drawings. FIG. 2 is a partially extracted view of the semiconductor device of the present invention, and (A) and (B) are perspective views. FIG. 2 is a partially extracted view of the semiconductor device of the present invention, and (A) and (B) are perspective views. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device of this invention, (A) and (B) are sectional drawings. BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device of this invention, (A) and (B) are sectional drawings. 1A and 1B are diagrams illustrating a semiconductor device of the present invention, in which FIG. 1A is a plan view, and FIG. It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a top view, (B) is a perspective view. It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a top view, (B) is a perspective view. It is a figure which shows the manufacturing method of the semiconductor device of this invention, (A) is a perspective view, (B) is a perspective view.

Explanation of symbols

10A, 10B, 10C, 10D Semiconductor device 12 First semiconductor element 14 Second semiconductor element 16 First island 18 Second island 20A, 20B, 20C, 20D, 20E, 20F, 20G, 20H Lead 22 Bonding portion 23 Sealing resin 24 Bonding part 26 Bonding part 28 Bonding part 30A, 30B, 30C, 30D Metal fine wire 31A, 31B, 31C Metal fine wire 32 Electrode 36 Electrode 40 Inclined part 42 Exposed part 50 Lead frame 52 Unit 54 Outer frame 56 Guide hole 58 Connecting part 60 Lead frame 62 Unit 64 Outer frame 66 Guide hole 68 Connection part A1, A2, A3, A4 Connection part

Claims (7)

A semiconductor device having a plurality of stacked semiconductor elements and leads that are electrically connected to the semiconductor elements and partially exposed to the outside;
A first island, a first semiconductor element fixed to the first island, and a first lead exposed to the outside continuously from the first island;
A second island, a second semiconductor element fixed to the second island, and a second lead exposed continuously from the second island,
A semiconductor device, wherein the first island, the first semiconductor element, the second island, and the second semiconductor element are arranged to overlap each other. The first island and the second island have a first main surface and a second main surface in the same direction;
The first semiconductor element is fixed to the first main surface of the first island;
The semiconductor device according to claim 1, wherein the second semiconductor element is fixed to the second main surface of the second island. The lead has a continuous exposed portion exposed to the outside, a connecting portion that is electrically connected to the semiconductor element and located on a different plane from the exposed portion, and the connecting portion and the exposed portion are continuous. Including
2. The semiconductor device according to claim 1, wherein a direction of a surface where the two semiconductor elements are fixed to the two islands is opposite to a direction in which the connecting portion protrudes. The lead has an exposed portion exposed to the outside, a connecting portion that is electrically connected to the semiconductor element and located on a different plane from the exposed portion, and a continuous portion that connects the connecting portion and the exposed portion. Including
2. The semiconductor device according to claim 1, wherein a direction of a surface where the two semiconductor elements are fixed to the two islands is the same as a direction in which the connecting portion protrudes. A third lead having the connection portion on the same plane as the first island and electrically connected to the first semiconductor element fixed to the first island via a connection means;
A fourth lead that has the connection portion on the same plane as the second island, and is electrically connected to the second semiconductor element fixed to the second island via a connection means; And
The semiconductor device according to claim 1, wherein the connection portion of the third lead partially overlaps the connection portion of the fourth lead. Covering both the semiconductor element and the both leads integrally, and having a sealing resin having an opposing flat surface on the outer surface,
The semiconductor device according to claim 1, wherein a main surface of the exposed portion of the lead is positioned on the same plane as the flat surface of the sealing resin.   The semiconductor device according to claim 1, wherein the second lead is led out in a direction opposite to a direction in which the first lead leads out.

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