JP2008300505A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of semiconductor device for controlling an increase in the amount of a cut of a semiconductor substrate even if the width of an offset spacer is changed during a manufacturing process. <P>SOLUTION: A nitride film 6 is formed covering an oxide film 5 on gate structures G1, G2 and the semiconductor substrate 1. Next, the nitride film 6 is anisotropically etched back using the oxide film 5 as an etching stopper. Next, an oxide film 7 having a higher selection ratio for the semiconductor substrate 1 and for the nitride film 6 is formed. The anisotropic etching-back is thereafter conducted to each oxide film 5, 7. Next, ion implantation is conducted to the semiconductor substrate 1 at the side of the one gate structure G2. By isotropic etching processing, the oxide films 7 formed on side surfaces of the gate structures G1, G2 are removed. Thereafter, ion implantation is conducted to the semiconductor substrate 1 at the side of the other gate structure G1. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including formation of an offset spacer and subsequent ion implantation processing for a semiconductor substrate.

  In general, the larger the lateral extension of the source / drain extension region, the smaller the effective channel length of the transistor, and the shorter the channel effect becomes. Therefore, it becomes difficult to form a fine transistor. In order to suppress the lateral expansion of the source / drain extension regions, ion implantation is performed with low energy. Alternatively, there is a method of reducing heat treatment. However, in the former case, there is a limit to the reduction in energy by the manufacturing apparatus. In the latter case, the activation rate decreases and the resistance of the source / drain extension region increases.

  Therefore, a technique using an offset spacer is employed. Employing this technique has the advantage that the effective channel length is increased by the amount of the offset spacer and the short channel effect is suppressed even when the same implantation energy and the same heat treatment are used. Further, by using this technique, when the ion implantation energy is increased, the source / drain extension regions are formed deeply. Therefore, the junction electric field at the end of the region is relaxed, and an effect that junction leakage current can be reduced is obtained.

  In general, the technique using the offset spacer employs the following process sequence in the manufacture of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). First, after etching for forming the gate structure, the oxide film is deposited. Next, a thin offset spacer is formed on the side surface of the gate structure by anisotropic etch back. Thereafter, ion implantation for forming source / drain extension regions is performed.

  For example, Patent Documents 1, 2, and 3 exist as conventional techniques related to offset spacers.

JP-A-3-259535 JP-A-8-330438 JP-A-9-237899

  In general, the profile at the time of ion implantation and the amount of diffusion due to heat treatment differ depending on the type of impurity. When transistors having different threshold voltages are operated with one type of power supply voltage, the allowable junction leakage current differs depending on the threshold voltage setting. Therefore, the optimum width of the offset spacer differs depending on the N-type / P-type of the transistor and the threshold voltage setting. Therefore, when making a plurality of types of transistors separately, it is necessary to change the width of the offset spacer formed in the gate structure during the manufacturing process.

  However, when the width of the offset spacer is changed during the manufacturing process, it is necessary to simply repeat oxide film deposition and anisotropic etch back. Therefore, scraping of the upper surface of the semiconductor substrate due to overetching is accumulated. Then, the performance of the transistor is deteriorated due to the accumulation of the semiconductor substrate shaving.

  Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can suppress an increase in the scraping of the upper surface of the semiconductor substrate even if the width of the offset spacer is changed during the manufacturing process.

  To achieve the above object, according to an embodiment of the present invention, a second insulating film is formed to cover the gate structure and the first insulating film on the semiconductor substrate. Next, using the first insulating film as an etching stopper, anisotropic etching back processing is performed on the second insulating film. Next, a third insulating film having a high selectivity with respect to the semiconductor substrate and a high selectivity with respect to the second insulating film is formed. Next, an anisotropic etch back process is performed on the third insulating film. Next, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate beside the second gate structure. Next, the third insulating film formed on the side surface portion of the gate structure is removed by an isotropic etching process. Thereafter, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate beside the first gate structure.

  According to the one embodiment, the semiconductor substrate can be prevented from being scraped during the anisotropic etch-back process of the second insulating film. In addition, the semiconductor substrate can be prevented from being scraped during the isotropic etching process for the third insulating film. That is, even if the width of the offset spacer formed on the side surface of the gate structure is changed during the manufacturing process, it is possible to suppress an increase in scraping of the upper surface of the semiconductor substrate.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
In the present embodiment, a case where NMOSFETs and PMOSFETs are separately formed on the semiconductor substrate 1 will be described. A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to process cross-sectional views.

  As shown in FIG. 1, an element isolation oxide film 2 is formed in a surface of a semiconductor substrate 1 such as a silicon substrate by a predetermined method. Next, an insulating film and an electrode film are deposited in this order on the upper surface of the semiconductor substrate 1. Thereafter, an etching process (patterning) is performed on the insulating film and the electrode film. Thereby, as shown in FIG. 1, two gate structures G1 and G2 are formed on the upper surface of the semiconductor substrate 1. Here, each of the gate structures G1 and G2 includes a stacked body of a gate insulating film (a part of the insulating film) 3 and a gate electrode (a part of the electrode film) 4.

  Next, the surface of the gate electrode 4 is oxidized or oxynitrided. At the same time, the upper surface of the semiconductor substrate 1 is also oxidized or oxynitrided. Thereby, as shown in FIG. 2, an oxide film (or an oxynitride film, which can be grasped as the first insulating film) 5 is formed so as to cover the upper surface of the semiconductor substrate 1 and the gate structures G1 and G2. Here, the oxynitride film 5 is a film having a higher composition ratio of oxygen than nitrogen. The film thickness of the oxide film 5 is about 2 to 5 nm from the viewpoint of the effect of oxidation on the gate electrode 4 and the etching stopper function in the anisotropic etch back process for the nitride film 6 described later. desirable.

  Next, as shown in FIG. 3, a nitride film (which can be grasped as a second insulating film) 6 is formed so as to cover the gate structures G <b> 1 and G <b> 2 and the oxide film 5 on the semiconductor substrate 1. Here, the thickness of the nitride film 6 is about 2 to 8 nm. The nitride film 6 has a high selectivity with respect to the oxide film 5.

  Next, an anisotropic etch back process is performed on the nitride film 6. At this time, the oxide film 5 functions as an etch stopper. By the anisotropic etch back process, as shown in FIG. 4, the nitride film 6 is left only on the side surfaces of the gate structures G1 and G2, and the nitride film 6 on the semiconductor substrate 1 is removed. That is, offset spacers made of the oxide film 5 and the nitride film 6 are formed on the side surfaces of the gate structures G1 and G2. As described above, the nitride film 6 is anisotropically etched using the oxide film 5 as an etch stopper. For this reason, shaving due to etching of the upper surface of the semiconductor substrate 1 is suppressed.

  Next, as shown in FIG. 5, an oxide film (which can be grasped as a third insulating film) 7 is formed so as to cover the gate structures G <b> 1 and G <b> 2 and the oxide film 5 on the semiconductor substrate 1. Here, the thickness of the oxide film 7 is about 2 to 8 nm. The oxide film 7 has a high selectivity with respect to the semiconductor substrate 1 and also has a high selectivity with respect to the nitride film 6.

  Next, anisotropic etch back processing is performed on the oxide films 5 and 7. Thus, as shown in FIG. 6, oxide films 5 and 7 and nitride film 6 are left on the side surfaces of gate structures G1 and G2. That is, an offset spacer made of a stack of the oxide films 5 and 7 and the nitride film 6 is formed on the side surfaces of the gate structures G1 and G2. As shown in FIG. 6, the upper surface of the semiconductor substrate 1 is exposed by the anisotropic etch-back process. That is, the oxide films 5 and 7 on the semiconductor substrate 1 are removed.

  Next, a resist mask 8 having an opening is formed on the semiconductor substrate 1. As shown in FIG. 7, the resist mask 8 covers the gate structure (first gate structure) G1, and from the opening of the resist mask 8, the gate structure (second gate structure) G2 and its peripheral part Is exposed. Then, as shown in FIG. 7, using the resist mask 8 as a mask, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate 1 beside the gate structure G2.

Here, when the ion implantation is an ion implantation process for forming a P-type transistor (PMOSFET), the ion implantation can be grasped as extension implantation. The extension implantation is performed, for example, under the conditions of ionic species BF ₂ , energy 2 keV, and concentration 5 × 10 ¹⁴ / cm ² . By the extension implantation, an extension region 9 is formed in the surface of the semiconductor substrate 1 beside the gate structure G2, as shown in FIG.

In addition, when the ion implantation is an ion implantation process for forming a P-type transistor (PMOSFET), the ion implantation can be performed in two stages of the extension implantation and the halo implantation. After the extension implantation, the halo implantation is performed on the semiconductor substrate 1 beside the gate structure G2, using the resist mask 8 as a mask, as shown in FIG. The halo implantation is performed by oblique rotation implantation, for example, under the conditions of an ion species As, an energy of 50 keV, and a concentration of 5 × 10 ¹³ / cm ² . By the halo implantation, a halo region 10 is formed around the extension region 9 as shown in FIG.

  Next, the resist mask 8 is removed. Thereafter, a wet etching process (isotropic etching process) using HF is performed. As a result, the oxide film 7 formed on the side surfaces of the gate structures G1 and G2 is removed. Therefore, after the isotropic etching process, offset spacers made of the oxide film 5 and the nitride film 6 remain on the side surfaces of the gate structures G1 and G2, as shown in FIG.

  Here, the oxide film 7 has a high selectivity with respect to the semiconductor substrate 1 and a high selectivity with respect to the nitride film 6. Therefore, even if the etching process is performed on the oxide film 7, it is possible to prevent the upper surface of the semiconductor substrate 1 made of a silicon substrate from being scraped. Further, the nitride film 6 formed on the side surfaces of the gate structures G1 and G2 can be prevented from being scraped.

  Next, a resist mask 18 having an opening is formed on the semiconductor substrate 1. As shown in FIG. 10, the resist mask 18 covers the gate structure G <b> 2, and the gate structure G <b> 1 and its peripheral part are exposed from the opening of the resist mask 18. Then, as shown in FIG. 10, using the resist mask 18 as a mask, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate 1 beside the gate structure G1.

Here, when the ion implantation is an ion implantation step for forming an N-type transistor (NMOSFET), the ion implantation can be grasped as extension implantation. The extension implantation is performed, for example, under the conditions of ionic species As, energy 2 keV, and concentration 8 × 10 ¹⁴ / cm ² . As a result of the extension implantation, an extension region 11 is formed in the surface of the semiconductor substrate 1 beside the gate structure G1, as shown in FIG.

Further, when the ion implantation is an ion implantation step for forming an N-type transistor (NMOSFET), the ion implantation can be performed in two stages of the extension implantation and the halo implantation. After the extension implantation, the halo implantation is performed on the semiconductor substrate 1 beside the gate structure G1, using the resist mask 18 as a mask, as shown in FIG. The halo implantation is performed, for example, by oblique rotation implantation under the conditions of ion species B, energy of 8 keV, and concentration of 5 × 10 ¹³ / cm ² . As a result of the halo implantation, a halo region 12 is formed around the extension region 11 as shown in FIG.

  Next, as shown in FIG. 12, an oxide film 13 and a nitride film 14 are deposited in this order so as to cover the gate structures G1 and G2 and the surface of the semiconductor substrate 1. Thereafter, anisotropic etch back is performed on the oxide film 13 and the nitride film 14. Thereby, as shown in FIG. 13, the oxide film 13 and the nitride film 14 can be left only on the side surfaces of the gate structures G1 and G2. As a result, sidewalls made of the oxide film 5, the nitride film 6, the oxide film 13, and the nitride film 14 are formed on the side surfaces of the gate structures G1 and G2.

  Next, a resist mask 28 having an opening is formed on the semiconductor substrate 1. As shown in FIG. 14, the resist mask 28 covers the gate structure G <b> 1, and the gate structure G <b> 2 and its peripheral part are exposed from the opening of the resist mask 28. Then, as shown in FIG. 14, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate 1 beside the gate structure G1, using the resist mask 28 as a mask.

Here, when the ion implantation is an ion implantation step for forming a P-type transistor (PMOSFET), the ion implantation can be grasped as source / drain implantation. The source / drain implantation is performed, for example, under the conditions of ion species B, energy 2 keV, and concentration 5 × 10 ¹⁵ / cm ² . By the source / drain implantation, source / drain regions 15 are formed in the surface of the semiconductor substrate 1 beside the gate structure G2, as shown in FIG.

  Next, the resist mask 28 is removed. Thereafter, a resist mask 38 having an opening is formed on the semiconductor substrate 1. As shown in FIG. 15, the resist mask 38 covers the gate structure G <b> 2, and the gate structure G <b> 1 and its peripheral part are exposed from the opening of the resist mask 38. Then, as shown in FIG. 15, using the resist mask 38 as a mask, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate 1 beside the gate structure G1.

Here, when the ion implantation is an ion implantation step for forming an N-type transistor (NMOSFET), the ion implantation can be grasped as source / drain implantation. The source / drain implantation is performed, for example, under the conditions of an ion species As, an energy of 10 keV, and a concentration of 5 × 10 ¹⁵ / cm ² . By the source / drain implantation, source / drain regions 16 are formed in the surface of the semiconductor substrate 1 beside the gate structure G1 as shown in FIG.

  Thereafter, the resist mask 38 is removed, and the semiconductor substrate 1 is subjected to a high-temperature heat treatment. As a result, the impurities implanted in each of the implantation processes are electrically activated. The heat treatment is performed by spike RTA (Rapid Thermal Anneal), laser annealing, flash lamp annealing, or a combination thereof.

  Through the above steps, the PMOS transistor P1 and the NMOS transistor N1 are formed on the semiconductor substrate 1 as shown in FIG. Further, an integrated circuit is completed through a contact / wiring process.

  Here, the structure as shown in FIG. 17 is formed by forming the transistors P1 and N1 on the semiconductor substrate 1 through the manufacturing method described above. FIG. 17 is an enlarged cross-sectional view of the circled portion of FIG.

  When the etching (patterning) for forming the gate structures G1 and G2 shown in FIG. 1 is performed, the top surface of the semiconductor substrate 1 is slightly shaved, thereby forming a step s1 as shown in FIG. In addition, when the anisotropic etching process is performed on the oxide films 5 and 7 shown in FIG. 6, the upper surface of the semiconductor substrate 1 is slightly shaved, so that a step s2 is formed as shown in FIG. Here, in FIG. 17, the dimension l1 from the end of the nitride film 6 to the step s2 is about 4 to 10 nm. The height h1 of the step s2 is about 2 to 3 nm. Each of the dimensions is attributed to the fact that the oxide film 7 has an etching selectivity when the oxide film 7 is removed, but the nitride film 6 and the semiconductor substrate 1 are scraped by about 2 nm.

  As described above, by performing the above-described series of steps, the oxide film 5 functions as an etching stopper when the nitride film 6 is anisotropically etched. Further, the oxide film 7 having an etching selectivity with respect to the semiconductor substrate 1 is removed by isotropic etching.

  Therefore, even if the width of the offset spacer is changed during the manufacturing process in order to form a plurality of types of transistors, it is possible to suppress an increase in chipping in the semiconductor substrate 1.

  The composition of the semiconductor substrate 1, the first insulating film 5, the second insulating film 6, and the third insulating film 7 can be arbitrarily selected as long as the following conditions are satisfied. That is, the first insulating film 5 functions as an etching stopper when the second insulating film 6 is anisotropically etched. The third insulating film 7 has a high etching selectivity with respect to the semiconductor substrate 1 and a high etching selectivity with respect to the second insulating film 6. If the said conditions are satisfy | filled, each member 1, 5-7 may be compositions other than a silicon | silicone, an oxide film, and a nitride film. In this specification, “A” has a higher etching selectivity than “B” means that “A” is more easily removed by etching than “B” under the same etching conditions.

  However, from the viewpoint of easy manufacture and practicality, the semiconductor substrate 1 is a silicon substrate, the first insulating film 5 and the third insulating film 7 are oxide films, and the second insulating film 6 is a nitride film. It is desirable.

  In general, when As or the like, which is an extension impurity of NMOSFET, is compared with B or the like, which is an extension impurity of PMOSFET, the spread and thermal diffusion during ion implantation are larger and more remarkable.

  Therefore, when the PMOS transistor P1 and the NMOS transistor N1 are formed on the semiconductor substrate 1, it is beneficial to employ the above series of steps. That is, the ion implantation shown in FIGS. 7 and 8 is an ion implantation for forming a P-type transistor. On the other hand, the ion implantation shown in FIGS. 10 and 11 is an ion implantation for forming an N-type transistor. Thereby, the offset spacer width for forming the PMOS transistor P1 can be set wider than the offset spacer for forming the NMOS transistor N1. Therefore, the short channel characteristics of the PMOS transistor P1 and the NMOS transistor N1 can be optimized independently, and the characteristics of the transistors P1 and N1 are improved.

<Embodiment 2>
In this embodiment, reference is made to another aspect of the method for forming the insulating film (first insulating film) formed on the semiconductor substrate 1 in FIG.

  First, as in the first embodiment, the element isolation oxide film 2 is formed in the surface of the semiconductor substrate 1 by a predetermined method. Next, as shown in FIG. 18, an insulating film (for example, an oxide film) 23 and an electrode film 24 are deposited in this order on the upper surface of the semiconductor substrate 1.

  Thereafter, an etching process (patterning) is performed on the insulating film 23 and the electrode film 24 to form two gate structures. Here, in the etching process, an insulating film having a predetermined thickness is left on the semiconductor substrate 1. Accordingly, as shown in FIG. 19, two gate structures G1 and G2 are formed on the semiconductor substrate 1 by the etching process, and the insulating film 5 (on the upper surface of the semiconductor substrate 1 is formed on the upper surface of the semiconductor substrate 1). An etching residual film of the insulating film 23) is formed.

  The insulating film 5 functions as an etching stopper in the anisotropic etch back process for the nitride film 6 described in the first embodiment. From the viewpoint of the etching stopper, the film thickness of the insulating film 5 formed (remaining) on the upper surface of the semiconductor substrate 1 is desirably 2 nm or more.

  The subsequent steps are the same as those in FIG. 3 and subsequent steps described in the first embodiment. However, as is clear from the above description, in this embodiment, the insulating film 5 is not formed on the side surfaces of the gate structures G1 and G2. That is, the steps of FIGS. 3 to 16 are common to the present embodiment except for the presence or absence of the insulating film 5 on the side surfaces of the gate structures G1 and G2. In the finished product according to the present embodiment, sidewalls made of nitride film 6, oxide film 13, and nitride film 14 are formed on the side surfaces of gate structures G1 and G2.

  As in the first embodiment, the patterning of the gate structures G1 and G2 and the formation of the oxide film (first insulating film) 5 may be performed in separate steps. Thereby, management of a manufacturing process (manufacturing conditions) becomes easy.

  On the other hand, in this embodiment, patterning of the gate structures G1 and G2 and formation of the insulating film 5 are performed simultaneously. Therefore, the process of FIG. 2 described in Embodiment 1 can be omitted, and the manufacturing process can be simplified.

<Embodiment 3>
In the first embodiment, the case where the NMOSFET and the PMOSFET are separately formed on the semiconductor substrate 1 has been described. In the present embodiment, a case where two NMOSFETs having different threshold voltages are separately formed on the semiconductor substrate 1 will be described. Here, the series of steps described with reference to FIGS. 1 to 16 is common to the present embodiment except for the following points.

  That is, in the first embodiment, the ion implantation process shown in FIGS. 7 and 8 is a process for forming a PMOSFET, and the ion implantation process shown in FIGS. 10 and 11 is a process for forming an NMOSFET. .

  On the other hand, in this embodiment, the ion implantation steps shown in FIGS. 7, 8, 10 and 11 are all steps for forming the NMOSFET. Specifically, in this embodiment, the ion implantation process shown in FIGS. 7 and 8 is a process for forming an N-type transistor having a first threshold voltage. On the other hand, in this embodiment, the ion implantation process shown in FIGS. 10 and 11 is a process for forming an N-type transistor having a second threshold voltage. Here, the second threshold voltage is smaller than the first threshold voltage.

  More specifically, in the steps of FIGS. 7 and 8, a resist mask 8 having an opening is formed on the semiconductor substrate 1. As shown in FIGS. 7 and 8, the resist mask 8 covers the gate structure G1, and the gate structure G2 and its peripheral part are exposed from the opening of the resist mask 8. 7 and 8, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate 1 beside the gate structure G2 using the resist mask 8 as a mask.

  Here, as the ion implantation, the following extension implantation and halo implantation are performed in order to form the NMOSFET having the first threshold voltage.

Extension implantation is performed, for example, under the conditions of ion species P, energy of 0.7 keV, and concentration of 4 × 10 ¹⁴ / cm ² . By the extension implantation, as shown in FIG. 7, a first extension region 9 is formed in the surface of the semiconductor substrate 1 beside the gate structure G2.

Further, the halo implantation after the extension implantation is performed on the semiconductor substrate 1 beside the gate structure G2 using the resist mask 8 as a mask, as shown in FIG. The halo implantation is performed, for example, by oblique rotation implantation under the conditions of ion species B, energy of 8 keV, and concentration of 5 × 10 ¹³ / cm ² . As a result of the halo implantation, a first halo region 10 is formed around the first extension region 9 as shown in FIG.

  On the other hand, in the steps of FIGS. 10 and 11, a resist mask 18 having an opening is formed on the semiconductor substrate 1. As shown in FIGS. 10 and 11, the resist mask 18 covers the gate structure G <b> 2, and the gate structure G <b> 1 and its peripheral portion are exposed from the opening of the resist mask 18. Then, as shown in FIGS. 10 and 11, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate 1 beside the gate structure G1 using the resist mask 18 as a mask.

  Here, as the ion implantation, the following extension implantation and halo implantation are performed in order to form the NMOSFET having the second threshold voltage.

The extension implantation is performed, for example, under the conditions of ion species As, energy 2 keV, and concentration 8 × 10 ¹⁴ / cm ² . By the extension implantation, as shown in FIG. 10, the second extension region 11 is formed in the surface of the semiconductor substrate 1 beside the gate structure G1.

Further, the halo implantation after the extension implantation is performed on the semiconductor substrate 1 beside the gate structure G1, using the resist mask 18 as a mask, as shown in FIG. The halo implantation is performed by, for example, oblique rotation implantation under the conditions of ion species In, energy 50 keV, and concentration 3 × 10 ¹³ / cm ² . Alternatively, in addition to the In ion implantation, oblique rotation implantation may be performed under the conditions of ion species B, energy of 8 keV, and concentration of 2 × 10 ¹³ / cm ² . By the halo implantation, a second halo region 12 is formed around the second extension region 11 as shown in FIG.

  By the way, it is assumed that the resistance between the source and drain when the transistor is on is divided into the parasitic resistance of the extension and the channel resistance. In this case, in general, a transistor having a higher threshold voltage has a high channel resistance, so that the contribution of the parasitic resistance of the extension is reduced. On the other hand, since the channel resistance is low in the transistor on the lower threshold voltage side, the contribution of the parasitic resistance of the extension is large. In general, a transistor having a higher threshold voltage has a low channel leakage, and therefore, it is necessary to keep the junction leakage current low. On the other hand, since the channel leakage is high in the transistor having the lower threshold voltage, the junction leakage current may be increased accordingly.

  The junction leakage current increases as the junction at the extension end becomes steeper. Therefore, in order to reduce the junction leakage current, it is necessary to increase the extension depth and reduce the concentration. However, in this case, degradation of on-current due to degradation of short channel characteristics and increase of parasitic resistance occurs.

  Therefore, when forming NMOS transistors having different threshold voltages on the semiconductor substrate 1, it is beneficial to employ the series of steps of the present invention. That is, the ion implantation shown in FIGS. 7 and 8 is the ion implantation for forming the N-type transistor having the first threshold voltage. On the other hand, the ion implantation shown in FIGS. 10 and 11 is ion implantation for forming an N-type transistor having a second threshold voltage lower than the first threshold voltage.

  Accordingly, the offset spacer width for forming the NMOS transistor having the first threshold voltage can be set wider than the offset spacer for forming the NMOS transistor having the second threshold voltage. Therefore, it is possible to alleviate the junction electric field while avoiding the deterioration of the short channel characteristics caused by increasing the extension depth. In addition, in the NMOS transistor having the first threshold voltage, the on-current reduction effect due to the extension resistance increase is small. Therefore, the junction electric field can be reduced by reducing the extension concentration.

  Further, in order to form the first extension region 9 of the NMOS transistor having the first threshold voltage, phosphorus ions are implanted in the step shown in FIG. On the other hand, in order to form the second extension region 11 of the NMOS transistor having the second threshold voltage, arsenic ions are implanted in the step shown in FIG.

  Thereby, phosphorus ions have a larger implantation distribution and thermal diffusion than arsenic ions, so that the leakage current can be suppressed smaller in the NMOS transistor having the first threshold voltage. On the other hand, in the NMOS transistor having the second threshold voltage, the leakage current can be set larger than in the former case. That is, the ion species are most appropriate from the viewpoint of setting the leakage current.

  In order to form the first halo region 10 of the NMOS transistor having the first threshold voltage, boron ions are implanted in the step shown in FIG. On the other hand, in order to form the second halo region 12 of the NMOS transistor having the second threshold voltage, in the process shown in FIG. 11, indium ions are implanted.

  As a result, boron ions have a wider implantation distribution and thermal diffusion than indium ions. Therefore, even when the halo regions 10 and 12 are formed, the leakage current can be further reduced in the NMOS transistor having the first threshold voltage. On the other hand, in the NMOS transistor having the second threshold voltage, the leakage current can be set larger than in the former case. That is, when the halo regions 10 and 12 are formed, the ionic species are most appropriate from the viewpoint of setting the leakage current.

  In the present embodiment, it is needless to say that the method for forming the insulating film 5 of the second embodiment may be employed instead of the process of FIG.

<Embodiment 4>
In the first embodiment, the case where the NMOSFET and the PMOSFET are separately formed on the semiconductor substrate 1 has been described. In the present embodiment, a case where two PMOSFETs having different threshold voltages are separately formed on the semiconductor substrate 1 will be described. Here, the series of steps described with reference to FIGS. 1 to 16 is common to the present embodiment except for the following points.

  That is, in the first embodiment, the ion implantation process shown in FIGS. 7 and 8 is a process for forming a PMOSFET, and the ion implantation process shown in FIGS. 10 and 11 is a process for forming an NMOSFET. .

  In contrast, in the present embodiment, the ion implantation steps shown in FIGS. 7, 8, 10 and 11 are all steps for forming the PMOSFET. Specifically, in this embodiment, the ion implantation process shown in FIGS. 7 and 8 is a process for forming a P-type transistor having a first threshold voltage. On the other hand, in this embodiment, the ion implantation process shown in FIGS. 10 and 11 is a process for forming a P-type transistor having a second threshold voltage. Here, the second threshold voltage is smaller than the first threshold voltage.

  More specifically, in the steps of FIGS. 7 and 8, a resist mask 8 having an opening is formed on the semiconductor substrate 1. As shown in FIGS. 7 and 8, the resist mask 8 covers the gate structure G <b> 1, and the gate structure G <b> 2 and its peripheral part are exposed from the opening of the resist mask 8. 7 and 8, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate 1 beside the gate structure G2 using the resist mask 8 as a mask.

  Here, as the ion implantation, the following extension implantation and halo implantation are performed in order to form the PMOSFET having the first threshold voltage.

The extension implantation is performed, for example, under the conditions of ion species B, energy of 0.4 keV, and concentration of 3 × 10 ¹⁴ / cm ² . By the extension implantation, as shown in FIG. 7, a first extension region 9 is formed in the surface of the semiconductor substrate 1 beside the gate structure G2.

Further, the halo implantation after the extension implantation is performed on the semiconductor substrate 1 beside the gate structure G2 using the resist mask 8 as a mask, as shown in FIG. The halo implantation is performed, for example, by oblique rotation implantation under the conditions of ion species P, energy 25 keV, and concentration 5 × 10 ¹³ / cm ² . As a result of the halo implantation, a first halo region 10 is formed around the first extension region 9 as shown in FIG.

  On the other hand, in the steps of FIGS. 10 and 11, a resist mask 18 having an opening is formed on the semiconductor substrate 1. As shown in FIGS. 10 and 11, the resist mask 18 covers the gate structure G <b> 2, and the gate structure G <b> 1 and its peripheral portion are exposed from the opening of the resist mask 18. Then, as shown in FIGS. 10 and 11, ion implantation of a predetermined conductivity type is performed on the semiconductor substrate 1 beside the gate structure G1 using the resist mask 18 as a mask.

  Here, as the ion implantation, the following extension implantation and halo implantation are performed in order to form a PMOSFET having the second threshold voltage.

The extension implantation is performed, for example, under the conditions of ion species BF ₂ , energy 2 keV, and concentration 5 × 10 ¹⁴ / cm ² . By the extension implantation, as shown in FIG. 10, the second extension region 11 is formed in the surface of the semiconductor substrate 1 beside the gate structure G1.

Further, the halo implantation after the extension implantation is performed on the semiconductor substrate 1 beside the gate structure G1, using the resist mask 18 as a mask, as shown in FIG. The halo implantation is performed by oblique rotation implantation, for example, under the conditions of an ion species As, an energy of 50 keV, and a concentration of 5 × 10 ¹³ / cm ² . Alternatively, in addition to the As ion implantation, P ions may be obliquely implanted. By the halo implantation, a second halo region 12 is formed around the second extension region 11 as shown in FIG.

  By adopting this embodiment when forming PMOS transistors having different threshold voltages, the same effects as those mentioned in Embodiment 3 can be obtained.

  That is, the ion implantation shown in FIGS. 7 and 8 is the ion implantation for forming the P-type transistor having the first threshold voltage. On the other hand, the ion implantation shown in FIGS. 10 and 11 is ion implantation for forming a P-type transistor having the second threshold voltage.

  Thereby, the offset spacer width for forming the PMOS transistor having the first threshold voltage can be set wider than the offset spacer for forming the PMOS transistor having the second threshold voltage. Therefore, it is possible to alleviate the junction electric field while avoiding the deterioration of the short channel characteristics caused by increasing the extension depth. In addition, the PMOS transistor having the first threshold voltage has a small effect of reducing the on-current due to the extension resistance increase. Therefore, the junction electric field can be reduced by reducing the extension concentration.

In addition, in order to form the first extension region 9 of the PMOS transistor having the first threshold voltage, boron ions are implanted in the step shown in FIG. On the other hand, in order to form the second extension region 11 of the PMOS transistor having the second threshold voltage, BF ₂ ions are implanted in the step shown in FIG.

As a result, boron ions have a larger distribution of implantation and thermal diffusion than BF ₂ ions, so that the leakage current can be suppressed smaller in the PMOS transistor having the first threshold voltage. On the other hand, in the PMOS transistor having the second threshold voltage, the leakage current can be set larger than in the former case. That is, the ion species are most appropriate from the viewpoint of setting the leakage current.

  In order to form the first halo region 10 of the PMOS transistor having the first threshold voltage, phosphorus ions are implanted in the step shown in FIG. On the other hand, in order to form the second halo region 12 of the PMOS transistor having the second threshold voltage, arsenic ions are implanted in the step shown in FIG.

  As a result, phosphorus ions have a wider implantation distribution and thermal diffusion than arsenic ions. Therefore, even when the halo regions 10 and 12 are formed, the leakage current can be further reduced in the PMOS transistor having the first threshold voltage. On the other hand, in the PMOS transistor having the second threshold voltage, the leakage current can be set larger than in the former case. That is, when the halo regions 10 and 12 are formed, the ionic species are most appropriate from the viewpoint of setting the leakage current.

  In the present embodiment, it is needless to say that the method for forming the insulating film 5 of the second embodiment may be employed instead of the process of FIG.

  In the above, after the ion implantation shown in FIGS. 7 and 8 and the ion implantation shown in FIGS. 10 and 11 are completed, the semiconductor substrate 1 may be subjected to heat treatment (first case). On the other hand, after the first heat treatment is performed on the semiconductor substrate 1 after the ion implantation shown in FIGS. 7 and 8, the ion implantation shown in FIGS. 10 and 11 is performed, and then the second heat treatment is performed on the semiconductor substrate 1. Is also good (second case).

  In the first case, the manufacturing process can be simplified. On the other hand, in the second case, when a plurality of transistors are formed on the semiconductor substrate 1, the performance of each transistor can be optimized. For example, in the second case, the following effects are achieved.

  First, a case where the PMOS transistor P1 and the NMOS transistor N1 are formed on the semiconductor substrate 1 will be described. Here, as described in the first embodiment, the ion implantation shown in FIGS. 7 and 8 is a process for forming the PMOS transistor P1. On the other hand, the ion implantation shown in FIGS. 10 and 11 is a process for forming the NMOS transistor N1.

  In this case, by implementing the second case, it is possible to suppress the diffusion of the impurities implanted in FIGS. 7 and 8 in the semiconductor substrate 1 more than when the first case is implemented. This coincides with the desire to suppress the expansion of the diffusion regions 9 and 10 of the PMOS transistor P1 more than the expansion of the diffusion regions 11 and 12 of the NMOS transistor N1.

  Further, a case where NMOS (or PMOS) transistors having different threshold voltages are formed on the semiconductor substrate 1 will be described. Here, as described in the third and fourth embodiments, the ion implantation shown in FIGS. 7 and 8 is a process for forming a transistor having the first threshold voltage (high threshold voltage). On the other hand, the ion implantation shown in FIGS. 10 and 11 is a process for forming a transistor having a second threshold voltage (low threshold voltage).

  In this case, by implementing the second case, on the transistor side having the first threshold voltage, the junction steepness can be reduced by impurity thermal diffusion and the junction leakage current can be reduced by recovering the implantation defects. This is consistent with the desire to reduce the leakage current in the transistor having the first threshold voltage more than the leakage current in the transistor having the second threshold voltage.

  Further, after the ion implantation shown in FIGS. 7 and 8, the first heat treatment and the second heat treatment may be continuously performed in two stages. Similarly, after the ion implantation shown in FIGS. 10 and 11, the first heat treatment and the second heat treatment may be continuously performed in two stages. In this case, after laser annealing or flash lamp annealing (first heat treatment) with a high activation rate (in other words, higher temperature and shorter time), the lower temperature and longer than the conditions of the first heat treatment are performed. It is desirable to perform a time spike RTA (second heat treatment).

  This makes it possible to control the diffusion of impurities while maintaining a high activation rate as compared with the case where laser annealing or flash lamp annealing (first heat treatment) is performed after spike RTA (second heat treatment). . That is, low resistance diffusion regions 9 to 12 can be formed. Here, the low resistance effect in the extension regions 9 and 11 is higher than the low resistance effect in the halo regions 10 and 12.

FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. FIG. 10 is a process cross-sectional view for illustrating the method of manufacturing the semiconductor device according to the first embodiment. 3 is an enlarged cross-sectional view of a transistor created by the method for manufacturing a semiconductor device according to the first embodiment. FIG. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 10 is a process cross-sectional view for illustrating the method for manufacturing the semiconductor device according to the second embodiment.

Explanation of symbols

  1 semiconductor substrate, 2 element isolation oxide film, 3 gate insulating film, 4 gate electrode, 5 first insulating film (first oxide film or oxide film), 6 second insulating film (nitride film), 7 third Insulating film (second oxide film or oxide film), 8, 18, 28 resist mask, 9 first extension region, 10 first halo region, 11 second extension region, 12 second halo region, 13 oxide film, 14 nitride film, 15, 16 source / drain region, 23 insulating film, 24 electrode film, G1, G2 gate structure, P1 PMOS transistor, N1 NMOS transistor, s1, s2 step.

Claims (14)

(A) forming a first gate structure and a second gate structure comprising a stacked body of a gate insulating film and a gate electrode on a semiconductor substrate;
(B) forming a first insulating film on at least the upper surface of the semiconductor substrate;
(C) forming a second insulating film so as to cover the gate structure and the first insulating film on the semiconductor substrate;
(D) Using the first insulating film as an etching stopper, the second insulating film is left on the side surface of the gate structure by subjecting the second insulating film to anisotropic etching back. And removing the second insulating film on the semiconductor substrate;
(E) after the step (D), forming a third insulating film having a high selectivity to the semiconductor substrate so as to cover the gate structure and the first insulating film on the semiconductor substrate; ,
(F) An anisotropic etch-back process is performed on the third insulating film to leave the third insulating film on the side surface of the gate structure, and the third insulating film on the semiconductor substrate. Removing the insulating film;
(G) After the step (F), using a mask that covers the first gate structure and exposes the second gate structure and its periphery, the side of the second gate structure A step of performing ion implantation of a predetermined conductivity type on a semiconductor substrate;
(H) After the step (G), a step of removing the third insulating film formed on the side surface portion of the gate structure by an isotropic etching process;
(I) After the step (H), the mask on the side of the first gate structure is covered with a mask having an opening that covers the second gate structure and exposes the first gate structure and its periphery. A step of performing ion implantation of a predetermined conductivity type on the semiconductor substrate,
A method for manufacturing a semiconductor device. The third insulating film is
High selectivity to the second insulating film,
The method of manufacturing a semiconductor device according to claim 1. The semiconductor substrate is a silicon substrate;
The first insulating film and the third insulating film are oxide films,
The second insulating film is a nitride film,
The method of manufacturing a semiconductor device according to claim 1. The step (B)
Forming the first insulating film so as to cover the gate structure and the upper surface of the semiconductor substrate;
The method of manufacturing a semiconductor device according to claim 1. The step (A) and the step (B)
After depositing an insulating film and an electrode film on the semiconductor substrate in this order, the insulating film and the electrode film are etched so that the insulating film having a predetermined thickness remains on the semiconductor substrate. This is a step of forming the gate structure and the first insulating film.
The method of manufacturing a semiconductor device according to claim 1. The step (G)
An ion implantation process for forming a P-type transistor,
The step (I) includes
An ion implantation process for forming an N-type transistor;
The method of manufacturing a semiconductor device according to claim 1. The step (G)
An ion implantation step for forming an N-type transistor having a first threshold voltage;
The step (I) includes
An ion implantation step for forming an N-type transistor having a second threshold voltage lower than the first threshold voltage;
The method of manufacturing a semiconductor device according to claim 1. The step (G)
(G-1) including a step of implanting phosphorus ions to form a first extension region;
The step (I) includes
(I-1) includes a step of implanting arsenic ions to form a second extension region.
The method of manufacturing a semiconductor device according to claim 7. The step (G)
(G-2) After the step (G-1), further includes a step of implanting boron ions to form a first halo region,
The step (I) includes
(I-2) The method further includes a step of injecting indium ions after the step (I-1) to form a second halo region.
The method for manufacturing a semiconductor device according to claim 8. The step (G)
An ion implantation step for forming a P-type transistor having a first threshold voltage;
The step (I) includes
An ion implantation step for forming a P-type transistor having a second threshold voltage lower than the first threshold voltage;
The method of manufacturing a semiconductor device according to claim 1. The step (G)
(G-1) including a step of implanting boron ions to form a first extension region;
The step (I) includes
(I-1) includes a step of implanting BF ₂ ions to form a second extension region.
The method of manufacturing a semiconductor device according to claim 10. The step (G)
(G-2) After the step (G-1), the method further includes a step of implanting phosphorus ions to form a first halo region.
The step (I) includes
(I-2) The method further includes a step of implanting arsenic ions to form a second halo region after the step (I-1).
The method of manufacturing a semiconductor device according to claim 11. (J) after the step (G) and before the step (I), subjecting the semiconductor substrate to a first heat treatment;
(K) after the step (I), further comprising a step of performing a second heat treatment on the semiconductor substrate,
The method of manufacturing a semiconductor device according to claim 1. (L) After the step (G) and / or after the step (I), the semiconductor substrate is subjected to a first heat treatment and a second heat treatment after the first heat treatment. A process,
The heating condition of the first heat treatment is as follows:
Higher temperature and shorter time than the second heat treatment,
The method of manufacturing a semiconductor device according to claim 1.

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