JP2008298701A - Test board and testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test board and a testing method which enables high-speed testing, using simple configuration. <P>SOLUTION: The test board is provided with a socket for mounting a non-test device, and first and second signal lines connected between an output terminal, an input terminal of the non-test device and a switch, respectively. First and second resistance elements in which impedance is smaller than the first signal line and the second signal line are provided, between the first signal line and the switch and between the second signal line and the switch respectively. A third signal line for connecting the resistance element and a tester via the switch and a fourth signal line for connecting the second resistance element and the tester are provided. The switch is connected between the first and second resistance elements, and the first resistance element and the third signal line are connected, at a direct current and a low-speed test or timing calibration. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a test board and a test method, and more particularly to a technique that is effective when used for a loopback test.

Japanese Patent Laid-Open No. 2003-028928 discloses a method (loop) for connecting an output terminal and an input terminal of an LSI, which is a device under test, on a test board and performing an operation test of an I / O interface at an actual operation speed.
JP 2003-028928 A

  The problem is how to stably mass-produce an LSI (large scale integrated circuit) having a performance of 200 Mbps to 667 Mbps with an existing tester (for example, performance of 166 Mbps; 333 MHz). Further, since LSI has a large jitter, it is difficult to perform stable mass production with an existing tester that has no idea of source synchronous. Therefore, it is necessary to devise the tester side (test board) at the same time as adding a high-speed interface test function to the LSI. The problem at that time is to make the waveform quality of the signal to be looped back compatible with the conventional test. The applicant of the present application examined a test board as shown in FIG. 8 in order to realize the loopback test. However, as shown in FIG. 9 obtained by computer simulation without considering impedance matching on the test board for loop bag test, the waveform quality is poor as shown in FIG. 9, which leads to a delay in development schedule and a decrease in mass production yield. In addition, since two transfer relays SW1 and W2 are used to form one loop bag, for example, an output circuit that outputs data in units of 64 bits and data input in units of 64 bits. An LSI with an input circuit requires a large number of 64 × 2 = 128 transfer relays, which increases the number of components mounted on the test board (on the board), making it unsuitable for parallel interface testing. Have.

  An object of the present invention is to provide a test substrate and a test method that enable a high-speed test with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. The test board has a socket for mounting the non-test device, a first signal line connecting the output terminal of the non-test device and the switch, and a connection between the input terminal of the non-test device and the switch. A second signal line is provided. First and second resistance elements having impedances smaller than those of the first signal line and the second signal line between the first signal line and the switch and between the second signal line and the switch. Is provided. A third signal line for connecting the first or second resistance element and the tester via the switch and a fourth signal line for connecting the second or first resistance element and the tester are provided. The switch connects between the first resistor and the second resistor during a loop test, and the first or second resistor and the third signal line during a direct current, low speed test, or timing calibration. To be connected with.

  Another embodiment disclosed in the present application is as follows. A first signal line for connecting the output terminal of the non-test device and the switch and a second signal line for connecting the input terminal of the non-test device and the switch are provided on the test board. Between the first signal line and the switch, a first resistance element having an impedance smaller than that of the first signal line, and between the second signal line and the switch, the second signal is provided. And a second resistance element having an impedance smaller than that of the line. A third signal line for connecting the first or second resistance element and the tester via the switch and a fourth signal line for connecting the second or first resistance element and the tester are provided. The tester is connected via the third and fourth signal lines. The non-test device is mounted on the test board, and a test pattern is input from the tester to the non-test device. The switch connects the first resistance element and the second resistance element, terminates the tester side of the fourth signal line with a termination resistor, and inputs an output signal from the output terminal to the input terminal. Perform a loop test.

  Can be configured with one switch corresponding to one set of output terminal and input terminal, and the signal line connected to the tester side and the terminating resistance on the tester side let the signal reflected in the loop test escape to the tester and improve the waveform quality Enables high-speed testing.

  FIG. 1 is a block diagram showing one embodiment for explaining a test board and a test method according to the present invention. A device to be tested is mounted on the test board. This device is mounted on a socket and electrically connected to wiring provided on a test board. In the test board of the figure, a signal path corresponding to one output terminal and one input terminal of the mounted device is exemplarily shown as a representative.

  The output terminal of the device is not particularly limited, but is connected to a signal line L1 having a characteristic impedance of 50Ω. The other end of the signal line L1 is connected to a damping resistor Rs having a resistance of about 20Ω, although not particularly limited. A switch SW is provided at the other end of the resistor Rs. The input terminal of the device is not particularly limited, but is connected to a signal line L2 having a characteristic impedance of 50Ω. The other end of the signal line L2 is connected to a damping resistor Rs having a resistance of about 20Ω, although not particularly limited. A switch SW is provided at the other end of the resistor Rs.

  The switch SW is constituted by a transfer switch, and switching between the contact a and the contact b is performed. Although not particularly limited, the contact b is connected to the resistor Rs corresponding to the signal line L2 and one end of the signal line L4 having a characteristic impedance of 50Ω as described above. The contact a is connected to one end of the signal line L3 having a characteristic impedance of 50Ω as described above. The other ends of the signal lines L3 and L4 are connected to a tester via an appropriate cable (not shown).

  The switch SW is connected to the contact b side during the loop test as shown in FIG. That is, the switch SW connects the damping resistors Rs. Thereby, the signal output from the output terminal of the device is input to the input terminal of the device through the signal line L1-damping resistor Rs-Rs-signal line L2, and a loop is configured. Before such signal transmission is performed, a test pattern or test mode using JTAG / TAP is set from the tester side to a test circuit (BIST) provided in the device. Then, the output signal A is output from the output circuit of the device through the output terminal by BIST, and is input as an input signal B to the input terminal through the loop (L1-Rs-Rs-L2).

  For example, when the operating frequency of the device is higher than the frequency of the tester, a clock generation circuit is provided on the test board, and the device is operated using this clock. Thereby, for example, a loop test in real time of a device (LSI) having a performance of 200 Mbps to 667 Mbps can be performed using a tester having a performance of 166 Mbps (333 MHz) as described above.

  In this embodiment, a signal path branched to the signal line L4 is provided at an interconnection point of the damping resistor Rs by the switch SW in the middle of the loop, and terminated with a termination resistor on the tester side. The presence of such a signal path allows a signal reflected between the loops to escape to the tester side by combining the damping resistance Rs and the 50Ω termination resistance of the tester, and the resonance of the signal within the loopback circuit ( (Reflection) can be suppressed.

  FIG. 2 shows a waveform diagram in the loop of FIG. Signal A is an output waveform on the output terminal side, and signal B is an input waveform on the input terminal side. This waveform is obtained by computer simulation, and the disturbance of the waveform, such as signals A and B, can be significantly reduced by the absorption of the reflection, as apparent from comparison with FIG.

  FIG. 3 shows a block diagram of another embodiment for explaining a test board and a test method according to the present invention. The figure shows an example in which a direct current (DC) test and a low-speed function test are performed. When performing the DC test and the low-speed function test, the switch SW is switched to the contact a side. Thereby, the output signal A from the output terminal of the device is transmitted as an input signal B as an input signal on the tester side through the signal line L1-damping resistor Rs-switch SW-signal line L3. Further, the output signal B from the tester is transmitted as the input signal A to the input terminal of the device through the signal line L4-damping resistor Rs-signal line L2.

  FIG. 4 shows the output waveform A of the device and the input waveform B of the tester obtained by computer simulation as described above. FIG. 5 also shows the output waveform B of the tester and the input waveform A of the device, which are similarly obtained by computer simulation. Signal transmission and reception in DC test and low-speed function test is not a problem. Therefore, the DC test and tester performance can be improved continuously before or after the loop test only by switching the switch SW as described above. A low-speed function test can be performed.

  FIG. 6 shows a block diagram of another embodiment for explaining a test board and a test method according to the present invention. In the figure, an example of performing timing calibration is shown. The switch SW is also connected to the contact a side when performing this timing calibration. In addition, no device is attached to the socket, and the wirings L1 and L2 are in a high impedance state on the device side. In this state, when the signal A is output from the tester side, it is reflected by the device side B of the wiring L2 and returns to the tester side through the same path. The round trip time is measured to measure the signal delay amount on the test board. FIG. 7 shows signals A and B obtained by computer simulation as described above. The round-trip propagation time as shown in FIG.

  In the embodiment described above, the degree of freedom of connection between LSIs (devices) is greater than that of the conventional test substrate as shown in FIG. Further, since the communication efficiency is improved, the data transfer efficiency is increased. In the conventional system as shown in FIG. 9, the DC and low-speed function test and the loopback test are switched by two switches (transfer relays). However, in the above-described embodiment, this can be handled by one switch. As described above, by combining the damping resistor and the 50Ω termination resistance of the tester during the loopback test, it is possible to release the reflected signal to the tester and suppress the resonance (reflection) of the signal in the loopback circuit. is there. It is also possible to take into account timing correction (timing calibration) during normal function tests. The DC circuit is compatible with SSTL used for a DDR interface and the like, and can perform a test while suppressing the transient current consumption of the LSI (device), leading to an improvement in the LSI operation margin. The configuration is close to the customer's product specifications in terms of DC, and test reliability is improved. The timing correction function of the tester can also be used by the timing calibration.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, the switch SW is connected to the wiring L1 around the wiring L2 instead of switching between the damping Rs and the wiring L3 to which the wiring L2 is connected around the wiring L1 as in the above embodiment. The damping Rs and the wiring L4 may be switched. In this case, the damping resistor Rs connected to the wiring L1 and the wiring L3 are always connected. The test board may be provided with a plurality of sockets to test a plurality of devices simultaneously. In this case, even if the number of input / output terminals of the device is large, the number of switches to be mounted may be half as described above. Therefore, the number of devices that can be mounted can be increased, and the efficiency of the test can be improved. The present invention can be widely used as a test substrate and a test method for performing a loopback test.

It is a block diagram of one Example for demonstrating the test board | substrate and test method which concern on this invention. FIG. 2 is a waveform diagram of FIG. 1. It is a block diagram of other one Example for demonstrating the test board | substrate and test method which concern on this invention. FIG. 3 is a waveform diagram of FIG. 2. FIG. 3 is another waveform diagram of FIG. 2. It is a block diagram of other one Example for demonstrating the test board | substrate and test method which concern on this invention. FIG. 7 is a waveform diagram of FIG. 6. It is a block diagram for demonstrating the test board | substrate considered prior to this invention. FIG. 9 is a waveform diagram of FIG. 8.

Explanation of symbols

  L1 to L4 ... signal line, Rs ... resistance (damping)

Claims (5)

A socket for mounting a non-test device;
A first signal line connecting the output terminal of the non-test device and the switch;
A second signal line connecting between the input terminal of the non-test device and the switch;
A first resistance element provided between the first signal line and the switch and having an impedance smaller than that of the first signal line;
A second resistance element provided between the second signal line and the switch and having an impedance smaller than that of the second signal line;
A third signal line connecting the first or second resistance element and the tester via the switch;
A fourth signal line connecting the second or first resistance element and the tester;
The switch is configured to connect the first resistance element and the second resistance element during a loop test, and the first or second resistance element and the second resistance element during a direct current, low speed test, or timing calibration. A test board configured to connect the third or fourth signal line. In claim 1,
The first to fourth signal lines are formed so as to have a characteristic impedance of 50Ω, and the first and second resistance means are set to a resistance value about half of the resistance value. A first signal line connecting the output terminal of the non-test device and the switch; a second signal line connecting the input terminal of the non-test device and the switch; the first signal line and the switch; Between the first signal line and the first signal line, and between the second signal line and the switch, and the impedance is smaller than that of the second signal line. A second signal line connecting the first or second resistance element and the tester via the switch, and a fourth signal line connecting the second or first resistance element and the tester. Using a test board having a signal line and a tester connected via the third and fourth signal lines,
A non-test device is mounted on the test board,
A first operation for inputting a test pattern from the tester to the non-test device;
The switch connects the first resistance element and the second resistance element, terminates the tester side of the fourth signal line with a termination resistor, and inputs an output signal from the output terminal to the input terminal. A test method that performs a loop test. In claim 3,
The test method in which the first to fourth signal lines are formed to have a characteristic impedance of 50Ω, and the first and second resistance means are set to a resistance value about half of the first and second resistance means. In claim 3,
Before or after the loop test, the switch is switched to connect the first or second resistance element and the third signal line or the fourth signal line, and either DC, low-speed test, or timing calibration is performed. Test method.

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