JP2008294415A5 - - Google Patents

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JP2008294415A5
JP2008294415A5 JP2008099483A JP2008099483A JP2008294415A5 JP 2008294415 A5 JP2008294415 A5 JP 2008294415A5 JP 2008099483 A JP2008099483 A JP 2008099483A JP 2008099483 A JP2008099483 A JP 2008099483A JP 2008294415 A5 JP2008294415 A5 JP 2008294415A5
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Prior art keywords
insulating layer
conductor portion
substrate
wiring layer
layer
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JP2008099483A
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Japanese (ja)
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JP2008294415A (en
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Priority to JP2008099483A priority Critical patent/JP2008294415A/en
Priority claimed from JP2008099483A external-priority patent/JP2008294415A/en
Priority to US12/109,811 priority patent/US7969005B2/en
Publication of JP2008294415A publication Critical patent/JP2008294415A/en
Priority to US13/073,225 priority patent/US20110177688A1/en
Publication of JP2008294415A5 publication Critical patent/JP2008294415A5/ja
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Claims (17)

絶縁層の一方の面上に導体部を形成する第１の工程と、
前記絶縁層の他方の面から前記導体部を露出させる第２の工程と、
前記導体部の露出した箇所および前記絶縁層の他方の面上に第１の配線層を設ける第３の工程と、
回路素子が形成された基板であって、該基板の表面に第２の配線層が形成されている基板を用意する第４の工程と、
前記第３の工程により前記第１の配線層が設けられた前記導体部と、前記第２の配線層とを対向させた状態で、前記絶縁層と前記基板とを圧着して前記導体部を前記絶縁層に埋め込む第５の工程と、
を含むことを特徴とする半導体モジュールの製造方法。 A first step of forming a conductor portion on one surface of the insulating layer;
A second step of exposing the conductor portion from the other surface of the insulating layer;
A third step of providing a first wiring layer on the exposed portion of the conductor and the other surface of the insulating layer;
A fourth step of preparing a substrate on which circuit elements are formed, the substrate having a second wiring layer formed on a surface of the substrate;
In the state where the conductor portion provided with the first wiring layer in the third step is opposed to the second wiring layer, the insulating layer and the substrate are pressure-bonded to form the conductor portion. A fifth step of embedding in the insulating layer;
A method for manufacturing a semiconductor module, comprising: 繊維の向きが絶縁層の厚さ方向と交差するように配向された繊維状の充填材であって該絶縁層より熱膨張係数が小さい繊維状の充填材、を含有する絶縁層の一方の面上に導体部を形成する第１の工程と、
前記絶縁層の他方の面から前記導体部を露出させる第２の工程と、
前記導体部の露出した箇所および前記絶縁層の他方の面上に第１の配線層を設ける第３の工程と、
回路素子が形成された基板であって、該基板の表面に第２の配線層が形成されている基板を用意する第４の工程と、
前記第３の工程により前記第１の配線層が設けられた前記導体部と、前記第２の配線層とを対向させた状態で、前記絶縁層と前記基板とを圧着して前記導体部を前記絶縁層に埋め込む第５の工程と、
を含むことを特徴とする半導体モジュールの製造方法。 One surface of an insulating layer containing a fibrous filler oriented so that the fiber direction intersects the thickness direction of the insulating layer and having a smaller coefficient of thermal expansion than the insulating layer A first step of forming a conductor portion thereon;
A second step of exposing the conductor portion from the other surface of the insulating layer;
A third step of providing a first wiring layer on the exposed portion of the conductor and the other surface of the insulating layer;
A fourth step of preparing a substrate on which circuit elements are formed, the substrate having a second wiring layer formed on a surface of the substrate;
In the state where the conductor portion provided with the first wiring layer in the third step is opposed to the second wiring layer, the insulating layer and the substrate are pressure-bonded to form the conductor portion. A fifth step of embedding in the insulating layer;
A method for manufacturing a semiconductor module, comprising: 前記第２の工程において、前記導体部の露出する面を粗化する粗化手段を用いることを特徴とする請求項１または２に記載の半導体モジュールの製造方法。   3. The method of manufacturing a semiconductor module according to claim 1, wherein in the second step, roughening means for roughening the exposed surface of the conductor portion is used. 前記粗化手段としてレーザを用い、複数回のレーザ照射により、前記絶縁層の他方の面からレーザのスポット径より大きなビアホールを形成するとともに前記導体部の露出する
面を粗化することを特徴とする請求項３に記載の半導体モジュールの製造方法。 A laser is used as the roughening means, and a via hole larger than the laser spot diameter is formed from the other surface of the insulating layer by laser irradiation a plurality of times, and the exposed surface of the conductor portion is roughened. A method for manufacturing a semiconductor module according to claim 3. 前記第２の工程において、前記導体部の露出する面の算術平均粗さＲａが２〜５０μｍとなるように前記絶縁層の他方の面から開口部を形成することを特徴とする請求項３または４に記載の半導体モジュールの製造方法。   In the second step, the opening is formed from the other surface of the insulating layer so that the arithmetic average roughness Ra of the exposed surface of the conductor portion is 2 to 50 µm. 5. A method for producing a semiconductor module according to 4. 前記第１の工程において、前記絶縁層の表面と垂直な方向の前記導体部の高さが、前記絶縁層の表面と平行な方向の前記導体部の長さより小さくなるように該導体部を形成することを特徴とする請求項１乃至５のいずれかに記載の半導体モジュールの製造方法。   In the first step, the conductor portion is formed such that the height of the conductor portion in a direction perpendicular to the surface of the insulating layer is smaller than the length of the conductor portion in a direction parallel to the surface of the insulating layer. A method for manufacturing a semiconductor module according to claim 1, wherein: 絶縁層の一方の面上に導体部を形成する第１の工程と、
前記絶縁層の他方の面から前記導体部を露出させる第２の工程と、
前記導体部の露出した箇所および前記絶縁層の他方の面上に配線層を設ける第３の工程と、を含み、
前記第２の工程において、前記導体部の露出する面を粗化する粗化手段を用いることを特徴とする素子搭載用基板の製造方法。 A first step of forming a conductor portion on one surface of the insulating layer;
A second step of exposing the conductor portion from the other surface of the insulating layer;
And a third step of providing a wiring layer on the exposed portion of the conductor portion and the other surface of the insulating layer,
In the second step, a roughening means for roughening an exposed surface of the conductor portion is used. 前記第１の工程において、前記絶縁層は、繊維の向きが絶縁層の厚さ方向と交差するように配向された繊維状の充填材であって該絶縁層より熱膨張係数が小さい繊維状の充填材、を含有する絶縁層を有していることを特徴とする請求項７に記載の素子搭載用基板の製造方法。 In the first step, the insulating layer is a fibrous filler that is oriented so that the fiber direction intersects the thickness direction of the insulating layer, and has a fibrous coefficient smaller than that of the insulating layer. The element mounting substrate manufacturing method according to claim 7, further comprising an insulating layer containing a filler. 前記粗化手段としてレーザを用い、複数回のレーザ照射により、前記絶縁層の他方の面からレーザのスポット径より大きなビアホールを形成するとともに前記導体部の露出する面を粗化することを特徴とする請求項７または８に記載の素子搭載用基板の製造方法。   A laser is used as the roughening means, and a via hole larger than the laser spot diameter is formed from the other surface of the insulating layer by laser irradiation a plurality of times, and the exposed surface of the conductor portion is roughened. The manufacturing method of the board | substrate for element mounting of Claim 7 or 8. 前記第２の工程において、前記導体部の露出する面の算術平均粗さＲａが２〜５０μｍとなるように前記絶縁層の他方の面から開口部を形成することを特徴とする請求項７乃至９のいずれかに記載の素子搭載用基板の製造方法。   In the second step, the opening is formed from the other surface of the insulating layer so that the arithmetic average roughness Ra of the exposed surface of the conductor portion is 2 to 50 μm. 10. A method for manufacturing an element mounting board according to any one of 9 above. 前記第１の工程において、前記絶縁層の表面と垂直な方向の前記導体部の高さが、前記絶縁層の表面と平行な方向の前記導体部の長さより小さくなるように該導体部を形成することを特徴とする請求項７乃至１０のいずれかに記載の素子搭載用基板の製造方法。   In the first step, the conductor portion is formed such that the height of the conductor portion in a direction perpendicular to the surface of the insulating layer is smaller than the length of the conductor portion in a direction parallel to the surface of the insulating layer. The method for manufacturing an element mounting substrate according to claim 7, wherein: 絶縁層と、
前記絶縁層の一方の面上に形成された導体部と、
前記絶縁層の他方の面上および前記絶縁層の他方の面から前記導体部まで貫通している貫通部に設けられた配線層と、を備え、
前記導体部は、前記配線層と接触する面の算術平均粗さＲａが２〜５０μｍであることを特徴とする素子搭載用基板。 An insulating layer;
A conductor formed on one surface of the insulating layer;
A wiring layer provided on the other surface of the insulating layer and a penetrating portion penetrating from the other surface of the insulating layer to the conductor portion, and
The element mounting substrate, wherein the conductor portion has an arithmetic average roughness Ra of 2 to 50 μm on a surface in contact with the wiring layer. 前記絶縁層は、繊維の向きが絶縁層の厚さ方向と交差するように配向された繊維状の充填材であって該絶縁層より熱膨張係数が小さい繊維状の充填材、を含有することを特徴とする請求項１２に記載の素子搭載用基板。   The insulating layer contains a fibrous filler that is oriented so that the fiber direction intersects the thickness direction of the insulating layer and has a smaller thermal expansion coefficient than the insulating layer. The device mounting substrate according to claim 12. 前記導体部は、前記絶縁層の表面と垂直な方向の高さが、前記絶縁層の表面と平行な方向の長さより小さいことを特徴とする請求項１２または１３に記載の素子搭載用基板。   14. The element mounting substrate according to claim 12, wherein the conductor portion has a height in a direction perpendicular to a surface of the insulating layer smaller than a length in a direction parallel to the surface of the insulating layer. 絶縁層と、
前記絶縁層の上に設けられた第１の配線層と、
回路素子が形成された基板と、
前記基板の表面に形成された第２の配線層と、
前記絶縁層に埋め込まれた状態で前記第１の配線層および前記第２の配線層を電気的に接続する導体部と、を備え、
前記導体部は、前記第１の配線層と接触する面の算術平均粗さＲａが２〜５０μｍであることを特徴とする半導体モジュール。 An insulating layer;
A first wiring layer provided on the insulating layer;
A substrate on which circuit elements are formed;
A second wiring layer formed on the surface of the substrate;
A conductor portion that electrically connects the first wiring layer and the second wiring layer in a state of being embedded in the insulating layer,
The semiconductor module according to claim 1, wherein the conductor portion has an arithmetic average roughness Ra of 2 to 50 μm on a surface in contact with the first wiring layer. 繊維の向きが絶縁層の厚さ方向と交差するように配向された繊維状の充填材であって該絶縁層より熱膨張係数が小さい繊維状の充填材、を含有する絶縁層と、
前記絶縁層の上に設けられた第１の配線層と、
回路素子が形成された基板と、
前記基板の表面に形成された第２の配線層と、
前記絶縁層に埋め込まれた状態で前記第１の配線層および前記第２の配線層を電気的に接続する導体部と、を備え、
前記繊維状の充填材は、前記絶縁層より熱膨張係数が小さく、前記導体部の近傍において前記第１の配線層に向かって湾曲しており、
前記導体部は、前記第１の配線層と接触する面の算術平均粗さＲａが２〜５０μｍであることを特徴とする半導体モジュール。 An insulating layer containing a fibrous filler oriented so that the direction of the fiber intersects the thickness direction of the insulating layer and having a smaller coefficient of thermal expansion than the insulating layer;
A first wiring layer provided on the insulating layer;
A substrate on which circuit elements are formed;
A second wiring layer formed on the surface of the substrate;
A conductor portion that electrically connects the first wiring layer and the second wiring layer in a state of being embedded in the insulating layer,
The fibrous filler has a smaller coefficient of thermal expansion than the insulating layer and is curved toward the first wiring layer in the vicinity of the conductor portion,
The semiconductor module according to claim 1, wherein the conductor portion has an arithmetic average roughness Ra of 2 to 50 μm on a surface in contact with the first wiring layer. 前記導体部は、前記絶縁層の表面と垂直な方向の高さが、前記絶縁層の表面と平行な方向の長さより小さいことを特徴とする請求項１５または１６に記載の半導体モジュール。   17. The semiconductor module according to claim 15, wherein the conductor portion has a height in a direction perpendicular to the surface of the insulating layer smaller than a length in a direction parallel to the surface of the insulating layer.
JP2008099483A 2007-04-27 2008-04-07 Element packaging board and method for manufacturing same, semiconductor module and method for manufacturing same, and portable device Withdrawn JP2008294415A (en)

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JP2008099483A JP2008294415A (en) 2007-04-27 2008-04-07 Element packaging board and method for manufacturing same, semiconductor module and method for manufacturing same, and portable device
US12/109,811 US7969005B2 (en) 2007-04-27 2008-04-25 Packaging board, rewiring, roughened conductor for semiconductor module of a portable device, and manufacturing method therefor
US13/073,225 US20110177688A1 (en) 2007-04-27 2011-03-28 Packaging board and manufacturing method therefor, semiconductor module and manufacturing method therefor, and portable device

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JP2007119388 2007-04-27
JP2008099483A JP2008294415A (en) 2007-04-27 2008-04-07 Element packaging board and method for manufacturing same, semiconductor module and method for manufacturing same, and portable device

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JP2008294415A5 true JP2008294415A5 (en) 2011-05-19

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JP5978577B2 (en) * 2011-09-16 2016-08-24 株式会社リコー Multilayer wiring board
DE112021002956T5 (en) * 2020-05-26 2023-03-09 Rohm Co., Ltd. SEMICONDUCTOR DEVICE AND METHOD OF MAKING SEMICONDUCTOR DEVICE

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JPH11224919A (en) * 1997-12-05 1999-08-17 Toppan Printing Co Ltd Substrate for semiconductor device
JP2000261149A (en) * 1999-03-08 2000-09-22 Ibiden Co Ltd Mutilayer printed wiring board and manufacture thereof
JP2001144441A (en) * 1999-11-05 2001-05-25 Three M Innovative Properties Co Multilayer double sided wiring board and method of production
JP2002118210A (en) * 2000-10-10 2002-04-19 Hitachi Cable Ltd Interposer for semiconductor device and semiconductor using the same
JP2002237663A (en) * 2001-02-09 2002-08-23 Mitsui Chemicals Inc Resin board with metallic circuit, and method for manufacturing the same
JP3850260B2 (en) * 2001-04-27 2006-11-29 イビデン株式会社 Manufacturing method of semiconductor chip

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