JP2007096186A - Circuit board and its production process - Google Patents

Circuit board and its production process Download PDF

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Publication number
JP2007096186A
JP2007096186A JP2005286299A JP2005286299A JP2007096186A JP 2007096186 A JP2007096186 A JP 2007096186A JP 2005286299 A JP2005286299 A JP 2005286299A JP 2005286299 A JP2005286299 A JP 2005286299A JP 2007096186 A JP2007096186 A JP 2007096186A
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Prior art keywords
circuit board
resin
insulating layer
side wall
conductor portion
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Yasuhiro Obara
泰浩 小原
Ryosuke Usui
良輔 臼井
Noriaki Kojima
則章 児島
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to JP2005286299A priority Critical patent/JP2007096186A/en
Priority to CN2006101543180A priority patent/CN1942049B/en
Priority to US11/536,317 priority patent/US7737368B2/en
Publication of JP2007096186A publication Critical patent/JP2007096186A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To enhance adhesion between an insulation layer and a conductor portion of a circuit board. <P>SOLUTION: The circuit board comprises a plurality of wiring layers, an insulation layer 20 having a fibrous filler and a resin 24 and insulating the plurality of wiring layers, and a conductor portion 41 formed on the sidewall 30a of a via 30 penetrating the insulation layer 20. The fibrous filler projecting from the sidewall 30a and contained in the conductor portion 41 has a length X longer than the film thickness Z of the conductor portion 41. Consequently, adhesion between the insulation layer and the conductor portion can be enhanced and a highly reliable circuit board can be provided. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、繊維状の充填剤を含む絶縁層を有する回路基板の技術に関する。より具体的には、絶縁層に対する金属等の導体部の密着性が優れた回路基板の技術に関する。   The present invention relates to a technique of a circuit board having an insulating layer containing a fibrous filler. More specifically, the present invention relates to a technique for a circuit board having excellent adhesion of a conductor portion such as a metal to an insulating layer.

近年、LSIのさらなる高性能化、高機能化にともない、その消費電力は増加の傾向にある。また、電子機器の小型化にともなって、実装基板にも小型化、高密度化、多層化が求められている。このため、回路基板の体積当たりの消費電力(熱密度)は上昇し、その放熱対策の必要性が高まっている。   In recent years, the power consumption of LSIs has been increasing as LSIs have further improved performance and functions. Further, as electronic devices are downsized, mounting substrates are also required to be downsized, high density, and multi-layered. For this reason, the power consumption (heat density) per volume of the circuit board is increased, and the necessity for heat radiation countermeasures is increasing.

このため、多層基板においては、多層基板の各層の導通を確保したり温度上昇を抑制したりするためのビアが設けられた構造が知られている。また、強度や機能性向上のために樹脂にガラス繊維を混入した絶縁層も用いられている。   For this reason, in a multilayer board | substrate, the structure provided with the via | veer for ensuring conduction | electrical_connection of each layer of a multilayer board | substrate, or suppressing a temperature rise is known. In addition, an insulating layer in which glass fibers are mixed into a resin is also used to improve strength and functionality.

特許文献1には、有機系樹脂基板にザグリ加工を施し、形成された凹部の側壁に露出したヒゲ状の多数の繊維をスルーホールめっき層で被覆したプリント配線基板が開示されている。
特開平5−55401号公報
Patent Document 1 discloses a printed wiring board in which an organic resin substrate is subjected to counterbore processing and a large number of beard-like fibers exposed on the side walls of the formed recesses are covered with a through-hole plating layer.
Japanese Patent Laid-Open No. 5-55401

しかしながら、凹部の側壁から垂直に露出した繊維の長さは、スルーホールめっき層で被覆できる程度までしか許容されず、銅めっきの厚さに依存する。そのため、熱負荷が高い時に絶縁樹脂から銅めっきが剥離する可能性があった。   However, the length of the fiber exposed vertically from the side wall of the recess is allowed only to the extent that it can be covered with the through-hole plating layer, and depends on the thickness of the copper plating. Therefore, there is a possibility that the copper plating is peeled off from the insulating resin when the heat load is high.

本発明はこうした課題に鑑みてなされたものであり、その目的は、回路基板における絶縁層と導体部との密着性を向上させる技術の提供にある。   This invention is made | formed in view of such a subject, The objective is to provide the technique which improves the adhesiveness of the insulating layer and conductor part in a circuit board.

本発明のある態様は、回路基板である。この回路基板は、複数の配線層と、繊維状の充填材と樹脂とを有し前記複数の配線層を絶縁する絶縁層と、前記絶縁層を貫通する貫通孔の側壁に形成された導体部と、を備え、前記側壁から突出し前記導体部に内包される繊維状の充填剤の長さが、前記導体部の膜厚より大きいことを特徴とする。ここで、繊維状の充填剤としては、放熱性や強度の観点からガラス繊維が好適である。   One embodiment of the present invention is a circuit board. The circuit board includes a plurality of wiring layers, an insulating layer having a fibrous filler and a resin, and insulating the plurality of wiring layers, and a conductor portion formed on a side wall of a through-hole penetrating the insulating layer. The length of the fibrous filler that protrudes from the side wall and is included in the conductor portion is larger than the film thickness of the conductor portion. Here, as the fibrous filler, glass fiber is suitable from the viewpoint of heat dissipation and strength.

この態様によれば、導体部に内包される繊維状の充填剤の長さが、導体部の膜厚より大きくなることで、アンカー効果により絶縁層と導体部との密着性を向上することができる。なお、繊維状の充填剤の全てが導体部の膜厚より長い必要はなく、少なくとも一つの繊維状の充填剤が長ければ上述の効果を得ることができる。   According to this aspect, the length of the fibrous filler included in the conductor portion is larger than the film thickness of the conductor portion, thereby improving the adhesion between the insulating layer and the conductor portion due to the anchor effect. it can. In addition, it is not necessary for all the fibrous fillers to be longer than the film thickness of the conductor portion, and the above-described effects can be obtained if at least one fibrous filler is long.

ここで、導体部とは、複数の配線層と導通して多層配線を構成する電気的導通部として機能する場合だけでなく、放熱の際の伝熱経路として機能する場合も含む。導体部としては、めっき処理により形成可能な金属が好ましく、例えば、銅めっきにより形成してもよい。   Here, the conductor portion includes not only the case of functioning as an electrical conduction portion that is connected to a plurality of wiring layers to form a multilayer wiring, but also the case of functioning as a heat transfer path during heat dissipation. As a conductor part, the metal which can be formed by a plating process is preferable, for example, you may form by copper plating.

また、導体部が銅めっきの場合、熱膨張率の小さいガラス繊維を銅めっき内へ食い込ませることで、ガラスと銅の熱膨張率が複合され銅めっきの熱膨張率が減少する。その結果、熱負荷時における銅めっきの膨張が軽減され、樹脂と銅めっきとの境界近傍におけるクラックの発生を抑制することができる。   Moreover, when a conductor part is copper plating, the thermal expansion coefficient of glass and copper is compounded and the thermal expansion coefficient of copper plating reduces by making glass fiber with a small thermal expansion coefficient bite into copper plating. As a result, the expansion of copper plating during a thermal load is reduced, and the generation of cracks in the vicinity of the boundary between the resin and copper plating can be suppressed.

上記態様において、貫通孔はドリル加工により形成されることが好ましい。これによれば、ドリル加工の際の回転により、側壁から突出するガラス繊維が側壁に対して斜めになりやすく、突き出たガラス繊維の長さが導体部の膜厚より大きくなりやすい。   In the above aspect, the through hole is preferably formed by drilling. According to this, the glass fiber protruding from the side wall tends to be inclined with respect to the side wall due to rotation during drilling, and the length of the protruding glass fiber tends to be larger than the film thickness of the conductor portion.

また、本発明の他の態様は、回路基板の製造方法である。この回路基板の製造方法は、繊維状の充填材と樹脂とを有し複数の配線層を絶縁する絶縁層にドリル加工により貫通孔を形成する工程と、前記貫通孔の側壁のうち樹脂部分の溶解処理を行う工程と、樹脂部分が溶解された側壁にめっき処理により導体部を形成する工程と、を有することを特徴とする。   Another embodiment of the present invention is a method for manufacturing a circuit board. The circuit board manufacturing method includes a step of forming a through hole by drilling in an insulating layer having a fibrous filler and a resin to insulate a plurality of wiring layers, and a resin portion of the side wall of the through hole. And a step of forming a conductor portion by plating on the side wall where the resin portion is dissolved.

この態様によれば、側壁のうち樹脂部分の溶解処理を前記めっき処理の前に行う。そのため、側壁のうち樹脂部分が溶解されるため、絶縁層に含まれていた繊維状の充填剤をより露出することができ、導体部の膜厚より長く突き出た繊維状の充填剤を形成することができる。ここで、繊維状の充填剤としては、放熱性や強度の観点からガラス繊維が好適である。   According to this aspect, the resin portion of the sidewall is melted before the plating treatment. Therefore, since the resin portion of the side wall is dissolved, the fibrous filler contained in the insulating layer can be more exposed, and the fibrous filler protruding longer than the film thickness of the conductor portion is formed. be able to. Here, as the fibrous filler, glass fiber is suitable from the viewpoint of heat dissipation and strength.

なお、上述した各要素を適宜組み合わせたものも、本件特許出願によって特許による保護を求める発明の範囲に含まれうる。   A combination of the above-described elements as appropriate can also be included in the scope of the invention for which patent protection is sought by this patent application.

本発明によれば、回路基板における絶縁層と導体部との密着性を向上させることができ、信頼性の高い回路基板を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, the adhesiveness of the insulating layer and conductor part in a circuit board can be improved, and a highly reliable circuit board can be provided.

以下、本発明の実施形態を図面を参照して説明する。なお、以下に述べる構成は例示であり、本発明の範囲を何ら限定するものではない。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the structure described below is an illustration and does not limit the scope of the present invention at all.

(回路基板の構造)
図2は、本実施形態に係る多層の回路基板10の構造を示す断面図である。回路基板10は、複数の絶縁層20,21,22と、絶縁層20を貫通するように形成されたビア30と、複数の絶縁層20の間または絶縁層20の表面上に形成された複数の配線層40と、各配線層40を回路基板10の鉛直方向に導通するビアプラグ50とを備える。
(Structure of circuit board)
FIG. 2 is a cross-sectional view showing the structure of the multilayer circuit board 10 according to the present embodiment. The circuit board 10 includes a plurality of insulating layers 20, 21, 22, vias 30 formed so as to penetrate the insulating layer 20, and a plurality of layers formed between the plurality of insulating layers 20 or on the surface of the insulating layer 20. Wiring layers 40, and via plugs 50 that connect each wiring layer 40 in the vertical direction of the circuit board 10.

絶縁層20は、ガラスクロスに絶縁性の樹脂24を含浸させた材料であり、樹脂としては例えばエポキシ樹脂、BTレジン等のメラミン誘導体、液晶ポリマー、PPE樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等の有機系樹脂が好適に用いられる。ガラスクロスは、エポキシ樹脂内に3層あると好ましい。ここで、1層とは、異なる方向にそれぞれ延びているガラス繊維が交差している状態をいい、3層とは、この状態を単位として上下方向に3段積み重なっている状態をいう。   The insulating layer 20 is a material obtained by impregnating a glass cloth with an insulating resin 24. Examples of the resin include epoxy resin, melamine derivatives such as BT resin, liquid crystal polymer, PPE resin, polyimide resin, fluororesin, phenol resin, An organic resin such as polyamide bismaleimide is preferably used. It is preferable that the glass cloth has three layers in the epoxy resin. Here, one layer means a state in which glass fibers extending in different directions intersect each other, and three layers means a state in which three layers are stacked in the vertical direction with this state as a unit.

なお、本実施形態では、難燃性ガラス布基材のエポキシ樹脂銅張り積層板(例えば、FR−4)を用いた。ここで、FR−4の熱伝導率は0.33W/mK、絶縁耐圧は29MV/mm(印加電圧の周波数が50Hzの場合)である。   In this embodiment, an epoxy resin copper-clad laminate (for example, FR-4) made of a flame-retardant glass cloth base material was used. Here, the thermal conductivity of FR-4 is 0.33 W / mK, and the withstand voltage is 29 MV / mm (when the frequency of the applied voltage is 50 Hz).

ビア30は、回路基板10の表面に配置された発熱体、例えばLSIチップ60で発生する熱を回路基板10の裏面に逃がすサーマルビアとして機能する。   The via 30 functions as a thermal via that releases heat generated by the heating element, for example, the LSI chip 60, disposed on the surface of the circuit board 10 to the back surface of the circuit board 10.

配線層40は、例えばめっき処理による銅配線が好適に用いられる。また、ビアプラグ50は、配線層40と同様の材質である銅を用いることで境界面での良好な導通を達成することができる。   For the wiring layer 40, for example, copper wiring by plating is preferably used. In addition, the via plug 50 can achieve good conduction at the boundary surface by using copper which is the same material as the wiring layer 40.

本実施形態に係る回路基板10に、LSIチップ60などの半導体素子や、キャパシタ、抵抗などの受動素子を実装し、配線層40と電気的に接続することにより、熱伝導性に優れた回路装置が得られる。   A circuit device having excellent thermal conductivity by mounting a semiconductor element such as an LSI chip 60 or a passive element such as a capacitor or resistor on the circuit board 10 according to the present embodiment and electrically connecting to the wiring layer 40. Is obtained.

(ビアの作製方法)
次に、図3を参照して、回路基板10のうちビア30の作製方法を説明する。図3(a)は、ガラスクロスを含む絶縁層を模式的に示した断面図、図3(b)は、(a)に示す絶縁層にドリルによりビアを形成した断面図、図3(c)は、(b)に示すビア近傍を溶解処理した状態を示す断面図、図3(d)は、(c)に示す溶解処理したビアにめっきをした状態を示す断面図である。
(Via fabrication method)
Next, a method for manufacturing the via 30 in the circuit board 10 will be described with reference to FIG. 3A is a cross-sectional view schematically showing an insulating layer including a glass cloth, FIG. 3B is a cross-sectional view in which a via is formed in the insulating layer shown in FIG. 3A by a drill, and FIG. ) Is a cross-sectional view showing a state in which the vicinity of the via shown in (b) is melt-treated, and FIG. 3D is a cross-sectional view showing a state in which the melt-treated via shown in (c) is plated.

本実施形態に係る絶縁層20は、図3(a)に示すように、紙面横方向に延びるガラス繊維23aと、紙面鉛直方向に延びるガラス繊維23bとが内包されている(以下、ガラス繊維23a,23bをまとめてガラス繊維23という)。   As shown in FIG. 3A, the insulating layer 20 according to the present embodiment includes glass fibers 23a extending in the horizontal direction on the paper surface and glass fibers 23b extending in the vertical direction on the paper surface (hereinafter referred to as glass fibers 23a). 23b are collectively referred to as glass fiber 23).

この絶縁層20の所望の位置にドリル加工によりビア30を形成すると、ガラス繊維23の一部が切断される(図3(b)参照)。本実施形態では、ドリル加工の際の回転により、側壁から突出するガラス繊維が側壁に対して斜めになりやすく、ガラス繊維の長さが導体部の膜厚より大きくなりやすい。   When the via 30 is formed at a desired position of the insulating layer 20 by drilling, a part of the glass fiber 23 is cut (see FIG. 3B). In this embodiment, the glass fiber protruding from the side wall tends to be inclined with respect to the side wall due to rotation during drilling, and the length of the glass fiber tends to be larger than the film thickness of the conductor portion.

この状態で、ガラス繊維23を溶解させず、絶縁性の樹脂24のみを溶解する薬液(例えば過マンガン酸溶液)によるデスミア処理を行う。この処理により、ドリル加工によるビア形成時に発生した樹脂カスや、ビア側壁表面の樹脂が除去される。しかし、放熱性を高める目的で絶縁層20に充填された無機材料、本実施形態ではガラス繊維23は溶解されずに残る。そのため、絶縁層に含まれていたガラス繊維をより露出することができ、導体部の膜厚より長いガラス繊維を形成することができる。   In this state, desmear treatment with a chemical solution (for example, a permanganate solution) that dissolves only the insulating resin 24 without dissolving the glass fiber 23 is performed. By this process, the resin residue generated at the time of via formation by drilling and the resin on the via sidewall surface are removed. However, the inorganic material filled in the insulating layer 20 for the purpose of enhancing the heat dissipation property, in this embodiment, the glass fiber 23 remains undissolved. Therefore, the glass fiber contained in the insulating layer can be exposed more, and a glass fiber longer than the film thickness of the conductor portion can be formed.

その結果、図3(c)に示すように、絶縁層20に内包されていたガラス繊維23は、ビア30の側壁からその一部が突き出た状態となる。   As a result, as shown in FIG. 3C, a part of the glass fiber 23 included in the insulating layer 20 protrudes from the side wall of the via 30.

次に、パラジウムをキャタリストに用いた無電解銅めっき処理によって、ビア30側壁表面に数百ナノメートルの銅薄膜を析出させる。その後、硫酸銅溶液をめっき液とした電解めっきによって導体部41を形成する(図3(d)参照)。銅めっきの膜厚は、数十μm程度の厚さが好ましく、より好適には10〜30μm程度の膜厚がよい。本実施形態では膜厚を約15μmとした。   Next, a copper thin film of several hundred nanometers is deposited on the via 30 side wall surface by electroless copper plating using palladium as a catalyst. Thereafter, the conductor portion 41 is formed by electrolytic plating using a copper sulfate solution as a plating solution (see FIG. 3D). The thickness of the copper plating is preferably about several tens of μm, more preferably about 10 to 30 μm. In this embodiment, the film thickness is about 15 μm.

このように、ガラス繊維23がビア側壁から突出した状態で銅めっき処理をすることで、突出したガラス繊維23が銅めっきに取り込まれた形となり、絶縁層20に含まれる樹脂とめっきにより形成された導体部41との密着性を向上させることができる。その結果、樹脂から導体部である金属の膜が剥がれたり、クラックが発生したりするのを抑制し、回路基板の信頼性を向上することができる。   Thus, by performing the copper plating process with the glass fiber 23 protruding from the via side wall, the protruding glass fiber 23 is taken into the copper plating, and is formed by the resin and plating contained in the insulating layer 20. Adhesion with the conductor part 41 can be improved. As a result, it is possible to suppress the peeling of the metal film that is the conductor portion from the resin and the occurrence of cracks, thereby improving the reliability of the circuit board.

上述の現象を図1を参照してより詳細に説明する。図1(a)は、ドリル加工により絶縁層にビアを形成した状態を上方から見た際の模式図である。図1(b)は、(a)に示すビアにめっき処理を施した状態を上方から見た際の模式図である。   The above phenomenon will be described in more detail with reference to FIG. Fig.1 (a) is a schematic diagram at the time of seeing the state which formed the via | veer in the insulating layer by drilling from upper direction. FIG.1 (b) is a schematic diagram when the state which plated the via | veer shown to (a) is seen from upper direction.

図1(a)に示すように、ドリル加工により絶縁層20にビア30を形成すると、ビア側壁30aからいくつかのガラス繊維23が突出した状態となる。特に、回転するドリルによりビア30が形成されるため、突出したガラス繊維23のうちのいくつかは、ビア側壁30aに沿って渦巻き状に突出する。   As shown in FIG. 1A, when the via 30 is formed in the insulating layer 20 by drilling, a number of glass fibers 23 protrude from the via sidewall 30a. In particular, since the via 30 is formed by a rotating drill, some of the protruding glass fibers 23 protrude spirally along the via sidewall 30a.

この状態で樹脂のみの溶解を行うと、側壁30aのうち樹脂部分が後退し、ガラス繊維23がより長く露出する。そのため、めっき処理がなされると、図1(b)に示すように、めっき膜厚Zより長さXの大きいガラス繊維が導体部41内に内包されることになる。ここで、導体部に内包されるガラス繊維の長さXは、図1(b)に示すように、側壁30aから突出した例えばガラス繊維23cに沿った長さである。また、めっき膜厚Zは、側壁30aの法線方向に向かう厚さである。本実施形態では、膜厚Zが約15μmであり、その場合は、導体部41に長さXが15〜30μm程度のガラス繊維が存在するとよい。   If only the resin is dissolved in this state, the resin portion of the side wall 30a is retracted, and the glass fiber 23 is exposed longer. Therefore, when the plating process is performed, glass fibers having a length X larger than the plating film thickness Z are encapsulated in the conductor portion 41 as shown in FIG. Here, the length X of the glass fiber included in the conductor portion is, for example, a length along the glass fiber 23c protruding from the side wall 30a, as shown in FIG. Moreover, the plating film thickness Z is the thickness which goes to the normal line direction of the side wall 30a. In this embodiment, the film thickness Z is about 15 μm, and in that case, glass fibers having a length X of about 15 to 30 μm may be present in the conductor portion 41.

したがって、本実施形態によれば、ドリル加工と樹脂の溶解処理により、ガラス繊維の長さX>めっき膜厚Zとなるガラス繊維23が導体部41に存在しやすくなり、ガラス繊維の長さX<めっき膜厚Zとなるガラス繊維しか存在しない場合と比較して、樹脂と配線等の導体部との密着性をより向上し、配線等の金属の剥がれを抑制することができる。   Therefore, according to this embodiment, the glass fiber 23 in which the length X of the glass fiber> the plating film thickness Z> is easily present in the conductor portion 41 by the drilling process and the resin melting treatment, and the length X of the glass fiber <Compared with the case where only the glass fiber having the plating film thickness Z is present, the adhesion between the resin and the conductor part such as wiring can be further improved, and peeling of the metal such as wiring can be suppressed.

本発明は、上述の各実施の形態に限定されるものではなく、当業者の知識に基づいて各種の設計変更等の変形を加えることも可能であり、そのような変形が加えられた実施の形態も本発明の範囲に含まれうるものである。   The present invention is not limited to the above-described embodiments, and various modifications such as design changes can be added based on the knowledge of those skilled in the art. The form can also be included in the scope of the present invention.

上述の実施形態では、絶縁層を貫通しているサーマルビア(貫通孔)の場合を例に説明しているが、これに限られない。絶縁層に設けられた凹部であっても同様の効果を得ることができる。   In the above-described embodiment, the case of a thermal via (through hole) penetrating the insulating layer is described as an example, but the present invention is not limited to this. The same effect can be obtained even if the recess is provided in the insulating layer.

また、上述の実施形態において、めっき膜厚Zは必ずしも均一でなくてもよく、めっき膜厚Zが場所によって異なる場合は、最も薄い膜厚Z1より導体部に内包されるガラス繊維の長さXが大きければよい。   In the above-described embodiment, the plating film thickness Z does not necessarily have to be uniform. When the plating film thickness Z varies depending on the location, the length X of the glass fiber included in the conductor portion from the thinnest film thickness Z1. Should be large.

また、上述の実施形態では、絶縁層の両面に配線層が形成されているが、配線層の構造はこれに限られない。例えば、配線層は絶縁層の片面のみに設けられていてもよい。また、複数の絶縁層を介して複数の配線層が積層されていてもよい。   In the above-described embodiment, the wiring layers are formed on both surfaces of the insulating layer, but the structure of the wiring layers is not limited to this. For example, the wiring layer may be provided only on one side of the insulating layer. A plurality of wiring layers may be stacked via a plurality of insulating layers.

また、上述の実施形態では、絶縁樹脂層は多層であるが、単層構造であってもよい。   In the above-described embodiment, the insulating resin layer is a multilayer, but may be a single layer structure.

図1(a)は、ドリル加工により絶縁層にビアを形成した状態を上方から見た際の模式図である。図1(b)は、(a)に示すビアにめっき処理を施した状態を上方から見た際の模式図である。Fig.1 (a) is a schematic diagram at the time of seeing the state which formed the via | veer in the insulating layer by drilling from upper direction. FIG.1 (b) is a schematic diagram when the state which plated the via | veer shown to (a) is seen from upper direction. 実施形態に係る多層の回路基板の構造を示す断面図である。It is sectional drawing which shows the structure of the multilayer circuit board which concerns on embodiment. 図3(a)は、ガラスクロスを含む絶縁層を模式的に示した断面図、図3(b)は、(a)に示す絶縁層にドリルによりビアを形成した断面図、図3(c)は、(b)に示すビア近傍を溶解処理した状態を示す断面図、図3(d)は、(c)に示す溶解処理したビアにめっきをした状態を示す断面図である。3A is a cross-sectional view schematically showing an insulating layer including a glass cloth, FIG. 3B is a cross-sectional view in which a via is formed in the insulating layer shown in FIG. 3A by a drill, and FIG. ) Is a cross-sectional view showing a state in which the vicinity of the via shown in (b) is melt-processed, and FIG. 3D is a cross-sectional view showing a state in which the melt-processed via shown in (c) is plated.

符号の説明Explanation of symbols

10 回路基板、20,21,22 絶縁層、23 ガラス繊維、24 樹脂、30 ビア、30a 側壁、40 配線層、41 導体部、50 ビアプラグ、60 LSIチップ。   DESCRIPTION OF SYMBOLS 10 Circuit board, 20, 21, 22 Insulating layer, 23 Glass fiber, 24 Resin, 30 Via, 30a Side wall, 40 Wiring layer, 41 Conductor part, 50 Via plug, 60 LSI chip.

Claims (6)

複数の配線層と、
繊維状の充填材と樹脂とを有し前記複数の配線層を絶縁する絶縁層と、
前記絶縁層を貫通する貫通孔の側壁に形成された導体部と、
を備え、
前記側壁から突出し前記導体部に内包される繊維状の充填剤の長さが、前記導体部の膜厚より大きいことを特徴とする回路基板。
Multiple wiring layers;
An insulating layer having a fibrous filler and a resin to insulate the plurality of wiring layers;
A conductor formed on a side wall of a through hole penetrating the insulating layer;
With
A circuit board characterized in that the length of the fibrous filler protruding from the side wall and encapsulated in the conductor is larger than the film thickness of the conductor.
前記繊維状の充填剤は、ガラス繊維であることを特徴とする請求項1に記載の回路基板。   The circuit board according to claim 1, wherein the fibrous filler is a glass fiber. 前記複数の配線層と前記導体部が導通していることを特徴とする請求項1または2に記載の回路基板。   The circuit board according to claim 1, wherein the plurality of wiring layers and the conductor are electrically connected. 前記貫通孔は、ドリル加工により形成されることを特徴とする請求項1乃至3のいずれかに記載の回路基板。   The circuit board according to claim 1, wherein the through hole is formed by drilling. 前記繊維状の充填剤は、前記側壁から突出する方向が側壁の法線方向に対して斜めであることを特徴とする請求項1乃至4のいずれかに記載の回路基板。   5. The circuit board according to claim 1, wherein the fibrous filler has a direction protruding from the side wall oblique to a normal direction of the side wall. 繊維状の充填材と樹脂とを有し複数の配線層を絶縁する絶縁層にドリル加工により貫通孔を形成する工程と、
前記貫通孔の側壁のうち樹脂部分の溶解処理を行う工程と、
樹脂部分が溶解された側壁にめっき処理により導体部を形成する工程と、
を有することを特徴とする回路基板の製造方法。
Forming a through hole by drilling in an insulating layer having a fibrous filler and a resin to insulate a plurality of wiring layers;
A step of dissolving the resin portion of the side wall of the through hole; and
Forming a conductor portion by plating on the side wall where the resin portion is dissolved;
A method of manufacturing a circuit board, comprising:
JP2005286299A 2005-09-30 2005-09-30 Circuit board and its production process Pending JP2007096186A (en)

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JP2005286299A JP2007096186A (en) 2005-09-30 2005-09-30 Circuit board and its production process
CN2006101543180A CN1942049B (en) 2005-09-30 2006-09-20 Circuit board and method of manufacturing circuit board
US11/536,317 US7737368B2 (en) 2005-09-30 2006-09-28 Circuit board and method of manufacturing circuit board

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Publication number Priority date Publication date Assignee Title
JP2015056558A (en) * 2013-09-12 2015-03-23 住友電工プリントサーキット株式会社 Flexible printed wiring board, multilayer printed wiring board, and method for manufacturing flexible printed wiring board

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JP5473413B2 (en) 2008-06-20 2014-04-16 株式会社半導体エネルギー研究所 Wiring substrate manufacturing method, antenna manufacturing method, and semiconductor device manufacturing method
KR102511542B1 (en) * 2015-12-02 2023-03-20 삼성디스플레이 주식회사 Circuit board and display device including the same
JP2020150026A (en) * 2019-03-11 2020-09-17 株式会社村田製作所 Multilayer wiring board

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US5985040A (en) * 1998-09-21 1999-11-16 Electrochemicals Inc. Permanganate desmear process for printed wiring boards

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015056558A (en) * 2013-09-12 2015-03-23 住友電工プリントサーキット株式会社 Flexible printed wiring board, multilayer printed wiring board, and method for manufacturing flexible printed wiring board

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