JP2008293212A - Transaction management method for information processor, and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To execute a read or write operation from/to a register of a memory or I/O device at a much more flexible timing by setting a start point for interrupt processing for operation analysis and debug processing or the like. <P>SOLUTION: This information processor equipped with a plurality of buses 230 to 232 is configured to set trigger conditions for transaction, and to, when detecting the transaction satisfying the trigger conditions, temporarily stop the processing of the transaction, and to generate interrupt for operation analysis and debug processing. Thus, it is possible to achieve the operation analysis and debug processing of an information processor with high flexibility by executing the read-out/write-in of the value of the register of the memory or I/O device just before the processing of the transaction satisfying the trigger conditions. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a transaction management method for an information processing apparatus and an information processing apparatus, and more particularly to a transaction management method for an information processing apparatus and an information processing apparatus capable of performing hardware operation analysis, debugging, and the like inside the apparatus. .

  Conventionally, processing for performing hardware operation analysis, debugging, and the like inside the information processing apparatus is generally performed after the ICE (in-circuit emulator) is used and the ICE detects the start point. It was. When performing hardware operation analysis, debugging, etc. using the ICE, the user connects the ICE to the bus and issues a transaction issued by the CPU (reading and writing to an I / O device connected to a memory or an I / O interface) ). At that time, the user decides a certain condition for the transaction contents (address, data, command, etc.), sets the condition in the ICE register, and detects a transaction on the bus that matches the condition set in ICE. Sometimes generate an interrupt. The above-described processing for performing hardware operation analysis, debugging, and the like within the apparatus performs operation analysis or debugging of the information processing apparatus by using this interrupt as a starting point.

  However, in the above-described method, only transactions that flow on the bus to which the ICE is connected are monitored, and thus a device having a plurality of buses, for example, a CPU, a memory, and an I / O device are connected to different buses. When an ICE is connected to one local bus of an information processing apparatus in which buses are connected by a bus bridge, only transactions flowing on the bus to which the ICE is connected can be monitored. There is a problem that it is impossible to detect a transaction for a memory from a DMA controller of the O device as a monitoring target, perform an interrupt process, and perform debugging.

As a conventional technique related to a bus monitoring apparatus for solving the above-described problem, for example, a technique described in Patent Document 1 is known. In this prior art, a transaction detection device is provided in a bus bridge, and all transactions can be monitored using this transaction detection device.
JP 2006-113906 A

  However, since the conventional technique described in Patent Document 1 described above monitors transactions flowing through the bus and performs an interrupt after detecting a transaction that satisfies the condition, it is intended for analysis of information processing apparatus and execution of debugging. It is limited to after a transaction, and there is a problem that it is not possible to analyze and debug operations preceding a transaction that rewrites the value of a memory or I / O device register before processing a transaction. Yes.

  An object of the present invention is to solve the above-mentioned problems of the prior art, set a starting point for processing such as operation analysis and debugging more flexibly, and read or write to a register of a memory or an I / O device. It is an object of the present invention to provide a transaction management method for an information processing apparatus and an information processing apparatus that can perform hardware operation analysis, debugging, and the like inside the apparatus by executing the interrupt processing.

  According to the present invention, the object is to provide a transaction management method for an information processing apparatus including a plurality of buses and a bus controller connected to all of the plurality of buses, wherein the bus controller monitors a transaction to be processed. When a transaction that satisfies a predetermined condition set in advance is detected, the processing of the detected transaction is not performed and the transaction issuance is repeated by causing the issuer of the transaction to repeat the transaction. , Execute processing of a transaction different from the transaction put in the hold state, and after the processing of another transaction ends, release the hold state of the transaction put in the hold state and process the released transaction Transaction It is achieved by managing.

  Further, the object is to provide an information processing apparatus including a plurality of buses and a bus controller connected to all of the plurality of buses, wherein the bus controller transmits and receives data between the plurality of buses. Unit, a register for recording a predetermined condition for transaction contents, a transaction monitoring unit for causing a transaction management unit to detect a transaction that satisfies the predetermined condition, and from the transaction monitoring unit When notified that a transaction satisfying a predetermined condition set in advance has been detected, a transaction control unit that controls the execution of a transaction different from the transaction triggered by this notification, and another transaction issued by the transaction control unit Within a transaction When the transaction management unit detects a transaction that satisfies a predetermined condition set in advance, the transaction management unit does not process the detected transaction, and reissues the transaction to the issuer of the transaction. This is achieved by putting the transaction processing in a pending state by repeating the issuance, and notifying the transaction control unit via the transaction monitoring unit that a transaction satisfying a predetermined condition has been detected.

  According to the present invention, in an information processing apparatus having a plurality of buses, when a transaction issued to each bus satisfies a predetermined condition set in advance, the processing of the transaction is temporarily stopped to generate an interrupt. It is possible to execute a transaction for processing such as information processing and debugging of an information processing device with the occurrence of this interrupt as a trigger, and to perform operation analysis and debugging of the information processing device at a flexible timing. it can.

  Embodiments of an information processing apparatus transaction management method and information processing apparatus according to the present invention will be described below in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of an information processing apparatus according to an embodiment of the present invention. As shown in FIG. 1, the information processing apparatus 200 according to the embodiment of the present invention includes a plurality of CPUs 240 and 241 connected to the processor bus 230, a plurality of memories 250 and 251 connected to the memory bus 231, A plurality of I / O devices 290 and 291 connected to the O bus 232 via I / O interfaces 260 and 261, a bus controller 210 that controls the processor bus 230, the memory bus 231, and the I / O bus 233; And a board management controller (BMC) 270.

  The bus controller 210 includes a transaction monitoring unit (Tx monitoring unit) 211, a transaction control unit (Tx control unit) 212, a trigger register (Trig Reg) 213, an execution flag register (Flag Reg) 214, and an address register (Addr). (Reg) 215, a data register (Data Reg) 216, a command register (CMD Reg) 217, an input / output control unit 218, and a transaction management unit (Tx management unit) 100.

  In the above description, the Tx management unit 100 manages all transactions processed in the information processing apparatus 200. In the embodiment of the present invention, the Tx control unit 212 is in the middle of normal transaction processing. In response to an interrupt signal from the Tx monitoring unit 211, another transaction having the contents recorded in the Addr Reg 215, the Data Reg 216, and the CMD Reg 217, for example, a transaction for performing an operation analysis, debugging, etc. of the information processing apparatus is issued. And control. The BMC 270 performs input / output control between the user terminal 280 and the bus controller 210, and the I / O devices 290 and 291 include registers 295 and 296 and DMA controllers 298 and 299, respectively. ing. The memories 250 and 251 include memory controllers 255 and 256, respectively. The memory controller 255 includes a register 258 for setting the operation mode of the memory controller. Similarly, the memory controller 256 is a register for setting the operation mode of the memory controller. 259.

  FIG. 2 is a block diagram showing a configuration of the Tx management unit 100 shown in FIG. As shown in FIG. 2, the Tx management unit 100 includes command control units (CMD control units) 151 to 154 and address control units (Addr control units) 161 to 164 connected to the buses 230 to 232 and the Tx control unit 212. , Data control unit (Data control unit) 171 to 174, address table (Addr Table) 180, command path switch (CMD Path SW) 185 for controlling connection between CMD control units 151 to 154, and Addr control unit An address path switch (Addr Path SW) 186 that controls connection between 161 to 164 and a data path switch (Data Path SW) 187 that controls connection between Data control units 171 to 174 are configured. .

  3A and 3B are flowcharts for explaining the operation of normal transaction processing performed by the information processing apparatus according to the embodiment of the present invention described above. Next, this will be described. An example of the processing described here is an example in which the CPU 240 or 241 or the DMA controller 295 or 296 of the information processing apparatus 200 serves as a bus master and issues a transaction. The transaction processing for performing memory read will be described with reference to FIGS.

(1) First, processing as an arbitration phase is started, and the CPU 240 issues a bus request to use the processor bus 230 and continues issuing the bus request until the bus control right can be acquired (step 301, 302).

(2) After acquiring the bus control right, next, processing as an address phase is started, and the CPU 240 issues a command (memory read) as a transaction to the control bus 111 and addresses the address. It is issued to the bus (Addr Bus) 121 (step 303).

(3) The Addr control unit 161 compares the address used by the preceding transaction recorded in the Addr Table 180 with the address of the transaction issued from the CPU 240 in the process of Step 303, and uses the address of the transaction. It is determined whether it is in the middle (address conflict), and if it is in use, it is reported to the CMD control unit 151. The CMD control unit 151 issues a retry request for issuing a transaction to the control bus 111. As a result, the process returns to step 303, and the CPU 240 retries the transaction (steps 304 and 303).

(4) If it is determined in step 304 that the transaction address is not in use, or if the preceding transaction ends and the address recorded in the Addr Table 180 is erased, the Addr control unit 161 sets the address conflict. After confirming that there is no address, the access address is recorded in the Addr Table 180, and the CMD control unit 151 outputs a signal indicating the completion of command reception to the control bus 111 (step 305).

(5) The Addr control unit 161 determines the connection destination (memory bus 231) from the address value, and the CMD Path SW 185 is a path between the CMD control unit 151 on the processor bus 230 side and the CMD control unit 152 on the memory bus 231 side. The Addr Path SW 186 connects the path between the Addr control unit 161 on the processor bus 230 side and the Addr control unit 162 on the memory bus 231 side (step 306).

(6) The CMD control unit 151 on the processor bus 230 side transmits a command to the CMD control unit 152 on the memory bus 231 side, and the Addr control unit 161 on the processor bus 230 side transmits to the Addr control unit 162 on the memory bus 231 side. The address is transmitted (step 307).

(7) Thereafter, the CMD Path SW 185 disconnects the path between the CMD control unit 151 on the processor bus 230 side and the CMD control unit 152 on the memory bus 231 side, and the Addr Path SW 186 is connected to the Addr control unit 161 on the processor bus 230 side. The path to the Addr control unit 162 on the memory bus 231 side is disconnected (step 308).

(8) Next, the CMD control unit 152 on the memory bus 231 side transmits a command on the control bus 112, and the Addr control unit 162 transmits an address on the Addr Bus 122. As a result, the command and address are sent to the memory 250. With the processing so far, the address phase processing is completed (step 309).

(9) Next, data phase processing is started, and the memory 250 that has received the command transmitted in step 309 from the control bus 112 outputs the content of the address on the Data Bus 132 as data. This data is received by the data control unit 172 (step 310).

(10) Thereafter, the CMD Path SW 185 connects the path between the CMD control unit 151 on the processor bus 230 side and the CMD control unit 152 on the memory bus 231 side, and the Data Path SW 187 is the Data control unit 171 on the processor bus 230 side. Are connected to the data control unit 172 on the memory bus 231 side (step 311).

(11) The data control unit 172 on the memory bus 231 side transmits the data received in step 310 to the data control unit 171 on the processor bus 230 side. Further, the CMD control unit 152 on the memory bus 231 side transmits an end signal to the CMD control unit 151 on the processor bus 230 side (step 312).

(12) The CMD Path SW 185 disconnects the path between the CMD control unit 151 on the processor bus 230 side and the CMD control unit 152 on the memory bus 231 side, and the Data Path SW 187 is connected to the Data control unit 171 on the processor bus 230 side and the memory. The path to the data control unit 172 on the bus 231 side is disconnected (step 313).

(13) The data control unit 171 on the processor bus 230 side receives the data transmitted from the data control unit 172 on the memory bus 231 side in the process of step 312 and transmits it to the data bus 131. This data is received by the CPU 240. With the processing so far, the data phase processing is completed (step 314).

(14) Finally, the transaction end / phase processing is started, and the address control unit 161 on the processor bus 230 side deletes the address recorded in the Addr Table 180 and ends the processing here (step 315).

  4A and 4B temporarily stop the normal transaction processing operation performed by the information processing apparatus according to the embodiment of the present invention described above, and then perform another transaction for analyzing the operation of the information processing apparatus, debugging, and the like. It is a flowchart explaining the process to perform, Next, this is demonstrated. An example of the processing described here is that the CPU 240 described above detects a transaction in which memory read is performed on the memory 250, holds the transaction, and performs memory controller of the memory 250 for analyzing the operation of the information processing apparatus. This is an example in which register write is performed to the register 258 of the memory controller 255 as a transaction for changing the operation mode of 255, which will be described with reference to FIGS.

(1) First, as an interrupt preparation phase, certain conditions are determined for the contents (bus master, command, address, data, etc.) of a transaction to be triggered by an interrupt. This is a trigger condition. The trigger condition in the example described is that the bus master is the CPU 240, the command is the memory read, and the address is the memory read target address. Next, the contents of the transaction for analyzing the operation of the information processing apparatus, debugging, etc., which are executed in response to the interruption are determined. In the example described, since the mode change transaction of the memory controller 255 is performed, the transaction command is register write, the address is the address to be set in the register 258 in the memory controller 255, and the data is the operation mode setting value. When the trigger condition and the content of the mode change transaction are input from the user terminal 280, the BMC 270 that has received the input receives the trigger condition as the Trig Reg 213 and the address of the mode change transaction as the Addr Reg 215 via the input / output control unit 218. In addition, the contents of the write are set in the Data Reg 216, and the command (write to the register 258 in the memory controller 255) and the execution timing (before processing of a normal transaction as a trigger) are set in the CMD Reg 217. Then, the Tx monitoring unit 211 sends the set trigger condition to the Tx management unit 100, and the Tx management unit 100 receiving the trigger condition triggers the CMD control unit 151 and the Addr control unit 161 on the processor bus 230 side. Conditions are set (step 401).

(2) Next, the transaction monitoring phase is started. That is, after starting the system and preparing the test environment, a transaction monitoring command is input from the user terminal 280. The BMC 270 that has received the transaction monitoring command sets the Flag Reg 214 via the input / output control unit 218. Upon receiving the set of Flag Reg 214, the Tx monitoring unit 211 transmits a start signal to the Tx management unit 100. Thereby, the CMD control unit 151 and the Addr control unit 161 in the Tx management unit 100 start monitoring a transaction issued from the CPU 240 to the processor bus 230 (step 402).

(3) The CMD control unit 151 and the Addr control unit 161 continue to monitor a transaction that satisfies the trigger condition, and when detecting a transaction that satisfies the trigger condition, the CMD control unit 151 and the Addr control unit 161 send an interrupt signal to the Tx control unit 212 via the Tx monitoring unit 211. Is transmitted (step 403).

(4) Further, the CMD control unit 151 continues to issue a transaction reissue request to the control bus 111 until the end of the transaction executed in response to an interrupt, which will be described in the processing of the next steps 405 to 420. The received CPU 240 repeatedly issues a transaction, and the transaction processing is put on hold (step 404).

(5) Next, the mode change transaction phase is started, and the address phase is first executed. That is, when the Tx control unit 212 receives a transaction detection interrupt that satisfies the trigger condition from the Tx monitoring unit 211 in the process of step 403, the content of the CMD Reg 217 (of the memory controller 255) is set to the address set in the Addr Reg 215. A bus request is issued in order to execute a transaction (write to the register 258) (step 405).

(6) The Tx control unit 212 determines whether or not the bus control right has been acquired with respect to the issuance of the bus request in step 405. If the bus control right cannot be acquired, the process returns to step 405. Then, the processing for issuing the bus request is continued (step 406).

(7) If the bus control right is acquired in the determination in step 406, the Tx control unit 212 issues a mode change transaction command and an address (step 407).

(8) Next, the Addr control unit 164 on the Tx control unit 212 side compares the address of the mode change transaction fetched from the Tx control unit 212 via the Addr Bus 124 with the contents of the Addr Table 180, resulting in an address conflict. If there is an address conflict, the fact is reported to the CMD control unit 154. The CMD control unit 154 transmits a transaction retry request to the Tx control unit 212. As a result, the process returns to the process from step 407 and the process is continued (step 408).

(9) If it is confirmed in step 408 that there is no address conflict, the Addr control unit 164 records the address to be accessed in the Addr Table 180. Further, the CMD control unit 154 transmits a command reception completion signal to the Tx control unit 212 via the control bus 114 (step 409).

(10) The Addr control unit 164 determines the connection destination (memory bus 231) from the address value. In response to this determination result, the CMD Path SW 185 connects a path between the CMD control unit 154 on the Tx control unit 212 side and the CMD control unit 152 on the memory bus 231 side, and the Addr Path SW 186 is connected to the Tx control unit 212. The path between the Addr control unit 164 on the side and the Addr control unit 162 on the memory bus 231 side is connected (step 410).

(11) Next, the CMD control unit 154 on the Tx control unit 212 side transmits a command to the CMD control unit 152 on the memory bus 231 side, and the Addr control unit 164 on the Tx control unit 212 side transmits the command on the memory bus 231 side. The address is transmitted to the Addr control unit 162 (step 411).

(12) Thereafter, the CMD Path SW 185 disconnects the path between the CMD control unit 154 on the Tx control unit 212 side and the CMD control unit 152 on the memory bus 231 side, and the Addr Path SW 186 is connected to the Tx control unit 212 side. The path between the Addr control unit 164 and the Addr control unit 162 on the memory bus 231 side is disconnected (step 412).

(13) The CMD control unit 152 on the memory bus 231 side transmits a command on the control bus 112, and the Addr control unit 162 transmits an address to the Addr Bus 122. These commands and addresses are transmitted to the memory 250 via the memory bus 231 (step 413).

(14) Next, the process proceeds to the data phase processing of the mode change transaction, and the Tx control unit 212 that has received the command reception completion signal via the control bus 114 in the processing of step 409, the contents of the Data Reg 216 Is output to the Data Bus 134, and the Data control unit 174 receives the data (Step 414).

(15) Thereafter, the Data Path SW 187 connects a path between the Data control unit 174 on the Tx control unit 212 side and the Data control unit 172 on the memory bus 231 side (Step 415).

(16) The data control unit 174 on the Tx control unit 212 side transmits the write content data to the data control unit 172 on the memory bus 231 side (step 416).

(17) Next, the Data Path SW 187 disconnects the path between the Data control unit 174 on the Tx control unit 212 side and the Data control unit 172 on the memory bus 231 side (Step 417).

(18) Then, the data control unit 172 on the memory bus side transmits data to the data bus 132. In step 413, the memory 250 receiving the command via the control bus 112 writes the data received via the data bus 132 to the register 258 of the memory controller 255. As a result, the operation mode of the memory controller 250 is changed (step 418).

(19) Next, the process proceeds to the mode change transaction end / phase process, and the address control unit 161 deletes the address recorded in the Addr Table 180 (step 419).

(20) Thereafter, the Tx control unit 212 reports the end of the mode change transaction processing to the user terminal 280 via the BMC 270, and ends the mode change transaction processing (step 420).

(21) After the processing of the mode change transaction is completed, the CMD control unit 151 on the processor bus 230 side stops the retry request to the CPU 240 and releases the pending state of the transaction (step 421).

(22) The CPU 240 reissues the transaction when the pending state of the transaction is released, and continues normal transaction processing thereafter (step 422).

  In the example of the processing of the present invention described above, an interrupt trigger condition is set for the command and the address, and the CPU memory read is triggered by the interrupt. However, the trigger condition is set for the Data control unit, and the transaction data The contents can also be used as a trigger for interruption.

  The CMD control unit, Addr control unit, and Data control unit connected to each bus have the same functions, and transactions issued by bus masters other than those described (for example, the DMA controller 298 of the I / O device 290). Can be triggered by an interrupt.

  In the above-described processing example of the present invention, the transaction executed in response to the interrupt is targeted for the register 258 of the memory controller 255, but accessible memory and registers in the information processing apparatus 200 other than those described (for example, , Registers 295 and 296 of the I / O devices 290 and 291 and registers in the bus controller 200) can be targeted for transactions.

  In the above-described processing example of the present invention, during the processing of a transaction executed in response to an interrupt, the processing of a normal transaction as a trigger is put on hold, but the timing of execution of the transaction executed in response to an interrupt Can be set after the processing of a normal transaction as a trigger, so that a retry request is not issued to the bus master that issued the normal transaction, and the processing of the transaction that is executed when an interrupt occurs after the processing of the normal transaction It can be performed.

  According to the above-described embodiment of the present invention, in an information processing apparatus including a plurality of buses, a bus controller connected to each bus is provided, and the transaction before the transaction passes from the transaction issuing bus to the issuing bus. Is temporarily suspended, and the transaction issuance source is repeatedly issued, whereby the transaction processing can be put on hold. The above-described embodiment of the present invention can execute another transaction for hardware operation analysis, debugging, and the like inside the apparatus of the information processing apparatus while in the pending state.

  As a result, according to the embodiment of the present invention, before processing a transaction that satisfies the trigger condition, the user performs processing such as reading a register value of a memory or an I / O device. Only the value of the register of the memory or the IO device can be changed, so that the flexibility of the interrupt operation can be improved.

It is a block diagram which shows the structure of the information processing apparatus by one Embodiment of this invention. It is a block diagram which shows the structure of the Tx management part shown in FIG. 6 is a flowchart (part 1) illustrating an operation of normal transaction processing performed by the information processing apparatus. It is a flowchart (the 2) explaining operation | movement of the normal transaction processing which information processing apparatus implements. FIG. 10 is a flowchart (part 1) illustrating a process of temporarily stopping an operation of a normal transaction process performed by the information processing apparatus and executing another transaction for analyzing the operation of the information processing apparatus, debugging, and the like. FIG. 10 is a flowchart (part 2) illustrating a process of temporarily stopping an operation of normal transaction processing performed by the information processing apparatus and executing another transaction for operation analysis, debugging, and the like of the information processing apparatus.

Explanation of symbols

100 Transaction manager (Tx manager)
111 112 113 114 Control bus 121 122 123 124 Address bus (Addr Bus)
131 132 133 134 Data Bus (Data Bus)
151 152 153 154 Command control unit (CMD control unit)
161 162 163 164 Address control unit (Addr control unit)
171 172 173 174 Data control unit (Data control unit)
180 Address table (Addr Table)
185 Command path switch (CMD Path SW)
186 Address path switch (Addr Path SW)
187 Data path switch (Data Path SW)
200 Information processing device 210 Bus controller 212 Transaction control unit (Tx control unit)
213 Trigger register (Taig Reg)
214 Execution flag register (Flag Reg)
215 Address register (Addr Reg)
216 Data Register (Data Reg)
217 Command register (CMD Reg)
218 Input / output control unit 230 Processor bus 231 Memory bus 232 I / O bus 240 241 CPU
250 251 Memory 255, 256 Memory controller 258, 259, 295 296 Register 260 261 I / O interface 270 Board management controller (BMC)
280 User terminal 290 291 I / O interface 298 299 DMA controller

Claims (8)

In a transaction management method for an information processing apparatus comprising a plurality of buses and a bus controller connected to all of the plurality of buses,
The bus controller monitors a transaction to be processed, and when a transaction that satisfies a predetermined condition set in advance is detected, does not process the detected transaction and causes the issuer of the transaction to reissue the transaction repeatedly The transaction processing is put into a pending state, and then processing of a transaction different from the transaction in the pending state is executed. After the processing of another transaction is finished, the pending state of the transaction in the pending state is executed. The transaction management method of the information processing apparatus is characterized in that the transaction is managed so that the released transaction is processed.   2. The transaction management method for an information processing apparatus according to claim 1, wherein the another transaction is a transaction for performing an operation analysis and debugging of hardware inside the information processing apparatus.   3. The transaction management method for an information processing apparatus according to claim 1, wherein the another transaction is executed immediately before processing of the transaction in the pending state.   4. The transaction management method for an information processing apparatus according to claim 1, wherein the predetermined condition is at least one of a bus master, a command, and an address included in the transaction. In an information processing apparatus comprising a plurality of buses and a bus controller connected to all of the plurality of buses,
The bus controller includes a transaction management unit that transmits and receives data between the plurality of buses, a register that records a predetermined condition for a transaction content, and a transaction that satisfies the predetermined condition. A transaction monitoring unit that causes the transaction management unit to detect the transaction and the transaction monitoring unit to detect that a transaction satisfying the predetermined condition is detected. A transaction control unit that controls the execution of the transaction, and a register group that sets the contents of another transaction issued by the transaction control unit,
When the transaction management unit detects a transaction that satisfies a predetermined condition set in advance, the transaction management unit does not process the detected transaction, and causes the transaction issuer to repeat transaction reissuance so that the transaction processing is suspended. And an information processing apparatus that notifies the transaction control unit that a transaction satisfying a predetermined condition is detected via the transaction monitoring unit.   6. The information processing according to claim 5, wherein after the processing of the other transaction is completed, the transaction management unit releases the held state of the transaction that has been put on hold and processes the released transaction. apparatus.   7. The information processing apparatus according to claim 5, wherein the another transaction is a transaction for performing an operation analysis and debugging of hardware inside the information processing apparatus.   The information processing apparatus according to claim 5, wherein the predetermined condition is at least one of a bus master, a command, and an address included in a transaction.

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