JP2008288581A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a consumption current of an input section for a bonding option pad, and to prevent malfunction of a circuit connected to the bonding option pad. <P>SOLUTION: A semiconductor integrated circuit of this invention includes for a pad (11) a first transistor (20g) which activates the pad (11) to a predetermined voltage at the time of power-on operation, and the pad potential is latched by half-latch of an inverter (20b) and a transistor (20e). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having bonding option pins (or pads) having different pad potentials depending on the type of package to be sealed or the operation mode used. More specifically, the present invention relates to a configuration of an input circuit provided corresponding to a bonding option pin in such a semiconductor integrated circuit.

  As semiconductor integrated circuits are highly integrated and highly functional, the number of input / output signals increases, and accordingly, the number of pin terminals for exchanging signals with the outside also increases. In order to increase the number of pins, an FP (flat package) in which pin terminals are arranged all around the pad is used. 11A is a top view of a QFP (quad flat package), FIG. 11B is a front view of the QFP package, and FIG. 11C is a right side view of the QFP package. It is.

  As shown in FIG. 11A, the QFP package has a rectangular shape, and pin terminals P are arranged on four sides thereof. The length of the QFP package in the long side direction is, for example, 20 ± 0.1 mm, and the length in the short side direction is 14 ± 0.1 mm. The length of the external pin terminal P is about 2.0 mm. In FIG. 11A, pin terminals P are arranged along all the long and short sides. In the long side direction, pin terminals of pin numbers # 1 to # 30 and # 51 to # 80 are arranged to face each other, and in the short side, pin terminals of pin numbers # 31 to 50 and # 81 to # 100 are arranged. Opposed to each other.

As shown in FIGS. 11B and 11C, these pin terminals P have a gull wing shape (L- shape ), the pin terminals are taken out from the center of the side surface of the package, and the L-shaped tip ends. The flat portion is approximately the same height as the bottom of the QFP package.

  FIG. 11D shows an enlarged view of the portion 30B shown in FIG. In FIG. 11D, the pin terminal P is taken out from the side surface of the package PK made of sealing resin, and the shape thereof is shaped into a gull wing shape. The bottom portion (flat portion) of the pin terminal P has a very small difference in height from the bottom portion of the package PK. Therefore, the height of the QFP is sufficiently reduced to about 1.6 mm. The flat portion of the pin terminal P is soldered to the wiring of the printed wiring board. This QFP is widely used as a surface mount package.

  This QFP has a pin terminal pitch of, for example, 0.65 mm. However, as the number of pin terminals further increases, the pin terminal pitch (interval between pin terminals) decreases. The pin terminal (lead terminal) is thin and easily deformed. When mounted on a printed wiring board, the pin terminal may be deformed depending on the handling and cannot be properly soldered to the printed wiring board. Misalignment or short circuit between pin terminals or damage). In order to cope with the increase in the number of pin terminals, a ball grid array type (BGA) package (solder ball planar arrangement type package) in which many terminals are arranged without reducing the pitch between the terminals has been used. ing.

  12A is a top view of the ball grid array type package, FIG. 12B is a right side view of the ball grid array type package, and FIG. 12C is a ball grid array type package. FIG.

  As shown in FIG. 12A, on the upper surface of the ball grid array type package, a mold resin MR is formed on a substrate BAS, and the semiconductor integrated circuit is sealed by the mold resin MR. As shown in FIG. 12B, solder balls SB are arranged in alignment on the back surface of the substrate BAS.

  As shown in FIG. 12C, the solder balls SB are arranged in a matrix on the back surface of the substrate BAS. In FIG. 12C, solder balls SB arranged in a matrix composed of the first column to the ninth column and the Ath row to the Uth row are shown as an example.

  In the case of this BGA (ball grid array type) package, the diameter of the solder balls SB is about 0.76 mm, and the pitch between the solder balls SB is about 1.27 mm. The height of the solder ball SB is about 0.60 mm. The height of the package is about 2.06 mm including the solder balls. The shape of the mold resin is about 19.50 mm in the long side direction and about 12.00 mm in the short side.

  In the case of the BGA package, the solder balls SB formed on the back surface of the substrate BAS are electrically connected to solder pads formed on the printed wiring board.

  In the case of this BGA package, the solder balls SB correspond to the pin terminals of the QFP package. Therefore, in the case of the BGA package, the terminal pitch can be made wider than that of the QFP package. Therefore, a large number of pin terminals can be arranged within a limited area, and the package area can be reduced. Further, the solder ball SB is a hard ball when mounted on the board, and the possibility of deformation due to contact is small. In this BGA package, the solder ball SB is electrically connected to a solder pad formed on the printed wiring board (reflow soldering), so that the inductance of the lead terminal (pin terminal) is small.

  However, in this BGA package, moisture absorbed by reflow heating during reflow soldering expands, and the semiconductor integrated circuit chip peels off from the substrate or the mold resin, or the mold resin and / or the substrate cracks. Arise. In the case of the BGA package, if the terminal pitch is made too small, the total number of wirings on the printed wiring board increases and the cost of the mounting board increases. In addition, since a double-sided printed circuit board is used in this BGA package, there are disadvantages such as variations in the height of terminals in the package due to warping of the board, and differences in the contactability of solder balls.

  Therefore, taking advantage of the characteristics of both the QFP package and the BGA package, one semiconductor integrated circuit device is selectively used depending on the application.

  Consider a synchronous burst SRAM (static random access memory) as an example of a semiconductor integrated circuit. This synchronous burst SRAM can continuously write / read data of a predetermined burst length in accordance with an external clock signal.

  FIG. 13 schematically shows an entire configuration of a conventional synchronous burst SRAM. In FIG. 13, a synchronous burst SRAM 100 includes a memory array 102 having a plurality of static memory cells arranged in a matrix, and an address register 104 that takes in an address signal AD in synchronization with an external clock signal CLK. , The least significant 2 bits of the address signal from the address register 104, the burst counter 106 that sequentially changes and outputs in a predetermined sequence, the address advance / ADV, the address status processor / ADSP, and the address status controller / ADSC as clock signals It includes an address control circuit 108 which takes in synchronization with CLK and controls the operation of the address register 104 and burst counter 106 in accordance with the state of these signals.

  Address control circuit 108 causes burst counter 106 to perform a counting operation when address advance / ADV is at L level at the rising edge of clock signal CLK. When one of the address status processor / ADSP and the address status controller / ADSC is at the L level at the rising edge of the clock signal CLK, the address control circuit 108 causes the address register 104 to take in the address signal AD from the outside and the burst counter 106. Then, the burst operation is stopped and the lower 2-bit address signal from the address register 104 is taken in.

  The sequence in which the burst counter 106 changes the fetched address signal bits is determined by the burst mode control MODE. By this burst mode control MODE, the burst counter 106 performs a linear burst operation that sequentially increments the fetched address by one, or performs an interleaved burst operation that sequentially changes upper bits and lower bits in a predetermined sequence. In this synchronous burst SRAM, when the address advance / ADV is at the L level at the rising edge of the clock signal CLK, the burst counter 106 performs a counting operation and changes the address signal. Therefore, the address signal is generated internally without externally supplying the address signal AD to each clock cycle, and the memory cell of the memory array 102 is addressed.

  Synchronous burst SRAM 100 further takes in write enable control / WE and chip select control / CS in synchronization with clock signal CLK, and performs a write control circuit for performing control necessary for the write operation in synchronization with clock signal CLK. 110, under the control of the write control circuit 110, the input register 112 for taking in external data D (DQ) in synchronization with the clock signal CLK at the time of data writing, and the control of the write control circuit 110 Below, a write circuit 114 for writing data applied from input register 112 to an addressed memory cell of memory array 102 is included. The write control circuit 110 also stops the write operation by the output enable / OE.

  Write enable control / WE includes a master byte write / MBW for permitting data writing in byte units, a global write / GW for simultaneously writing to all bits (for example, 32 bits) memory cells, and Byte writes / BW1, / BW2, / BW3, and / BW4 for controlling data writing in byte units are included. At the time of data writing, data writing control (masking) can be performed in units of bytes, and the input register 112 is therefore controlled in units of bytes of internal write data under the control of the write control circuit 110. Transfer with.

  Synchronous burst SRAM 100 further reads and latches data in output control circuit 118 that generates an output control signal in accordance with output enable / OE and the output signal of write control circuit 110, and data in a selected memory cell in memory array 102. Under the control of the output register 116 and the output control circuit 118, an output buffer 120 for sequentially outputting latch data of the output register 116 to the outside is included.

  When the output enable / OE becomes an active L level, the write control circuit 110 stops the write control operation and enables the output control circuit 118 in the next cycle. In this enable state, output control circuit 118 changes output buffer 120 from output high impedance state to output low impedance state in accordance with output enable / OE, and sequentially outputs read data from output register 116 to the outside. Output register 116 transmits read data to output buffer 120 in a pipeline manner according to clock signal CLK in accordance with follow-through / FT, or data read from memory array 102 ignoring clock signal CLK in a non-pipeline manner. Is transferred to the output buffer 120 as it is. Snooze mode control ZZ is given to each circuit, and when activated, the operation of each circuit is stopped to reduce current consumption.

  Synchronous burst SRAM 100 also receives power supply voltages VDD and VSS as operation power supply voltages of the internal circuit, and receives voltages VDDQ and VSSQ as operation power supply voltages of the input / output buffer circuit. By providing the power supply voltages VDDQ and VSSQ for the input / output buffer circuit separately from the power supply voltages VDD and VSS for operating the internal circuit, even if the power supply voltages VDDQ and VSSQ vary during the input / output buffer operation, the power supply voltages This prevents the fluctuation (power bump) from adversely affecting the internal circuit operation. In addition, the input / output circuit operates stably. The voltage VDDQ is about 1.8V, while the voltage VDD is about 3.3V, and signals are transmitted at high speed on the board.

  Also in such a synchronous burst SRAM, according to the request of a user who constructs a system or an electronic device using the synchronous burst SRAM, as a package, a QFP package which is a representative of a flat package, and a BGA In some cases, the package is sealed in a solder ball planar arrangement package in which solder balls are bonded in an array on the back surface of the package, as represented by the package. In order to be able to use both of these QFP packages and BGA packages, a pin arrangement for both packages has been proposed in JEDEC (Joint Electron Device Engineering Council).

  FIG. 14 is a diagram showing signal assignment to each pin terminal in the QFP package. FIG. 14 shows the pin arrangement of a 32K / 36-bit synchronous burst SRAM. In FIG. 14, data input / output bit DQ, follow-through control FT # (/ FT), power supply voltages Vddq, Vssq, Vdd, and Vss are assigned to the portion where pin terminals 1 to 30 are arranged. The reason why the pin terminal receiving the power supply voltage is arranged between the pin terminals receiving the data bits is to supply the power supply voltage to these data input / output buffer circuits stably. Follow-through control FT # (/ FT) is given to the pin terminal of pin number 14.

  In the pin terminals of pin number 31 to pin number 50, a burst mode control LBO # (MODE) for setting the count sequence of the burst counter and an address signal AD (SA, SA1, SA0) are assigned.

  Data DQ and power supply voltages Vddq, Vssq, Vdd, and Vss are assigned to the pin terminals of pin number 51 to pin number 80. The assignment of the signals assigned to the pin terminals of pin number 51 to pin number 80 is the same as the signal assigned to the pin terminals of pin number 1 to pin number 30 arranged opposite to each other. Snooze mode control ZZ is given to the pin terminal of pin number 64. The snooze mode control ZZ significantly reduces current consumption by stopping all internal circuit operations. In the configuration of the burst SRAM shown in FIG. 13, a snooze mode control ZZ is given to each circuit, and its output signal level is fixed.

  An address signal AD and each control signal are assigned to the pin terminals of the pin numbers 81 to 100. Signals SE1 #, SE2, and SE3 # are chip select / CS, signals SBWd #, SBWc #, SBWb #, SBWa #, SGW #, SBWE # are write enable controls / WE, and signal G # is Corresponds to output enable / OE. The signal CK corresponds to the clock signal CLK.

  Signal SAC # corresponds to address status control / ADSC, signal SAP # corresponds to address status processor / ADSP, and signal SADV # corresponds to address advance control / ADV.

  By arranging the data input / output pins on both sides of the package and arranging the address signal AD and the control signal on opposite sides, the configuration of the memory array is made symmetrical and the internal layout is simplified.

  FIG. 15 is a diagram illustrating assignment of signals to solder balls (bumps) in a BGA package. In FIG. 15, in this BGA package, solder balls (bumps) are arranged in 17 rows (A row to U row) and 7 columns, and a signal is assigned to each. The first column is assigned data and power supply voltage, the second column is assigned address and data, the third column is assigned control signal, power supply voltage and address signal bit, and the fourth column is assigned. Are assigned control signals and power supply voltages, control signals and address signal bits are also assigned in the fifth column, data and address signals are assigned in the sixth column, and data bits and power supply voltages are assigned in the seventh column. It is done. The name (symbol) of each signal is the same as that shown in FIG.

  14 and 15, the symbol NC means “no connection”, and this pin terminal indicates that no wiring connection is made even when the board is mounted.

  In the allocation shown in FIG. 15, signals TMS, TDI, TCK, TDO and TRST are allocated in the U-th row. These are a control signal, a test clock signal, and a test data signal used in the boundary scan test circuit. Hereinafter, this boundary scan test and the reason why these signals / data are allocated in the BGA package will be described.

  FIG. 16 is a diagram schematically showing a configuration of a board constituted by chips that are test-designed according to the boundary scan design. In FIG. 16, a plurality (four in FIG. 16) of semiconductor chips 152a, 152b, 152c and 152d are arranged on a board (printed wiring board) 150. These chips 152a to 152d may be semiconductor integrated circuit devices that realize the same logic function, or may be semiconductor integrated circuits that realize the same function, such as a semiconductor memory device. A chip 152 (chips 152a to 152d are generically shown) has input / output terminals 154 (terminals 154a to 154d are generically shown) for inputting or outputting data to be processed or processed in a normal operation. Boundary scan register (BSR) 155 (generally showing boundary scan registers 155a to 155d) having at least a function of transmitting test data, and internal logic 153 (internal logic 153a to 153d) for executing a desired logical operation For example, the synchronous burst SRAM shown in FIG. 13 corresponds to this).

  The boundary scan register 155 is provided corresponding to each data input / output terminal (pad) 154. That is, a boundary scan register 155 is provided corresponding to each input / output buffer. The boundary scan register 155 is connected in series so as to form a serial data shift path in one chip. The boundary scan registers of each chip are serially connected via a shift path 156. Thus, on the board 150, the boundary scan register 155 of the chips 152a to 152d forms one serial test data transfer path.

  The input / output terminals 154a, 154b, 154c and 154d of the chips 152a to 152d are interconnected via a system signal line 157. On this system signal line 157, a data signal to be processed or processed in the normal operation is propagated.

  On board 150, a board input / output terminal area (edge connector) for transmitting data between chip 152 of board 150 and a device external to board 150 (a chip on another board or a test device). 158 is provided. The edge connector 158 outputs input / output terminals 158a, 158b and 158c for inputting / outputting processing data SD during a normal operation at the board level, a scan-in terminal 159 for receiving test data TDI, and test data TDO. The scan-out terminal 160 is included. Test data TDI applied to the scan-in terminal 159 is serially propagated through a scan path composed of boundary scan registers 155 formed in each of the chips 152a to 152d. The scanned-in test data TDI is sequentially propagated through the boundary lease campus, and is set in a desired boundary scan register 155.

  The scan-out terminal 160 serially receives test data TDO transmitted through a scan path formed by a boundary scan register 155 formed in the chips 152a to 152d on the board 150. This test data TDO can be read from an arbitrary boundary scan register 155.

  The boundary scan register 155 is provided corresponding to each input / output terminal 154, shifts the applied test data, and latches the data from the internal logic 153 or the data applied to the input / output terminal 154. It also has a latching function.

  A clock signal for controlling the shift operation of the boundary scan register 155 is given by a test clock signal TCK that is different from the system clock for operating the chips 152a to 152d on the board 150. Further, since the propagation path of test data is separated from the propagation path of system data (memory write / read data and control signals and address signals), boundary scan register 155 operates in internal logic 153. The processing data of the internal logic 153 can be taken in without adverse effects.

  As shown in FIG. 16, a boundary scan register is provided in each chip, and the boundary scan register in the chip is interconnected between the chips to form a data transfer path, thereby forming an edge connector of the board 150. A specific chip 152 provided on the board 150 can be accessed directly from 158. Thus, a desired chip 152 on the board 150 can be tested without using an expensive in-circuit tester. Moreover, even in the case of a chip that makes it difficult to bring a test probe into contact with the chip terminal, such as a surface mount component, the test can be easily executed.

  Boundary scan test methods using such a boundary scan register include an internal test, an external test, and a sample mode. In the internal test, desired data is set to the boundary scan register via the scan path, the internal logic is operated, and it is determined whether or not the internal logic is operating normally. In the external test, wiring between chips (wiring on the board 150, system signal line 157) is tested. In the case of this external test, test data for connection confirmation is propagated through the shift path 156 and held in the boundary scan register 155 connected to the output terminal of the chip 152. This test data for connection confirmation is then applied to the corresponding output terminal. The test data given to the output terminal is taken into a boundary scan register connected to the input terminal of another chip. The data captured in the boundary scan register is propagated to the shift path 156 and output from the scan-out terminal 160. By observing this output data TDO, it is confirmed whether or not the wiring connection of the system signal line 157 between the chips is normal. By this external test, it is possible to perform a test for opening and short-circuiting of the inter-chip wiring due to disconnection of the inter-chip wiring and poor soldering between the chip and the board.

  For example, in FIG. 16, in the chips 152a, 152b, 152c and 152d, the boundary scan register 155c of the chip 152c is a boundary scan register connected to the output terminal, and the boundary scan register 155a of the chip 152a and the chip 152d Suppose that the boundary scan register 155d is a boundary scan register connected to an input terminal. In this case, the signal from the output terminal corresponding to boundary scan register 155c is applied to the input terminals corresponding to boundary scan registers 155a and 155d via system signal line 157.

  An operation for testing the connection between the boundary scan register 155c and the boundary scan registers 155a and 155d will be briefly described. First, test data for connection confirmation is propagated to the boundary scan register 155c via the shift path 156 and held there. The test data for connection confirmation held in the boundary scan register 155c is then transmitted to the boundary scan registers 155a and 155d of the chips 152a and 152d via the corresponding output terminals of the chip 152c, and held there. The

  The test data for connection confirmation taken in the boundary scan registers 155a and 155d is output from the scan-out terminal 160 via the shift path 156. By observing the data TDO output from the scan-out terminal 160, the connection of the signal line 157 between the chips 152a and 152d and the chip 152c is confirmed. This operation is performed for input / output terminals between the interfaced chips. By this test, it is possible to execute a test of an interchip wiring defect due to disconnection of the interchip wiring and a soldering defect between the chip and the board, that is, an open and short circuit test.

  For the boundary scan test as described above, a standard has been proposed by JTAG (Joint Test Action Group).

  In the BGA package, as shown in FIG. 12, the solder balls are arranged at the bottom of the package, and the joint between the solder and the wiring of the printed wiring board cannot be seen. Further, the BGA package is a surface-mount type package, and the pin (probe) of the in-circuit tester cannot be applied. In the case of the QFP package, as shown in FIG. 13A, since the pin terminals are arranged on the surface of the printed wiring board even in the surface mount package, the solder joint portion can be visually observed. Therefore, even when the electrical characteristics test is passed in a state where the lead terminal is merely on the solder and no joint is formed, such an appearance inspection of the solder joint is performed. It is possible to find a bonding failure. In the case of the BGA package, since the terminal is on the bottom surface of the package and visual inspection of the joint portion cannot be performed visually, a boundary scan test circuit according to the scan design method as described above is provided in the semiconductor integrated circuit. Provide. After mounting on the printed wiring board of the BGA package, this boundary scan test is performed to inspect the short circuit / opening of each wiring to ensure the reliability of the memory system after mounting.

  As described above, in the synchronous burst SRAM, it is necessary to make the boundary scan test executable when sealing in the BGA package, while in the case of sealing the QFP package, the boundary scan test is required. No testing is required. Changing the internal configuration of the synchronous burst SRAM having the same function in accordance with the type of the sealed package deteriorates design efficiency and manufacturing efficiency. Therefore, regardless of the package type to be sealed, a boundary scan test circuit is formed, and a pad for the test circuit and a corresponding pin terminal are selectively connected in accordance with the package type in the bonding process. Thereby, the synchronous burst SRAM having the same function can form a product having the same function in the same process by changing only the bonding in the bonding process, and the production efficiency and the design efficiency are improved.

  FIG. 17 schematically shows an entire configuration of a conventional synchronous burst SRAM with a built-in test circuit. In FIG. 17, this synchronous burst SRAM includes input / output buffer groups 160 arranged in the periphery, and boundary scan registers provided corresponding to the input buffers and output buffers included in the input / output buffer group 160, respectively. And a boundary scan register group 165 that forms a serial transfer path, a test control circuit 167 that performs control for performing a boundary scan test, and an internal circuit 169 that performs a predetermined function.

  The test control circuit 167 sequentially transfers the test input data TDI to the boundary scan register group 165 according to the test mode select signal TMS, the test mode reset signal TRST, and the test clock signal TCK given from the outside through the input / output buffer group. The test specified by the test mode select signal TMS is performed. The test result data TDO held in the registers included in the boundary scan register group 165 are sequentially output by the shift operation of the boundary scan register group 165 under the control of the test control circuit 167. Internal circuit 169 includes the circuit configuration shown in FIG.

  The boundary scan test circuit configured by the boundary scan register group 165 and the test control circuit 167 is not coupled to an external terminal because a pin terminal is not assigned when sealed in a QFP package. In other words, pads provided for signals TMS, TRST, and TCK and data TDI and TDO are not connected to the external pin terminals. Therefore, at the time of sealing in the QFP package, it is necessary that the unused boundary scan test circuit does not cause a malfunction or does not consume extra current.

  In addition, although pin terminals are assigned regardless of the package type, the connection between the pin terminals and the corresponding internal pads by bonding wires is selectively performed, or signals corresponding to the fixed potentials of the corresponding pin terminals are different. is there. An operation mode performed internally is determined by selectively connecting or selectively setting a pad potential in the step of bonding a pin terminal to a corresponding pad. Such a pad is hereinafter referred to as a bonding option pad.

  FIG. 18 is a diagram illustrating an example of signals related to the bonding option pad. In FIG. 18, three control signals, follow-through signal / FT (FT #), burst mode signal MODE (LBO #), and snooze mode signal ZZ are shown. When the pad corresponding to follow-through signal / FT (FT #) is set to the H level or the NC state, a normal mode (pipeline operation mode) in which data output is performed in synchronization with clock signal CLK is set. . On the other hand, when follow-through signal / FT (FT #) is fixed at L level, follow-through mode (non-pipeline) is entered, the clock synchronization operation of the output register is stopped, and data is output statically. Here, the NC state indicates a state where the bonding wire is not connected to the pad and the corresponding pin terminal or the pin terminal is not connected to the wiring.

  Burst mode signal MODE (LBO #) designates the interleaved burst mode when the corresponding pad is set to the H level or the NC state, and designates the linear burst mode when the pad is fixed at the L level. In the interleaved burst mode, in the burst counter 106 shown in FIG. 13, the address signal (A1, A0) is changed from (A1, A0) → (A1, / A0) → (/ A1, A0) → (/ A1, / It changes cyclically in the order of A0). On the other hand, in the linear burst mode, the address bits (A1, A0) are cyclically selected first in the order of (0, 0) → (0, 1) → (1, 0) → (1, 1). It changes according to the value of the address bit inserted. These follow-through signal / FT (FT #) and burst mode signal MODE (LBO #) have their pad potential fixed at the time of package mounting or board mounting, and their states are changed during normal operation. Absent.

  On the other hand, for snooze mode signal ZZ, the normal operation mode state is set when the corresponding pad is at the L level or the NC state, while the snooze mode is specified when the corresponding pad is set at the H level. In the normal operation mode, access is performed in accordance with an external clock signal CLK. On the other hand, when the snooze mode is set, the input / output buffer does not operate and the state of the internal circuit does not change regardless of the external application of the clock signal CLK. When the snooze mode is set, the internal circuit does not operate and the potential level of the internal signal does not change, so that a state with extremely small power supply current is set. In the case of the snooze mode signal ZZ, the synchronous burst SRAM capable of operating the snooze mode and the synchronous burst SRAM incapable of performing the snooze mode operation are set depending on the presence / absence of bonding to this pad.

  In general, in a semiconductor integrated circuit having only a necessary function among a plurality of functions, all these functions are implemented in the integrated circuit, and only necessary functions are set by the presence / absence of bonding / wiring. The manufacturing process is simplified, the delivery time is shortened, and the design efficiency is improved. Such a bonding option pad is in a floating state or bonded to a power supply line / ground line. In this case, even if the floating state (NC state) is set, the internal signal state needs to be set to a predetermined voltage level.

  FIG. 19 is a diagram illustrating an example of the configuration of the input unit of the bonding option pad. In FIG. 19, an input protection circuit including diodes D1 and D2 and a buffer circuit Bufa for buffering the signal potential on pad PDa are provided for pad PDa. Diode D1 has an anode connected to pad PDa and a cathode connected to a power supply node receiving power supply voltage VDD. Diode D2 has a cathode connected to pad PDa and an anode connected to the ground node. A pull-up resistor R1 is further provided for the pad PDa. The pull-up resistor R1 pulls up the potential of the input portion of the buffer Bufa to the power supply voltage VDD level.

  Pad PDa is selectively connected to corresponding pin terminal PTa by bonding wire BWa. Signal φph applied to pin terminal PTa is burst mode signal LBO # (MODE) or follow-through signal FT # (/ FT) in the example shown in FIG. When the bonding wire BWa is not provided or the pin terminal is in the NC state, the potential of the input portion of the buffer Bufa is set to the power supply voltage VDD level by the pull-up resistor R1. On the other hand, when the pad PDa and the pin terminal PTa are connected by the bonding wire BWa, if the signal φph is at the H level, no current flows through the pad PDa.

  However, when this signal φph is set at L level, current i flows from pull-up resistor R1 to ground of pin terminal PTa via pad PDa and bonding wire BWa. Signal φph is burst mode signal LBO # or follow-through signal FT #, and is set to either H level or L level. Therefore, when the pin terminal PTa is set to a logic level opposite to the logic set by the pull-up resistor R1, there arises a problem that current flows from the pull-up resistor R1 and current consumption increases. In particular, in the standby state, even when the resistance value of the pull-up resistor R1 is sufficiently large, the size cannot be ignored.

  FIG. 20 is a diagram illustrating another configuration of the input unit for the bonding option pad. In FIG. 20, an input protection circuit composed of diodes D3 and D4 and a buffer Bufb are provided for pad PDb. Diode D3 is connected in the forward direction from pad PDb to the power supply node, while diode D4 is connected in the reverse direction from pad PDb to the ground node. A pull-down resistor R2 having a relatively large resistance value is provided at the input portion of the buffer Bufb.

  Pad PDb is selectively connected to corresponding pin terminal PTb via bonding wire BWb. Signal φpl applied to pin terminal PTb is, for example, snooze mode signal ZZ. When the bonding wire BWb is not provided and the pin terminal PTb and the pad PDb are disconnected or when the pin terminal is in the NC state, the potential of the pad PDb is held at the ground voltage level by the pull-down resistor R2. On the other hand, when pin terminal PTb and pad PDb are interconnected by bonding wire BWb, if signal φpl is at L level, no current flows through pad PDb, bonding wire BWb and pin terminal PTb. On the other hand, when signal φpl is set to H level, a current flows from pin terminal PTb through bonding wire BWb, pad PDb, and pull-down resistor R2. When the signal φpl is the snooze mode signal ZZ, the device can operate in the snooze mode when the pad PDb and the pin terminal PTb are connected by the bonding wire BWb. When the snooze mode is set, the snooze mode signal ZZ is set to the H level. Therefore, in the snooze mode, current flows from the pin terminal PTb via the pad PDb and the resistor R2, and current is unnecessarily consumed in the snooze mode for realizing low current consumption, thereby reducing current consumption. The problem that it becomes impossible to occur.

  The above-described problem generally becomes a problem when the function of the internal circuit is set by the presence or absence of pad bonding.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that does not increase the current consumption of a circuit provided for a bonding option pad.

  Another object of the present invention is to provide a semiconductor integrated circuit in which an input circuit provided for a bonding option pad does not malfunction.

Still another object of the present invention is to provide a semiconductor integrated circuit in which a boundary scan test circuit that is selectively used according to a package to be sealed does not malfunction even when it is not used (when pins are not connected). Is to provide.

  A specific object of the present invention is to provide a semiconductor integrated circuit including a boundary scan test circuit in which current consumption is reduced without malfunctioning when not in use (when pin terminals are not connected).

  Still another specific object of the present invention is to provide a synchronous burst SRAM incorporating a boundary scan test circuit with low current consumption and no malfunction.

A semiconductor integrated circuit according to the present invention includes a pad, a first transistor that sets the pad to a voltage level of a first logic level in response to a power-on detection signal, and an inverter that inverts the logic of the potential of the pad And a second transistor provided in parallel with the first transistor and receiving the output signal of the inverter at the control electrode node. The operation mode of the internal circuit is set by the output signal of the inverter.

Preferably, the semiconductor integrated circuit further includes a transfer gate interposed between the pad and the input portion of the inverter and receiving a fixed potential at its control electrode node.

The path head potential, is set to a predetermined potential level when the power is turned on, by latching the potential of the pad between the inverter and the second transistor, it is possible to set the pad potential fixedly, with low current consumption The pad potential can be stably maintained. Also, since no pull-up or pull-down resistor is used, even when this pad is connected to the pin terminal, the current flow path is cut off regardless of the pin terminal potential, reducing current consumption. Can do.

That is, even if this pad is a bonding option pad, the internal operation mode can be designated accurately according to the potential of this pad without increasing the current consumption.

If a transfer gate is provided, the pad potential can be set to a voltage level higher than the control electrode node potential of the transfer gate, and the fixed voltage level of the pad can be set to a plurality of types of voltage levels. Therefore, the wiring layout when the semiconductor integrated circuit is mounted on the board is simplified, and the degree of freedom in board design is increased.

[Embodiment 1]
FIG. 1 schematically shows an overall configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. 1, a semiconductor integrated circuit 1 includes a memory internal circuit 2 that performs data input / output in synchronization with a clock signal CLK, and a boundary for testing an electrical connection between the pin terminals of the semiconductor integrated circuit 1. A scan test circuit 3, a control circuit 4 that sets the boundary scan test circuit 3 to an operable / inoperable state, and a power-on detection circuit 5 that detects the power-on voltage VDD and outputs a power-on detection signal POR. Including.

  In operation, boundary scan test circuit 3 performs a test operation in accordance with input signal JTG applied to pad 6a. The control circuit 4 selectively sets the boundary scan test circuit 3 to the operable / inoperable state according to the potential of the pad 6b. The pads 6a to 6c are bonding option pads, and bonding wires are selectively connected according to a package to be sealed or an internal operation function mode. Here, the bonding option pad includes a pad in which bonding between the pad and the pin terminal is selectively performed and a pad in which wiring to the corresponding pin terminal is selectively performed, and indicates a pad whose potential is programmable. .

  Memory internal circuit 2 has a configuration similar to that shown in FIG. 13, takes in external signals (control signal, address signal, and write data) in synchronization with clock signal CLK, and data in synchronization with clock signal CLK. Is output. The memory internal circuit 2 can operate in the burst mode and can be set to the follow-through mode.

Boundary scan test circuit 3 generates an internal signal by buffering scan register group 3a having a scan register provided corresponding to each input / output buffer of semiconductor integrated circuit 1 and signal JTG applied to pad 6a. And a test control circuit 3c for controlling the operation of the scan register group 3a in accordance with a signal supplied from the input circuit 3b and performing a boundary scan test. Scan register group 3a includes scan registers provided corresponding to the input / output buffers (input buffer, output buffer, and input / output buffer) of semiconductor integrated circuit 1, and serially transfers signals (data). It forms a serial path, to the simplification of the drawing in FIG. 1, in one block, indicates the scan register group 3a.

  In response to the potential on the pad 6b, the control circuit 4 responds to the function setting circuit 4a for setting the boundary scan test circuit 3 to an operable or inoperable state and the signal potential on the pad 6c. The mode setting circuit 4b for setting the operation mode of the memory internal circuit 2, the output signal / OBi of the function setting circuit 4a and the output signal ZZi of the mode setting circuit 4b are received, and the input circuit 3b of the boundary scan test circuit 3 A control circuit 4c for setting enable / disable (operable / inoperable) is included. Mode setting circuit 4b specifies one of the snooze mode and the normal operation mode according to the signal potential on pad 6c. The reason why the boundary scan test circuit 3 is enabled / disabled by giving the control gate 4c with the snooze mode instruction signal ZZi from the mode setting circuit 4b is that the boundary scan test circuit 3 is operable. This is to reduce the current consumption by disabling the input circuit 3b in the snooze mode.

  Pads 6a-6c receive external signals JTG, OB and ZZ when connected to the corresponding pin terminals. Signal JTG applied to pad 6a is a signal defined in the JTAG boundary scan test standard, and includes test clock signal TCK, test input data TDI, test mode select signal TMS, test mode reset signal TRST, and test output data. Includes TDO. An input circuit shown in FIG. 1 is provided for each signal. The test input data TDI is given to the test control circuit 3c via the input circuit 3b, and is given to the scan register group 3a according to the test clock signal TCLK and sequentially transferred under the control of the test control circuit 3c.

  As shown in FIG. 1, the boundary scan test circuit 3 is set to an operable / disabled state based on the output signal of the function setting circuit 4a, and the output signal level of the input circuit 3b is fixed in the disabled state. By doing so, no malfunction occurs and the current consumption is reduced (since the potential is fixed, no switching operation is performed and no current is consumed). Further, when the boundary scan test circuit 3 is set to an operable state, the current consumption in the snooze mode is reduced by stopping the operation of the input circuit 3b through the control gate 4c in accordance with the snooze mode instruction signal ZZi. In addition, the boundary scan test can be executed accurately in the normal operation mode. In this way, it is possible to prevent malfunction when the boundary scan test circuit is in an inoperable state and reduce current consumption.

  When power is turned on, the power-on detection circuit 5 outputs a power-on detection signal POR to initialize each internal node of the semiconductor integrated circuit to a predetermined potential level. Next, the configuration of each unit will be described.

  FIG. 2 is a diagram showing a configuration of one scan register included in the scan register group 3a. In FIG. 2, one scan register 3aa is provided for an input / output buffer 2a included in the memory internal circuit 2. The input / output buffer 2a is any one of an input buffer, an output buffer, and an input / output buffer. In the case of an input / output buffer configuration, two input registers and an output register are provided as scan registers. The scan register 3aa is connected in series with a scan register (not shown) so as to form a serial transfer path in order to enable serial transfer of signals (data). During normal operation, scan register 3aa is set to the through state, and input / output buffer 2a exchanges signals / data with the internal circuit (see FIG. 3) via scan register 3aa.

  The specific configuration of the scan register 3aa is arbitrary. In the test mode, signals / data can be transferred serially. In the normal operation mode, between the input / output buffer circuit and the corresponding internal circuit. Any configuration may be used as long as it is set to a through state in which a signal is transferred.

  FIG. 3 is a diagram showing a configuration of function setting circuit 4a shown in FIG. In FIG. 3, the function setting circuit 4a includes an input protection circuit 4aa for preventing an excessive voltage applied to the pad 6b from being transmitted to the inside, an inverter 4ab for inverting the signal potential on the pad 6b, an inverter Inverter 4ac that inverts the output signal of 4ab, and in accordance with the output signals of inverters 4ab and 4ac, the voltage level of the output signal of inverter 4ab is changed from power supply voltage VDDq (= 1.8V) to internal power supply voltage VDD (= 3.3V). ) The level conversion circuit 4ad for converting to the level, the n-channel MOS transistor 4ae which is turned on when the power-on detection signal POR is activated, and initially sets the input node 4ai of the inverter 4ab to the ground potential level, and the output signal of the inverter 4ab Conductive when H level, input node 4ai of inverter 4ab is grounded And an n channel MOS transistor 4af discharging the bell.

  The power supply voltage VDDq is one operating power supply voltage of the input / output buffer circuit, and the power supply voltage VDD is an internal power supply voltage of the synchronous burst SRAM. In the processing system using this synchronous burst SRAM, the signal voltage of the wiring on the board is 1.8 V level, and the signal is propagated at high speed. On the other hand, by using the power supply voltage VDD (= 3.3 V) as the internal power supply voltage, the memory internal circuit is operated at high speed.

  Input protection circuit 4aa includes a diode Da connected between pad 6b and a node receiving power supply voltage VDD, and a diode Db connected between pad 6b and a ground node. Diode Da is connected in the forward direction from pad 6b to the power supply node, and diode Db is connected in the forward direction from the ground node toward pad 6b. The diode Da becomes conductive when the voltage applied to the pad 6b becomes 3.3V + Vf or more, while the diode Db becomes conductive when the voltage of the pad 6b becomes −Vf. Here, Vf is the forward voltage drop of the diodes Da and Db. Normally, when the pad 6b is connected to an external pin terminal, only a voltage of about 1.8V is applied. However, the input protection circuit 4aa can pass up to a voltage of about 3.3V. Therefore, even when a high voltage is applied, the input protection circuit 4aa is not bypassed in the forward direction, so that no current continues to flow from the input pin terminal via the input protection circuit 4a. Therefore, even if a large voltage is generated in the pad 6b due to noise or the like, if the voltage on the pad 6b is 3.3 V or less, no current flows in the input protection circuit 4aa and the current consumption is reduced. Is reduced. Further, when an H level signal is applied from the outside when the mode is fixed, a voltage of 3.3 V or 1.8 V can be applied, and both the power supply VDD and VDDq can be used, increasing the degree of freedom in board design.

  Inverter 4ab is connected between a node receiving power supply voltage VDDq (= 1.8V) and an output node, and has p-channel MOS transistor PQ1 whose gate is coupled to pad 6b, and input node coupled to pad 6b. N channel MOS transistor NQ2 receiving the signal on 4ai at its gate and having one conduction node connected to the ground node, and n channel connected between the output node and MOS transistor NQ2 and receiving power supply voltage VDDq at its gate MOS transistor NQ1 is included. MOS transistor NQ1 has a gate potential of power supply voltage VDDq (= 1.8V), operates in a resistance mode, and functions as a current limiting element that limits the flow of a large current in inverter 4ab.

  Inverter 4ac includes a p-channel MOS transistor PQ2 and an n-channel MOS transistor NQ3 connected between a power supply node receiving power supply voltage VDDq and a ground node. The gates of MOS transistors PQ2 and NQ3 are coupled to the output node of inverter 4ab.

  Level conversion circuit 4ad is connected between node 4aj and a ground node and has an n-channel MOS transistor NQ4 receiving the output signal of inverter 4ab at its gate, and connected between node 4ak and ground node and connected at its gate to inverter 4ac. N-channel MOS transistor NQ5 receiving the output signal, p-channel MOS transistor PQ3 connected between power supply node receiving power supply voltage VDD and node 4aj and having its gate connected to node 4ak, and node receiving power supply voltage VDD And a node 4ak, and includes a p-channel MOS transistor PQ4 having a gate connected to node 4aj.

  When the output signal of inverter 4ab is at H level, MOS transistor NQ4 is turned on, MOS transistor NQ5 is turned off, and node 4aj is discharged to ground potential level through MOS transistor NQ4. In response to the potential drop of node 4aj, the conductance of p channel MOS transistor PQ4 increases, and node 4ak is charged to the level of power supply voltage VDD. As the potential of node 4ak rises, the conductance of MOS transistor PQ3 becomes smaller, and the fall of node 4aj to the ground potential level and the rise of node 4ak to the power supply voltage VDD level are performed at high speed. Finally, the node 4ak becomes the power supply voltage VDD level, and the node 4aj becomes the ground voltage level. Internal function setting signal / OBi is generated from node 4ak.

  On the other hand, when the output signal of inverter 4ab is at L level, MOS transistor NQ4 is turned off, MOS transistor NQ5 is turned on, node 4ak is at L level of the ground voltage level, and node 4aj is at H level of power supply voltage VDD level. . Therefore, this level conversion circuit 4ad converts the H level of the voltage VDDq level of the output signal of the inverter 4ab into the H level of the internal power supply voltage VDD (= 3.3V) level, and generates the internal function setting signal / OBi. To do.

  As a result, the internal circuit that operates using the power supply voltage VDD as one operating power supply voltage can be accurately operated (herein, the internal circuit includes the memory internal circuit and the control gate 4c). This level conversion circuit 4ad is a latch circuit composed of p-channel MOS transistors PQ3 and PQ4. Therefore, after nodes 4aj and 4ak reach H level (power supply voltage VDD level) and L level (ground voltage level), the voltage levels of nodes 4aj and 4ak are latched by MOS transistors PQ3 and PQ4, and pass through. The path through which current flows is interrupted, and current consumption is reduced. Next, the operation of the function setting circuit 4a shown in FIG. 3 will be described.

(I) When sealing the BGA package:
When sealed in a BGA package, the boundary scan test circuit of the synchronous burst SRAM must be set to an operable state, and the pad 6a that receives the signal JTG related to the boundary scan test is Connected to the pin terminal. In this case, the pad 6b is bonded so that the potential thereof is at the H level. When the signal OB of the pad 6b is set to H level (this H level may be either the power supply voltage VDD or VDDq), the output level of the inverter 4ab becomes L level and is output from the level conversion circuit 4ad. The internal function setting signal / OBi to be set becomes L level. The MOS transistor 4af is turned off by the L level signal from the inverter 4ab. The MOS transistor 4ae is only turned on for a predetermined period when the power is turned on according to the power-on detection signal POR. Therefore, even if pad 6b is fixed at the H level potential, only a very short current flows through MOS transistor 4ae after power-on. When the power-on detection signal POR falls to the L level, the MOS transistor 4ae is turned off, the current path for the pad 6b is cut off, and no current is consumed.

(Ii) When sealing the QFP package:
When the QFP package is sealed, the boundary scan test circuit 3 shown in FIG. 1 is not used. Further, the pad 6a provided for the input circuit 3b is not connected to the external pin terminal. In this case, the pad 6b is not bonded and is in the NC state or bonded so as to be fixed at the L level. When fixed to L level, the output signal of inverter 4ab becomes H level, and internal function setting signal / OBi from level conversion circuit 4ad also becomes H level of power supply voltage VDD level. When the output signal of inverter 4ab becomes H level, MOS transistor 4af is turned on, and input node 4ai of inverter 4ab is held at the ground voltage level. Therefore, in this state, inverter 4ab and MOS transistor 4af constitute a latch circuit, pad 6b (input node 4ai) is reliably held at the ground voltage level, and there is no current path.

  When pad 6b is in the NC state and is not connected to the pin terminal, when power is turned on, power-on detection signal POR is at H level for a predetermined period. Therefore, MOS transistor 4ae causes this input node 4ai to be at the ground voltage level. Driven. When input node 4ai is initially set to L level, the output signal of inverter 4ab increases as the voltage level of power supply voltage VDDq increases, MOS transistor 4af is turned on, and input 4ai is set to the ground potential level. Discharge. Thereby, inverter 4ab and MOS transistor 4af form a latch circuit, and input node 4ai and pad 6b are set to the ground voltage level. Therefore, even in the NC state, there is no path through which current flows, and current consumption is reduced. Further, since no pull-up or pull-down resistor is used, no through current is generated in such a resistor, and current consumption is reduced.

  As described above, function setting signal / OBi from function setting circuit 4a is set to the L level when the BGA package is sealed, and is set to the H level when the QFP package is sealed. The logic level is different. Thus, the boundary scan test circuit can be set in an operable / inoperable state according to the potential of the pad 6b in accordance with the type of package to be sealed.

  The pin terminal to which the bonding pad 6b is connected may be a power supply pin terminal when set to the H level, and may be a pin terminal that receives the ground voltage when set to the L level. In addition, when pad 6b is connected to a pin terminal externally, a configuration in which the corresponding pin terminal is externally fixed at a power supply voltage level or a ground voltage level may be used. Further, the potential of the pad 6b may be fixed simply by mask wiring.

  FIG. 4 shows an example of the configuration of mode setting circuit 4b shown in FIG. In FIG. 4, the mode setting circuit 4b includes an input protection circuit 4ba for protecting the internal circuit from an excessive voltage of the pad 6c, an inverter 4bb for inverting the logic of the signal ZZ on the pad 6c, and an output signal of the inverter 4bb. Inverter 4bc which inverts, level conversion circuit 4bd which converts the level of the output signal of inverter 4bb according to the output signals of inverters 4bb and 4bc, and input node 4bi of inverter 4bb in response to power-on detection signal POR. N channel MOS transistor 4be discharging to the level and n channel MOS transistor 4bf discharging input node 4bi of inverter 4bb to the ground voltage level in response to the output signal of inverter 4bb.

  Inverters 4bb and 4bc operate using power supply voltage VDDq (= 1.8V) as one operating power supply voltage, and input protection circuit 4ba and level conversion circuit 4bd operate using power supply voltage VDD (= 3.3V) as one operating power supply voltage. receive. The configuration of mode setting circuit 4b shown in FIG. 4 is the same as that of function setting circuit 4a shown in FIG. 3, and only the signals applied to the pads are different. Snooze mode signal ZZ is applied to pad 6c, internal snooze mode instruction signal / ZZi is output from node 4bk of level conversion circuit 4bd, and internal snooze mode instruction signal ZZi is output from node 4bj. The operation of the mode setting circuit 4b shown in FIG. 4 is the same as that of the function setting circuit 4a shown in FIG. The mode setting circuit 4b is a circuit for setting whether or not the synchronous burst SRAM operates according to the snooze mode. When the snooze mode is not used, the pad 6c is fixed to the L level or set to the NC state (the corresponding pin terminal may be in the NC state). In this state, the voltage level of input node 4bi is L level, internal snooze mode instruction signal ZZi is L level, and memory internal circuit 2 (see FIG. 1) operates in the normal operation mode.

  On the other hand, in order to enable the snooze mode operation, the pad 6c is connected to a corresponding pin terminal. The external pin terminal is supplied with an L level snooze mode instruction signal ZZ in the normal operation mode, and with an H level snooze mode signal ZZ in the snooze mode. When snooze mode signal ZZ is set to this H level, input node 4bi goes to H level, internal snooze mode instruction signal ZZi goes to H level, the memory internal circuit is set to snooze mode, and operation stops.

  The mode setting circuit shown in FIG. 4 has the same configuration as the function setting circuit 4a shown in FIG. 3, and can similarly set the internal node to a predetermined voltage level stably with low current consumption.

  The pad 6c may always be connected to a corresponding pin terminal (ZZ pin), and the pin terminal may be set to the NC state, the L level fixed state, or the H / L state. This is because the pin terminal for the snooze mode is assigned to the outside in both the QFP package and the BGA package. This is different from the function setting circuit 4a shown in FIG. A pin terminal may not be assigned for the signal / OB.

  FIG. 5 is a diagram showing an example of the configuration of the power-on detection circuit 5 shown in FIG. In FIG. 5, power-on detection circuit 5 includes a p-channel MOS transistor 5a connected between a power supply node receiving power supply voltage VDD and node NA and having its gate connected to node NA, and between node NA and the ground node. Capacitor 5b connected to node 5, high resistance resistor 5c connected between node NA and ground node, inverter 5e for inverting the logic of the potential of node NA and transmitting it to node NB, and output signal of inverter 5e Is inverted and transmitted to the input of the inverter 5e, the capacitor 5f connected between the node receiving the power supply voltage VDD and the node NB, and the signal at the node NB is inverted to complement the power-on detection signal / POR. For generating the power-on detection signal POR by inverting the output signal of the inverter 5g Including. Inverters 5d and 5e constitute a latch circuit. The current driving force of the inverter 5d is reduced. Next, the operation of the power-on detection circuit 5 shown in FIG. 5 will be described with reference to the signal waveform diagram shown in FIG.

  Before power-on, nodes NA and NB are at the ground voltage level, and output signals of inverters 5g and 5h are at the L level. When the power is turned on, the voltage level of the power supply voltage VDD increases. MOS transistor 5a is diode-connected and supplies current to node NA. Capacitor 5b and resistor 5c are connected to node NA, and the voltage level of node NA rises gently. The charging of the node NA is started after the power supply voltage VDD becomes higher than the absolute value of the threshold voltage of the MOS transistor 5a. On the other hand, node NB is coupled to the power supply node by capacitor 5f, and the voltage level of node NB rises due to capacitive coupling of capacitor 5f as power supply voltage VDD rises. Thereby, node NB is latched at H level and node NA is latched at L level by inverters 5e and 5d. Therefore, since node NB is latched at the H level, the voltage level of power-on detection signal POR output from inverter 5h increases as power supply voltage VDD increases.

  On the other hand, when the node NA is charged by the MOS transistor 5a and the charging potential of the capacitor 5b becomes higher than the input logic threshold value of the inverter 5e (the current driving force of the track 5a is larger than that of the inverter 5d), the inverter 5e Thus, the voltage level of node NB is driven to L level, and accordingly, power-on detection signal POR output from inverter 5h is driven to H level. In this state, node NA is latched at the H level by inverters 5e and 5d, and the voltage level rises according to the time constant determined by capacitor 5b and resistor 5c.

  Therefore, the power-on detection signal POR maintains the H level when the power is turned on until the power supply voltage VDD exceeds a certain voltage level. Therefore, MOS transistors 4ae and 4bb shown in FIGS. 3 and 4 are turned on for a period when power-on detection signal POR is higher than the threshold voltage of MOS transistors 4ae and 4be, and the corresponding nodes 4ai and 4bi are turned on. Are discharged to the ground potential level. Thereby, each internal node can be initialized to a predetermined voltage level accurately.

  FIG. 7 is a diagram showing an example of the configuration of the input circuit 3b included in the boundary scan test circuit 3 shown in FIG.

  In FIG. 7, control gate 4c includes an internal snooze mode instruction signal ZZi and a two-input NOR circuit 4ca that receives complementary internal function setting signal / OBi. Complementary internal function setting signal / OBi is output from the circuit shown in FIG. 3, and internal snooze mode instruction signal ZZi is output from the mode setting circuit shown in FIG.

  The input circuit 3b includes an input protection circuit 3ba for protecting the internal circuit when an excessive voltage is applied to the pad 6a, a 2-input NAND circuit 3bb for receiving the signal JTG on the pad 6a and the output signal of the control gate 4c, Inverter 3bc for inverting the output signal of NAND circuit 3bb, and level conversion circuit 3bd for converting the voltage level of the output signal of inverter 3bb in accordance with the output signal of NAND circuit 3bb and the output signal of inverter 3bc are included.

  Input protection circuit 3ba includes a diode connected between pad 6a and the power supply node and a diode connected between pad 6a and the ground node. The configuration of the input protection circuit 3ba is the same as the configuration of the input protection circuit shown in FIGS. A power supply voltage VDD is applied to the input protection circuit.

  2-input NAND circuit 3bb is connected in series between a power supply node receiving power supply voltage VDDq and output node 3bbi, and has p-channel MOS transistor PQ5 whose gate is coupled to pad 6a, and between output node 3bbi and the ground node. N channel MOS transistors NQ6 and NQ7 connected to, and a p channel MOS transistor PQ6 connected between the power supply node receiving power supply voltage VDDq and the output node and receiving the output signal of control gate 4c at its gate. MOS transistor NQ6 receives the output signal of control gate 4c at its gate, and MOS transistor NQ7 has its gate coupled to pad 6a.

  Inverter 3bc has a configuration of a CMOS inverter composed of a p-channel MOS transistor and an n-channel MOS transistor. Inverter 3bc operates with power supply voltage VDDq as one operating power supply voltage.

  Level conversion circuit 3bd converts the voltage VDDq level signal from NAND circuit 3bb into a voltage VDD (= 3.3V) level signal and outputs complementary internal input signal / JTGi. From node 3bj, an internal signal JTGi having the same logic as the signal on pad 6a is output. These signals JTGi and / JTGi are applied to boundary scan test control circuit 3c shown in FIG. The configuration and operation of level conversion circuit 3bd are the same as those of level conversion circuits 4ad and 4bd shown in FIGS. Next, the operation will be described.

(I) When sealing the BGA package:
When sealing the BGA package, the pad 6a is connected to the corresponding pin terminal. When the BGA package is sealed, the function setting signal / OBi is set to the L level (bonding option). In this state, the output signal of NOR circuit 4ca included in control gate 4c outputs a signal corresponding to internal snooze mode instruction signal ZZi. When internal snooze mode instruction signal ZZi is at L level, the output of NOR circuit 4ca is at H level, MOS transistor NQ6 is turned on, and MOS transistor PQ6 is turned off. Therefore, internal signals JTGi and / JTGi are generated in accordance with signal JTG applied through pad 6a, and a boundary scan test can be performed.

  On the other hand, when internal snooze mode instruction signal ZZi is set to H level, the output signal of NOR circuit 4ca included in control gate 4c becomes L level, MOS transistor NQ6 is turned off, and MOS transistor PQ6 is turned on. . In this state, the output signal of NAND circuit 3bb is fixed at the H level regardless of the state of signal JTG of pad 6a. Accordingly, internal signal JTGi is fixed at L level and internal signal / JTGi is fixed at H level. When internal snooze mode instruction signal ZZi is at the H level, snooze mode is designated and all operations of the internal circuit are stopped.

  At the time of sealing the BGA package, the pad 6a is connected to the external pin terminal, and this signal JTG becomes H level or L level. Therefore, regardless of the signal potential on pad 6a (or pin terminal), the voltage level of internal node 3bbi is fixed to H level, so that the operation of the circuit portion that operates in response to the output signal of NAND circuit 3bb is performed. Can be stopped (switching operation can be stopped). Thereby, all the current consumption of the internal circuit can be reduced. Further, by turning off the MOS transistor NQ6 in the NAND circuit 3bb, a path through which the through current of the NAND circuit 3bb flows can be cut off, and current consumption can be reduced.

(Ii) When sealing the QFP package:
At the time of sealing the QFP package, the pad 6a is in a floating state because the pin terminal is not provided. When the QFP package is sealed, internal function setting signal / OBi is fixed at the H level (see FIG. 3). Therefore, the output signal from control gate 4c is fixed at L level, MOS transistor NQ6 is turned off, MOS transistor PQ6 is turned on, and output node 3bbi of NAND circuit 3bb is fixed at the voltage level of power supply voltage VDDq. . In this state, regardless of the signal potential of pad 6a, NAND circuit 3bb is set in an inoperable state with the potential level of its output signal fixed. Also in the test control circuit subsequent to level conversion circuit 3bb, the potential level of the applied signal is fixed, so that the internal circuit does not operate and is set in an inactive state (the same state as in the snooze mode).

  Even if the pad 6a is in a floating state, the function setting signal / OBi reliably prevents malfunction by setting the input circuit 3b to an inoperable state (the potential of the output signal of the 2-input NAND circuit 3bb is fixed). can do. Further, when the pad 6a is in a floating state, current consumption flowing from the power supply node to the ground node of the NAND circuit 3bb can be cut off to reduce current consumption.

  Further, when the pad 6a is connected to the external pin terminal by controlling the operation enable / disable state of the input circuit 3b by taking the logic of the internal snooze mode instruction signal ZZi and the internal function setting signal / OBi (BGA The current consumption in the input circuit 3b can be surely reduced in the snooze mode when the package is sealed.

  As described above, according to the first embodiment of the present invention, in the circuit in which the presence / absence of connection to the pin terminal is determined according to the package to be sealed, this boundary is determined according to the potential of a specific pad. Since the dual scan test circuit is selectively set to an operable state or an inoperable state, it is possible to accurately prevent malfunction when the boundary scan test circuit is not used.

  In addition, a 2-input NAND circuit is used for the input part of the test circuit. When this circuit is not used, the current path of the input circuit is cut off and the output signal potential level is fixed, thereby reliably reducing current consumption. can do. Also, the snooze mode is used when the pad of the test circuit is connected to the pin terminal by combining the snooze mode instruction signal and the function setting signal to set the operation enable / disable state of the input circuit. Even in the case, current consumption can be surely reduced.

  In the above configuration, the correspondence relationship between the internal snooze mode instruction signal and the logic level at which internal function setting signal / OBi is activated and the operable / incapable state of the internal circuit is an example. Relationships may be used.

[Embodiment 2]
FIG. 8 schematically shows a whole structure of the semiconductor integrated circuit according to the second embodiment of the present invention. FIG. 8 shows the configuration of a synchronous burst SRAM. In FIG. 8, this synchronous burst SRAM includes a memory internal circuit 2, a follow-through mode setting circuit 10a for setting the follow-through mode of the memory internal circuit 2 in accordance with the potential of the signal FT of the pad 11a, and a pad 11b. A burst mode setting circuit 10b for setting the burst mode of the memory internal circuit 2 in response to the signal potential of the upper signal LBO is included. The memory internal circuit 2 has a configuration shown in FIG. The output signal of follow-through mode setting circuit 10a is applied to an output register included in memory internal circuit 2, and the output register is set to the pipeline or non-pipeline mode according to the potential of signal FT on pad 11a.

  Burst mode setting circuit 10b provides the output signal to a burst address counter included in memory internal circuit 2. The burst mode setting circuit 10b sets the burst mode to either the interleaved burst mode or the linear burst mode according to the potential of the signal LBO on the pad 11b. Pads 11a and 11b are bonding option pads, and their potential levels are determined according to the set operation mode. That is, the pads 11a and 11b are set to any one of the H level, the L level, and the NC state. Follow-through mode setting circuit 10a and burst mode setting circuit 10b do not include a pull-up or pull-down resistor. As a result, when the pads 11a and 11b are set to a logic state different from the output logic in the NC state (when bonding is performed), the follow-through mode setting circuit 10a and the burst mode setting circuit 10b are pulled up and pulled out. The path through which the through current flows in the pull-down resistor is cut off to reduce current consumption.

  FIG. 9 shows an example of the configuration of follow-through mode setting circuit 10a and burst mode setting circuit 10b shown in FIG. Since follow-through mode setting circuit 10a and burst mode setting circuit 10b have the same configuration, they are shown as operation mode setting circuit 20.

  In FIG. 9, an operation mode setting circuit 20 receives an input protection circuit 20a for absorbing an excessive voltage to the pad 11 and a power supply voltage VDDq at the gate, and a voltage lower than the power supply voltage VDDq from the pad 11 to the internal input node 20i. In accordance with the output signal of inverter 20b, inverter 20b for inverting the signal on internal input node 20i, inverter 20c for inverting the output signal of inverter 20b, and the output signals of inverters 20b and 20c. Includes a level conversion circuit 20d for converting the voltage level of the first voltage. Inverters 20b and 20c operate using power supply voltage VDDq as one operating power supply voltage, and level conversion circuit 20d operates using power supply voltage VDD (= 3.3V) as one operating power supply voltage. Therefore, the level conversion circuit 20d converts a signal having the amplitude of the power supply voltage VDDq into a signal having the amplitude of the power supply voltage VDD. The configurations of inverters 20b and 20c and level conversion circuit 20d are the same as those shown in FIGS.

  Operation mode setting circuit 20 further includes a p-channel MOS transistor 20e transmitting power supply voltage VDDq to internal input node 20i in response to an output signal of inverter 20b, and an internal input in response to power-on detection signal / POR. P channel MOS transistor 20g transmitting power supply voltage VDDq to node 20i is included. The power-on detection signal / POR is a complementary signal to the power-on detection signal POR shown in FIG. 6, and rises to the H level when the power supply voltage VDDq exceeds a predetermined voltage level. Next, the operation will be described.

(I) When the pad 11 is fixed at the H level:
When pad 11 is fixed at H level, internal input node 20i is set to H level via MOS transistor 20f, the output signal of inverter 20b becomes L level, MOS transistor 20e is turned on, The H level of input node 20i is latched by inverter 20b and MOS transistor 20e. Since the output signal of inverter 20b is at L level, internal signal φMi from level conversion circuit 20d is at H level of power supply voltage VDD level, and complementary internal operation mode instruction signal / φMi is at L level of ground voltage level. Become. Signal φM on pad 11 is follow-through mode signal FT or burst mode control signal LBO. When signal FT is set to H level, a pipeline operation is performed, and data is output in synchronization with the clock signal. On the other hand, in the case of the burst mode control signal LBO, the burst address is changed according to a sequence defined in the interleaved burst mode.

  When pad 11 is set to this H level, there is no path through which current flows in inverter 20b (during a stable state). Further, the MOS transistor 20g is turned on only when the power is turned on, and after the power supply voltage VDDq is stabilized, the MOS transistor 20g is kept off and there is no current path. Even when the voltage level of signal φM on pad 11 is set to, for example, power supply voltage VDD level, decoupling MOS transistor 20f causes voltage level of power supply voltage VDDq−Vth to be supplied to internal input node 20i. Only transmitted. Here, Vth is a threshold voltage of the MOS transistor 20f. Therefore, when pad 11 has a voltage level higher than power supply voltage VDDq, MOS transistor 20f operates with its internal input node 20i as the source, so that MOS transistor 20f has the same voltage level at the source and gate, and is off. The state is maintained and the current path is interrupted. Therefore, in this state, there is no current flow path, and current consumption is reduced.

(Ii) When the pad 11 is set to L level:
When pad 11 is set at the L level of the ground voltage level, internal input node 20a is set at the L level. The output signal of inverter 20b becomes H level, and internal operation mode instruction signal φMi from level conversion circuit 20d similarly becomes L level, while complementary internal operation mode instruction signal / φMi becomes H level. In this case, MOS transistor 20e is in an off state, and there is no path through which current flows from the power supply node to the external terminal via pad 11 after internal input node 20i is set to the L level.

  CMOS inverter 20c and level conversion circuit 20d exhibit characteristics peculiar to the CMOS circuit in the stable state, and all the MOS transistors are turned off, so that no current flows.

  When pad 11 is set at the L level, in the case of follow-through mode signal FT, a follow-through operation is performed in the memory internal circuit, and output data is read out in a pipeline manner. On the other hand, in the case of the burst mode control signal LBO, the burst address is updated according to the linear burst mode.

(Iii) When the pad 11 is in a floating state:
As shown in FIG. 10, the power-on detection signal / POR is maintained at the L level until the power voltage VDD reaches a predetermined voltage level after the power voltage VDD is turned on (see the circuit in FIG. 5). . Therefore, during this period, the MOS transistor 20g is turned on, and the node 20i is charged via the MOS transistor 20g and rises in accordance with the rise in the voltage level of the power supply voltage VDDq. In this state, since the voltage level of internal input node 20i does not exceed the input logic threshold level of inverter 20b, the output signal potential of inverter 20b also rises as the power supply voltage level rises.

  When the voltage level of node 20i exceeds the input logic threshold value of inverter 20b, the output signal of inverter 20b rises to L level, MOS transistor 20e is turned on, and internal input node 20i Is charged through. Therefore, even when power-on detection signal / POR rises to H level and MOS transistor 20g is turned off, internal input node 20i is latched to H level by inverter 20b and MOS transistor 20e. In particular, the power supply voltage VDD is higher than the power supply voltage VDDq of the inverter 20b. If the charge level of the internal input node 20i is set to a predetermined voltage level of the power supply voltage VDD, The output signal of inverter 20b is driven to the H level, and internal input node 20i can be held at the voltage level of power supply voltage VDDq by the latch circuit formed of MOS transistor 20e and inverter 20b.

  Therefore, even when pad 11 is in the NC state and is set in the floating state, internal input node 20i is reliably set to the H level. After the internal input node 20i is set to the H level of the power supply voltage VDDq, the MOS transistor 20e maintains the off state, so that there is no path through which current flows, and current consumption is reduced.

  In this case, the same state as when the pad 11 is fixedly set at the H level is realized.

  In the circuit configuration shown in FIG. 9, when the signal φM is changed from the H level to the L level, the MOS transistor 20e is in the on state when the signal φM is at the H level. Therefore, the input signal φM is changed from the H level. Only immediately after changing to the L level, a current flows from the MOS transistor 20e through the MOS transistor 20f and the pad 11. However, when the inverter 20b operates and the voltage level of the MOS transistor 20e becomes H level (the level of the voltage VDDq), the MOS transistor 20e is turned off, and a path through which a steady through current flows is cut off. Therefore, in the configuration of operation mode setting circuit 20 shown in FIG. 9, not only when the voltage level of pad 11 is fixedly set, but also when the voltage level is switched under the control of an external device, Current consumption can be realized.

  When the MOS transistor 20f is used, no current flows through the input protection circuit 20a even if a voltage of about 3.3V is applied to the pad 11. Only the voltage level of power supply voltage VDDq is transmitted to internal input node 20i by MOS transistor 20f. When MOS transistor 20f is not provided, when signal φM is set at power supply voltage VDD level, MOS transistor 20e is turned on, and current flows from the external pin terminal to power supply VDDq via pad 11 and MOS transistor 20e. .

  Therefore, by providing the MOS transistor 20f, the MOS transistor 20f can be operated as a decoupling transistor, and the voltage level of the pad 11 can be set to a voltage level of 1.8V or 3.3V. That is, when connected to the external pin terminal, the level of the signal φM can be set to either the power supply voltage VDD or the power supply voltage VDDq. Therefore, when the power supply wiring layout is complicated in the on-board wiring, the most easily used power supply voltage can be used, and the degree of freedom in board design can be increased.

  This is because, in the system used, the burst mode of the synchronous burst SRAM is fixedly set, and the follow-through mode is usually set to a state in which the pipeline operation is set.

  As described above, according to the second embodiment of the present invention, in the configuration in which the internal operation mode is set by the pad potential, the internal input node is set to the H level by the latch circuit composed of the inverter and the MOS transistor, and this internal Since the decoupling transistor is provided between the input node and the pad, a path through which a current flows can be cut off regardless of the state of the pad, and current consumption can be reduced. Also, by providing this decoupling transistor, the voltage level of the pad 11 can be set to either the power supply voltage VDD or VDDq, and this connection can be determined according to the power supply wiring layout on the board. The degree of freedom in board design can be increased.

  In the configuration shown in FIG. 9, the internal snooze mode instruction signal is not used. When this semiconductor integrated circuit (synchronous burst SRAM) is used at the time of system mounting, the voltage level of the pad 11 is often fixed during actual use. In this state, in this burst mode setting circuit, This is because there is no path through which the through current flows, and it is not necessary to cut off.

  In the above description, the pad 11 is described as being in a floating state. However, the pad 11 may be bonded to a corresponding external pin terminal, and this external pin terminal may be set to the NC state.

  In particular, in the case of a synchronous burst SRAM, the follow-through mode control signal FT # and the burst mode control signal LBO # are assigned to both the QFP package and the BGA package, and the NC state indicates that the external pin terminal is in a normally floating state. Corresponding to the state to be performed.

[Other application examples]
In the above description, the synchronous burst SRAM is shown as the semiconductor integrated circuit. However, if the semiconductor integrated circuit is sealed in either the QFP package or the BGA package, the same effects as those of the first embodiment can be obtained. When encapsulated in a BGA array, a boundary scan test circuit is required. In this case, when the power down mode for stopping the internal circuit operation such as the snooze mode is not provided, the state of the operation mode (input circuit) of the logic gate is determined only by the output signal of the function setting circuit. The Therefore, in this case, the test input circuit has the same configuration as the operation mode setting circuit shown in FIG. 4 or FIG.

  Further, the operation mode setting signal may be not only the follow-through mode and the burst mode as described above, but also other operation modes, as long as the internal operation mode is set simply by the potential of the bonding option pad. The second embodiment or the first embodiment can be applied.

  In the above description, the BGA package is shown. However, the solder balls (bumps) may be arranged in a two-dimensional array.

The present invention can be applied to a semiconductor integrated circuit having bonding option pads / pins.

1 schematically shows an entire configuration of a semiconductor integrated circuit according to a first embodiment of the invention. FIG. FIG. 2 is a diagram schematically showing a configuration of a scan register group shown in FIG. 1. It is a figure which shows an example of a structure of the function setting circuit shown in FIG. It is a figure which shows an example of a structure of the mode setting circuit shown in FIG. It is a figure which shows an example of a structure of the power-on detection circuit shown in FIG. FIG. 6 is a signal waveform diagram showing an operation of the power-on detection circuit shown in FIG. 5. It is a figure which shows an example of a structure of the input circuit shown in FIG. It is a figure which shows roughly the structure of the principal part of the semiconductor integrated circuit according to Embodiment 2 of this invention. It is a figure which shows an example of a structure of the follow through mode setting circuit and burst mode setting circuit which are shown in FIG. FIG. 10 is a signal waveform diagram representing an operation of the operation mode setting circuit shown in FIG. 9. (A) is a top view of the QFP package, (B) is a front side view of the QFP package, (C) is a right side view, and (D) is a portion 30B of (B). FIG. (A) is a top view of a BGA package, (B) is a right side view, and (C) is a back view thereof. It is a figure which shows schematically the whole structure of the conventional synchronous burst SRAM. It is a figure which shows the pin arrangement in the QFP package of synchronous burst SRAM. It is a figure which shows the pin arrangement | positioning of the BGA array of synchronous burst SRAM. It is a figure for demonstrating the conventional boundary scan test. It is a figure which shows schematically the structure of the conventional semiconductor integrated circuit with a boundary scan test circuit. FIG. 5 is a diagram showing a list of correspondence relationships between bonding option pin states of an operation mode setting signal of a synchronous burst SRAM and specified operation modes. It is a figure which shows the structure of the input part of the conventional bonding option pad. It is a figure which shows the structure of the input part of the conventional bonding option pad.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit, 2 Memory internal circuit, 3 Boundary scan test circuit, 3a Scan register group, 3b Input circuit, 3c Test control circuit, 4 Control circuit, 4a Function setting circuit, 4b Mode setting circuit, 4c Control gate, 5 Power-on detection circuit, 6a, 6b, 6c pad, 4ab inverter, 4ae, 4af MOS transistor, 4bb inverter, 4be, 4bf MOS transistor, 4ad, 4bd level conversion circuit, 4ca NOR circuit, 3bb 2-input NAND circuit, 10a follow-through Mode setting circuit, 10b burst mode setting circuit, 20 operation mode setting circuit, 20b inverter, 20f n-channel MOS transistor, 20g, 20e p-channel MOS transistor.

Claims (2)

pad,
A first transistor for setting the pad to a voltage level of a first logic level upon power-up;
An inverter for inverting the logic of the potential on the pad; and a second transistor provided in parallel with the first transistor and receiving an output signal of the inverter at a control electrode node;
A semiconductor integrated circuit in which an operation mode of an internal circuit is set by an output signal of the inverter. It said pad being interposed between the input portion of the inverter, further comprising a semiconductor integrated circuit according to claim 1, wherein the transfer gate receiving a fixed potential to the control electrode node.

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