JP2008288406A - Tape carrier for semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a tape carrier for a semiconductor device which can be subjected to continuity test as it is, while avoiding blockage of further miniaturization, densification, increased number of pins and so on for a wiring pattern or a connection pad, avoiding adverse influences to electrical characteristics on a signal current flowing through the wiring pattern, and eliminating the need for a troublesome work such as debasing and to provide a method of manufacturing the tape carrier. <P>SOLUTION: In the tape carrier for a semiconductor device, a blind via 22a and a reinforcement copper layer 20 as a peelable layer are used as a conductor for supplying an electroplating current, a gold/nickel electroplated layer 24 is formed on the surface of at least one of a wiring pattern 12 and a connection pad 13 by electroplating, and the reinforcement copper layer 20 is peeled off after completion of the electroplating step. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  In the present invention, an electrolytic plating layer such as an electrolytic gold plating layer or an electrolytic gold / nickel plating layer is formed on a wiring pattern or a connection pad, and a semiconductor device such as a driver IC for a liquid crystal display device is mounted. The present invention relates to a tape carrier for a semiconductor device and a manufacturing method thereof.

Conventionally, this type of semiconductor device tape carrier has a wiring pattern and a connection pad formed on one surface of an insulating film substrate such as a carrier tape made of polyimide film, and electrolytic gold / nickel plating on the surface. A layer is formed. A semiconductor device such as a driver IC for a liquid crystal display device mounted on a surface opposite to the surface on which a wiring pattern or the like is formed is bonded to a connection pad through a device hole.
A substantially spherical bonding member such as a solder ball or a gold ball is provided in a grid shape on the surface on which the wiring pattern or the like is formed to form a so-called ball grid array (BGA) package. Such a BGA package is proposed in, for example, Japanese Patent Application Laid-Open No. 2005-236244 (Patent Document 1).

The semiconductor mounting package having such a structure is called a 1 metal circuit out type BGA package, and a substrate (tape carrier) used therefor is called a 1 metal circuit out type BGA substrate.
In this one-metal circuit-out type BGA substrate, in general, as a final surface treatment on the surface of a wiring pattern or a connection pad, an electrolytic gold / nickel plating layer by an electrolytic plating method or an electroless gold / nickel layer by an electroless plating method. A nickel plating layer is formed.

The advantage of the electrolytic plating method and the electrolytic gold / nickel plating layer formed thereby is that, first, thick gold plating suitable for wire bonding can be stably and efficiently applied in a short time. That is. This is a very advantageous advantage for a one-metal circuit-out type BGA substrate (more specifically, a tape carrier for a semiconductor device serving as the substrate) that is strongly required to have good mass productivity and good throughput.
Secondly, as described above, a thick gold plating suitable for wire bonding can be applied on the wiring pattern and connection pads, so that infrastructure for abundant mounting equipment, etc. without using a special bonding process. There is also an advantage that reliable bonding can be easily performed at low cost by the wire bonding method that can be used.

However, on the other hand, the first drawback is that a power supply wiring (also called power supply lead) is required to supply the current for electroplating during the plating operation, and this is arranged on the substrate together with the wiring pattern and connection pads. Must. For this reason, the freedom of design tends to be restricted. In particular, as the wiring pattern is further miniaturized and denser, and the number of pins is increased (the number of bonding pads and leads is further increased), the presence of the power supply wiring becomes increasingly obstructive. In other words, the presence of power supply wiring that is essential for electrolytic plating can be a factor that significantly hinders further miniaturization, densification, and increase in the number of pins of wiring patterns and connection pads.
Secondly, in general, the power supply wiring is left with the wiring pattern on the substrate even after the electrolytic plating process is completed. There is a high risk of adverse effects on electrical characteristics due to the antenna effect and the like. Such an adverse effect on electrical characteristics tends to become more prominent as the operation of a semiconductor integrated circuit or the like mounted further increases in speed and becomes compatible with high-frequency signals.
Third, wiring patterns and connections corresponding to individual elements at a stage prior to separation of elements after mounting a semiconductor chip or the like, that is, at a stage where the tape carrier is still connected to a single tape. Even if the pad energization test is to be performed, at this stage, almost all wiring patterns are connected by the power supply wiring, so it is difficult or impossible to conduct the energization test, especially the short-circuit test. It is. Generally, in a tape carrier for a semiconductor device, it is required to complete an energization test as a single tape carrier after it is completed and before a semiconductor chip is mounted. In order to carry out the process, after performing electrolytic plating, an extremely complicated, time-consuming and time-consuming separation (cutting) operation called so-called electrode removal (debashing) is performed to make each wiring pattern independent. There must be.

On the other hand, the advantages of the electroless plating method and the electroless gold / nickel plating layer formed by the electroless plating method are, first of all, electroless plating, which eliminates the need for power supply wiring, and thus increases the degree of freedom in design. In addition, as for the formation of the gold plating layer, there is a case that further miniaturization / densification / multi-pinning of the wiring pattern and connection pads are not hindered.
Second, since there is no power supply wiring, there is no adverse effect on the electrical characteristics with respect to the signal current due to reflection noise, antenna effect, or the like when it exists.
Third, since there is no power supply wiring, almost all wiring patterns can be made independent even at the stage of one tape carrier. Therefore, it is possible to perform an energization test without performing an extremely complicated and time-consuming separation work such as debashing.

However, on the other hand, the first disadvantage is that thick gold plating is generally difficult with the electroless plating method. Therefore, in the completed tape carrier for semiconductor devices, it is based on a general gold wire for gold / gold bonding. It may be difficult to employ wire bonding.
Second, the electroless plating method generally tends to have a low deposition rate of the plating layer. This is extremely inconvenient as a technology for manufacturing a tape carrier for semiconductor devices, which is one of mass-produced industrial products for which productivity and efficiency are strongly demanded. Alternatively, in order to overcome this, it may be effective to increase the deposition rate of the electroless plating layer by increasing the temperature of the working solution (electroless plating solution). Another new inconvenience arises that the material that can be used becomes severely limited, such as the necessity of using a material with high temperature durability.
Thirdly, the manufacturing process of one-metal circuit-out type BGA substrates using the tape carrier system for semiconductor devices is basically a technology for improving productivity and efficiency, and is a continuous line using reel to reel. In most cases, it is manufactured. However, when electroless plating is performed on such a reel-to-reel continuous line, abnormal precipitation occurs due to local cell action on the surface to be plated, for example, in the state of being wound on a reel, which is markedly plated. There is a risk that the quality of the surface may be impaired.
Fourth, in electroless gold plating by the replacement method with nickel, a phosphorus-rich layer called a black pad is likely to be formed on the surface of the nickel plating, which may significantly impair ball shear strength.
Judging from the characteristics of the electrolytic plating method and the electroless plating method, it is possible to apply gold plating with thick and thick metal plating mainly at the present time. The electroplating method is advantageous in that it is easy to become familiar with bonding, and in many cases, an electrolytic gold plating layer or an electrolytic gold / nickel plating layer is often used on the surface of a wiring pattern or a connection pad. .

JP 2005-236244 A

However, in the electroplating method, since the power supply wiring is indispensable as described above, the presence of the power supply wiring has been a significant hindrance to further miniaturization / densification / multi-pinning of wiring patterns and connection pads. .
Further, there has been a problem that reflection noise due to the presence of the power supply wiring, antenna effect, and the like have an adverse effect on electrical characteristics with respect to a signal current flowing through the wiring pattern.
Further, almost all wiring patterns are in a continuous state due to the presence of the power supply wiring, and there is a problem that it is difficult or impossible to perform an energization test in a tape carrier state.
Further, in particular, in a BGA substrate provided with a device hole, in many cases, the power supply leads are concentrated around the position where the device hole is to be drilled, and after the electrolytic plating is performed, the device The hole is punched out, but at that time, the power supply lead that has been continuous is cut to make the circuit electrically independent. However, when the number of input / output terminals further increases, there is a high possibility that it will become increasingly difficult to route the power supply lead to a predetermined location due to restrictions on the wiring rules of the board. Also, when punching a device hole, the power supply REIT will be exposed at the end face of the device hole, but a burr occurs in the power supply lead due to the stamping of the punching, which is a short circuit in the circuit system due to the wiring pattern. There is a high risk of causing defects.
Thus, the conventional general power supply wiring that causes such various problems is indispensable for electrolytic plating and cannot be omitted. It was thought that it was not easy to solve.

  The present invention has been made in view of such problems, and its purpose is not to prevent further miniaturization / densification / multi-pinning of the wiring pattern and connection pads, and the signal flowing through the wiring pattern. It is possible to conduct an energization test in the state of a tape carrier without adversely affecting the electrical characteristics with respect to the current and without requiring complicated work such as electrode removal (debashing). Another object of the present invention is to provide a semiconductor device tape carrier and a method of manufacturing the same.

  In the first tape carrier for a semiconductor device of the present invention, a wiring pattern and a connection pad are formed on one side of the front and back surfaces of the insulating film substrate, and at least on the surface of the connection pad among the wiring pattern and the connection pad. An electrolytic plating layer is formed, and is connected to at least one of the wiring pattern and the connection pad from a surface opposite to the one surface on which the wiring pattern is formed in the insulating film substrate. A blind via made of a conductive material for power supply for electrolytic plating is provided, and the power supply wiring for electrolytic plating does not exist on both surfaces of the insulating film substrate.

  The tape carrier for a semiconductor device according to a second aspect of the present invention is the tape carrier for a semiconductor device according to the first aspect, wherein the blind via is made of a conductive metal formed by conformal plating.

  The tape carrier for a semiconductor device according to a third aspect of the present invention is characterized in that, in the first or second tape carrier for a semiconductor device, the electrolytic plating layer is an electrolytic gold plating layer or an electrolytic gold / nickel plating layer. It is said.

The first method for manufacturing a tape carrier for a semiconductor device according to the present invention has a metal conductor material layer for forming a wiring pattern and a connection pad on one surface, and a conductor provided on the surface opposite to the one surface so as to be peeled off. In the insulating film substrate having a peelable layer made of a material, a step of forming a blind via hole extending from the surface of the peelable layer to the metal conductor material layer, and the metal from the peelable layer through the blind via hole A step of forming a blind via made of a conductive material connected to the conductive material layer; a step of patterning the metal conductive material layer to form a wiring pattern and a connection pad; and the peelable layer and the blind via. Used as a power supply conductor for the electroplating current, by the electroplating method, the wiring pattern and the front A step of forming an electroplating layer on at least one surface of the connection pads; and a step of peeling off the peelable layer from the insulating film substrate after the formation of the electroplating layer. Yes.

  According to a second method for manufacturing a tape carrier for a semiconductor device of the present invention, in the first method for manufacturing a tape carrier for a semiconductor device, in addition to using the peelable layer as the power supply conductor, the semiconductor in the process of manufacturing. It is also used as a reinforcing layer for reinforcing the mechanical strength of the tape carrier for apparatus.

  A third method for manufacturing a tape carrier for a semiconductor device according to the present invention is characterized in that, in the first or second method for manufacturing a tape carrier for a semiconductor device, the blind via is formed by conformal plating.

  A fourth method for manufacturing a tape carrier for a semiconductor device according to the present invention is the method for manufacturing a tape carrier for a semiconductor device according to any one of the first to third aspects, wherein the electrolytic plating layer is formed by electrolytic gold plating or electrolysis. It is characterized by being formed by a gold / nickel plating method.

  According to the present invention, the peelable layer and the blind via are used as a power supply conductor for the electrolytic plating current, and an electrolytic plating layer is formed on the surface of at least one of the wiring pattern and the connection pad by an electrolytic plating method. Since the peelable layer was peeled off from the insulating film substrate after the electrolytic plating layer was formed, the power supply wiring for electrolytic plating was formed on both surfaces of the insulating film substrate on the completed tape carrier for semiconductor devices. It is possible to form an electroplating layer without leaving it at all. As a result, for example, it is possible to form an electrolytic plating layer suitable for wire bonding, such as a thick electrolytic gold plating layer, and to achieve further miniaturization, densification, multiple pins, etc. of wiring patterns and connection pads. In addition, it is possible to prevent the occurrence of adverse effects on the electrical characteristics with respect to the signal current flowing through the wiring pattern, and to conduct a current test in the state of the tape carrier without requiring complicated work such as debashing. Can be performed.

Hereinafter, a tape carrier for a semiconductor device and a manufacturing method thereof according to the present embodiment will be described with reference to the drawings.
FIG. 1 is a cross-sectional view showing the structure of the main part of a one-metal circuit-out BGA package manufactured using the tape carrier for a semiconductor device according to the present embodiment, and FIG. 2 relates to the present embodiment. 3 is a plan view of a tape carrier for a semiconductor device, FIG. 3 is a diagram showing a peelable material used for manufacturing the tape carrier for a semiconductor device of FIG. 2, and FIGS. 4, 5, and 6 are semiconductor devices according to the present embodiment. It is a figure which shows the flow of the main processes in the manufacturing method of the tape carrier for medical use. FIG. 7 is a view showing a ball shear test result in the tape carrier for a semiconductor device according to one embodiment of the present invention.

As shown in FIG. 1, a one-metal circuit-out type BGA package manufactured using the tape carrier for a semiconductor device according to the present embodiment includes a semiconductor integrated circuit 1 such as an LCD (Liquid Crystal Display) driver IC. And an adhesive layer 2 and a semiconductor device tape carrier 3.
Further, as shown in FIG. 2, the tape carrier for a semiconductor device according to the present embodiment has the transport holes 15 arranged along both edges in the longitudinal direction, and the device hole 14 at the center. A ball pad 11, a wiring pattern 12, and a connection pad (also referred to as a bonding pad) 13 are formed on one side of an insulating film substrate 10 that is provided with holes (specifically, for example, formed by a punching press). . On these surfaces, an electrolytic gold / nickel plating layer 8 (reference numeral 24 in FIGS. 4 to 6) is formed. A solder resist layer 9 (not shown in FIG. 2) is formed so as to cover one surface of the insulating film substrate 10 except for the ball pad 11, the wiring pattern 12, and the connection pad 13.

The semiconductor integrated circuit 1 is, for example, an LCD driver IC, and a large number of fine bonding pads (not shown) are arranged in the center. This semiconductor integrated circuit 1 is an insulating film substrate 10 such as a polyimide film for carrier tape, for example, on the side opposite to the surface on which a wiring layer composed of ball pads 11, wiring patterns 12, connection pads 13 and the like is formed. The adhesive layer 2 is disposed on the surface. Here, both the ball pad 11 and the connection pad 13 fall under the category of so-called connection pads, but a ball bump is connected to the ball pad 11 and a gold wire or the like is connected to the connection pad 13. This is the main difference between the two.
Bonding pads of the semiconductor integrated circuit 1 and connection pads 13 of the tape carrier 3 for semiconductor devices are connected by a gold wire 4 passing through the device hole 14. The device hole 14 is potted with the sealing resin 5.

  An electrolytic gold / nickel plating layer 8 is formed on almost the entire surface of the connection pad 13, the ball pad 11 and the wiring pattern 12. The surfaces of the connection pad 13 and the ball pad 11 are exposed without being covered with the solder resist 9 and are suitable for bonding with the gold wire 4. On the electrolytic gold / nickel plating layer 8 on the surface of the ball pad 11, ball bumps 6 for external connection such as solder balls or gold balls are attached. In spite of the formation of the electrolytic gold / nickel plating layer 8 as described above, both the front and back surfaces of the tape carrier 3 for a semiconductor device, which is the finished product, are used in general conventional electrolytic plating. There is no power supply wiring (or power supply lead, etc.).

Such a tape carrier for a semiconductor device according to this embodiment is manufactured as follows.
First, a so-called peel-able material is prepared. As shown in FIG. 3, the peelable material has a wiring pattern 12, a connection pad 13, a ball pad 11, etc. on one side (also referred to as a wiring layer surface) of an insulating film substrate 17 (10) such as a polyimide film for carrier tape. A metal conductor material layer 16 such as a copper foil is formed, and a surface opposite to one side (also referred to as a reinforcing copper layer surface) is formed of a copper foil made of, for example, 1 μm or less copper foil. A base layer 18 and an intermediate metal layer 19 are formed thereon, and a reinforcing copper layer 20 made of a conductive material such as a copper foil having a thickness capable of ensuring a predetermined mechanical strength is formed on the outermost layer thereof. It is pasted together so that it can be peeled off. This peelable material is bonded to the reinforcing copper layer 20, so that the overall mechanical properties of the insulating film substrate 10 and the metal conductor material layer 16 during the process of manufacturing a tape carrier using this peelable material. The strength can be reinforced by the mechanical strength of the reinforcing copper layer 20, and the reinforcing copper layer 20 can be easily peeled off from the interface with the intermediate metal layer 19 after the manufacturing process is completed. Is set.

As shown in FIGS. 4A to 4B, a blind via hole 21 extending from the surface side of the reinforcing copper layer 20 to the metal conductor material layer 16 is formed in such a peelable material. The blind via hole 21 can be formed by, for example, a laser beam method. The position where the blind via hole 21 is provided and the hole diameter are the optimum position and hole diameter at which an electrolytic plating current can be effectively supplied to the wiring pattern 12, the ball pad 11, and the like formed in a later process. It can be set freely. This is because the reinforcing copper layer 20 is bonded to almost the entire surface of the reinforcing copper layer of the insulating film substrate 17 in a so-called solid state, so that the blind via hole 21 can be provided by equal condition at any position. Therefore, as described above, the blind via hole 21 can be freely arranged at the optimum position for supplying the electroplating current.

Subsequently, as shown in FIG. 4 (c), copper 22 is deposited or deposited on the entire surface of the reinforcing copper layer including the inside of the blind via hole 21 and the surface of the reinforcing copper layer 20 by the filled via method. A blind via 22 a is formed by embedding copper in the hole 21. At this time, the copper layer 22b is deposited or deposited on almost the entire surface of the reinforcing copper layer 20 at a position other than the blind via hole 21, and this occurs when the reinforcing copper layer 20 is peeled off later. Since it will be peeled off together with the reinforcing copper layer 20, it may be left as it is at this stage. Rather, by adding the thickness of the copper layer 22b to the thickness of the reinforcing copper layer 20, the cross-sectional area as the conductor is increased, so that it is easier to supply current when performing electroplating, This is preferable because the mechanical strength of the entire tape carrier for a semiconductor device during manufacture can be further reinforced.
In this way, the blind via 22a that electrically connects the reinforcing copper layer 20 and the metal conductor material layer 16 is formed.

Subsequently, as shown in FIG. 4D, the metal conductor material layer 16 is patterned by, for example, a photoetching method to form the wiring pattern 12, the ball pad 11, and the connection pad 13. No power supply wiring for electrolytic plating is formed on the wiring layer surface.
Then, as shown in FIG. 4E, the solder resist pattern 9 is formed so as to expose the surfaces of the wiring pattern 12, the ball pad 11, and the connection pad 13, and cover almost the entire surface of the other wiring layer. It should be noted that the solder resist pattern 9 may be a pattern that covers the surface of the wiring pattern 12 when the surface of the wiring pattern 12 is not required to be electroplated. It is. By doing so, it is possible to further reduce the amount of gold and nickel for electrolytic plating, which are expensive and valuable so-called noble metal materials, which is preferable.

Thereafter, as shown in FIG. 5A, the substantially entire surface of the reinforced copper layer surface on which the reinforced copper layer 20 and the copper layer 22b are formed is covered with a masking film 23 made of an insulating material. This avoids significant loss of material resources, such as expensive and precious gold and nickel for electroplating being deposited on the copper layer 22b on almost the entire surface of the reinforced copper layer during electroplating in the next process. It is to do.
And as shown in FIG.5 (b), supplying the electric current for electrolytic plating from the outside using the reinforcement copper layer 20, the copper layer 22b, and the blind via 22a substantially as a feeding conductor for electrolytic plating, Electrolytic gold / nickel plating is applied to the surfaces of the wiring pattern 12, the ball pad 11, and the connection pad 13 exposed from the solder resist pattern 9 to form an electrolytic gold / nickel plating layer 24.

Subsequently, as shown in FIG. 5C, the masking film 23 is peeled off, and further, the reinforcing copper layer 20 is peeled off from the intermediate metal layer 19 as shown in FIG. The copper layer 22b is removed together with the reinforcing copper layer 20 itself. At this time, the blind via 22a is mechanically broken at the peeling interface, and the portion embedded in the blind via hole 21 as a main part thereof remains in the blind via hole 21 almost entirely.
Further, the copper base layer 18 and the intermediate metal layer 19 are completely removed as shown in FIGS. 5D to 5E by, for example, pickling. At this time, even if the residue or metal ions of the reinforcing copper layer 20 remain on the intermediate metal layer 19 at the time of peeling, the intermediate metal layer 19 itself is completely removed. There is no possibility that residues of the reinforcing copper layer 20, metal ions, or the like remain on the layer surface. Further, in this pickling process, the surfaces of the wiring pattern 12 and the connection pads 13 are already completely covered with the thick film of the electrolytic gold / nickel plating layer 24 having high acid resistance. .
In this way, the electrolytic gold / nickel plating layer 24 is applied to the surfaces of the wiring pattern 12 and the connection pads 13 without leaving any electrolytic plating power supply wiring or the like on the wiring layer surface and the reinforcing copper layer surface on the back surface. Thus, the main part of the tape carrier for a semiconductor device according to the present embodiment is manufactured.

As described above, according to the tape carrier for a semiconductor device and the manufacturing method thereof according to the present embodiment, the blind via 22a and the reinforcing copper layer 20 and the copper layer 22b, which are peelable layers, are used as the power supply conductors for the electrolytic plating current. Then, an electrolytic gold / nickel plating layer 24 is formed on the surface of the wiring pattern 12, the connection pad 13, and the ball pad 11 by electrolytic plating, and after the formation, the reinforcing copper layer 20 and the copper layer 22b are peeled off and removed. As a result, it is possible to form a thick electrolysis gold / nickel plating layer 24 suitable for wire bonding without leaving any power supply wiring for electroplating on the completed tape carrier for semiconductor devices. Become.
In addition, since the power supply wiring for electrolytic plating is not left at all, the wiring pattern 12 and the connection pad 13 can be further miniaturized, densified, multi-pinned, and the like. It is possible to prevent an adverse effect on the electrical characteristics with respect to the signal current flowing through the circuit 12, and to conduct an energization test of the wiring pattern 12 in a tape carrier state without requiring a complicated operation such as debashing It becomes possible.

Further, the reinforced copper layer 20 that has been conventionally used only for mechanical strength reinforcement and is simply peeled off and discarded after manufacture is formed as described above. The power supply wiring as described above can be used without adding a complicated process such as newly forming a power supply conductor layer for current supply separately. Electrolytic gold / nickel plating that does not remain can be easily realized.
Further, since such a reinforced copper layer 20 is a so-called solid-surface conductor layer, there is an advantage that the blind via hole 21 can be freely arranged at an optimum position for supplying an electrolytic plating current.
In addition, when performing electroplating, parts other than those necessary are covered with the solder resist pattern 9 and the masking film 23, so that gold and nickel, which are expensive and valuable material resources, are used in a necessary minimum amount. Thus, electrolytic plating can be performed, and further reduction in the amount of gold or nickel used can be achieved.
Further, in the pickling process, the surfaces of the wiring pattern 12 and the connection pads 13 are completely covered with the thick film of the electrolytic gold / nickel plating layer 24 having high acid resistance. There is also an advantage that a complicated process is not required to be added.

Here, the blind via can be formed by a conformal copper plating method as shown in FIG. 6 in addition to the blind via 22a formed by the hole-filling copper plating method as described above.
That is, first, a peelable material as shown in FIG. 6A is prepared, and a blind via hole 21 is drilled therein as shown in FIG. 6B. The process up to this point is the same as the above-described hole-filling copper plating method. Subsequently, as shown in FIG. 6 (c), the copper layer 22c is deposited or deposited by thinning that can secure a thickness capable of supplying a necessary and sufficient current for electrolytic plating. And as shown in FIG.6 (d), by peeling the reinforcement copper layer 20 from the intermediate metal layer 19,
The copper layer 22c is removed together with the reinforcing copper layer 20 itself. At this time, the blind via 22c is mechanically broken at the peeling interface, and almost all of the blind via 22c deposited or deposited in the blind via hole 21 as the main part remains in the substrate. Further, the copper base layer 18 and the intermediate metal layer 19 are completely removed by pickling.
Thus, by forming the blind via 22c by the conformal copper plating method, it is possible to thinly form the blind via 22c having a necessary and sufficient thickness in a shorter time than the case of forming by the hole filling copper plating method. As a result, further improvement in the throughput of the entire manufacturing process can be achieved. Further, by thinning the copper layer of the blind via 22c in this way, it is possible to further easily and reliably break the blind via 22c when the reinforcing copper layer 20 is peeled off. is there.

In general, a semiconductor integrated circuit (IC chip) 1, a heat spreader / stiffener (not shown) or the like is attached to the surface of the reinforced copper layer via an adhesive layer 2 made of an insulating epoxy resin or polymer. Therefore, there is no problem even if the copper on the bottom surface is exposed at the opening of the blind via 22a or the blind via 22c. However, when protection or insulation of this portion is necessary, a cover lay made of an insulating material or A solder resist (both not shown) may be applied or pasted on the part.
Further, as described above, the hole diameters of the blind vias 22a and 22c can be basically freely set. Therefore, the blind vias 22a and 22c can be formed as fine micro blind vias or the like if necessary. (Not shown) is set to a size that can be surely contacted, and after the tape carrier is completed, a probe for inspection is applied to the copper on the bottom surfaces of the blind vias 22a and 22c exposed on the reinforcing copper layer surface. It may be possible to perform a continuity test of the wiring pattern 12 and the connection pad 13 through the blind vias 22a and 22c by contacting them. As described above, each wiring pattern 12 is not connected by a conventional electrolytic plating power supply wiring and is independent, so that the blind vias 22a and 22c to which the probe is applied are appropriately selected. By using these, it is possible to perform a continuity test of such a wiring pattern 12 or the like.

The manufacturing method as described in the above embodiment was executed by a reel-to-reel manufacturing facility to manufacture a semiconductor device tape carrier.
A metal conductor material layer 16 made of copper foil having a thickness of 12 μm is laminated on the wiring layer surface of the insulating film substrate 17 made of polyimide film having a thickness of 25 μm, and a copper layer having a thickness of 1 μm is made on the reinforcing copper layer surface. A peelable material is used in which a copper base layer 18 and an intermediate metal layer 19 are formed, and a reinforced copper layer 20 having a thickness of 12 μm is peelably attached thereto.
A micro via having a hole diameter of 40 μm was drilled by a laser method to form a blind via hole 21. Blind vias 22a were formed by depositing 10 μm hole-filled copper 22 on the reinforced copper layer surface by electrolytic plating. An electrolytic gold / nickel plating layer 24 was formed by an electrolytic plating method using the reinforced copper layer 20, the copper layer 22b, and the blind via 22a as a power supply conductor. Then, the reinforcing copper layer 20 was peeled off, and the tape carrier for a semiconductor device was completed through the steps described in the above embodiment.
For comparison, a tape carrier for a semiconductor device was produced by an electroless gold / nickel plating method with the same specifications and circuit pattern settings as in this example.
And the ball shear test was done about each of the tape carrier for semiconductor devices of a present Example, and the tape carrier for semiconductor devices of a comparative example, and the result was compared and examined.

In the tape carrier for a semiconductor device of this example, the thickness of the electrolytic gold plating layer was 0.41 μm on average and the thickness of the electrolytic nickel plating layer was 1.7 μm on average. Moreover, in the tape carrier for semiconductor devices of the comparative example, the thickness of the electroless gold plating layer was 0.15 μm on average, and the thickness of the nickel plating layer was 4.5 μm on average. In both cases, the solder mask pattern 9 was provided with an opening having a diameter of 0.6 mm, and a gold / nickel plating layer was formed on the surface of the ball pad 11 or the like exposed from the opening. The ball bump 6 used for the ball shear test had a diameter of 0.81 μm, and this was mounted on the ball pad 11 and the shear strength was measured after repeating 230 ° C. reflow three times.

The result was as shown in FIG. Here, the horizontal axis in the graph of FIG. 7 indicates the shear force of the ball shear strength (scale in g (grams)), and the vertical axis indicates the generation of numerical values obtained from a plurality of measurement results. Each frequency is shown.
LSL (Lower Specification Limit) is a lower standard limit, and the value is set to the same 1000 g for both the example and the comparative example.
The bar graph with halftone dots in the graph is a graph in which the number of measurement points that fall within the ball shear strength range on the horizontal axis is plotted for each 100 g. The curve is a so-called distribution prediction line when the experimental result is assumed to follow a normal distribution.
On the right side of each graph, the average shear strength, standard deviation, and number of measurements are shown.
As a result of this test, it was confirmed that the ball shear strength of the tape carrier for a semiconductor device of this example was 1.4 times that in the comparative example using the electroless plating method, as is apparent from FIG. . In addition, Cpk when the lower standard limit value of the ball shear strength is set to 1000 g is also 3 or more, which is about 10 times that of 0.366 in the comparative example using the electroless plating method ( It was confirmed that the process capability (one digit higher) could be achieved.

It is sectional drawing which shows the structure of the principal part of the 1 metal circuit out type | mold BGA package produced using the tape carrier for semiconductor devices which concerns on this Embodiment. It is a top view of the tape carrier for semiconductor devices which concerns on this Embodiment. It is a figure which shows the peelable material used for manufacture of the tape carrier for semiconductor devices of FIG. It is a figure which shows the flow of the main processes in the manufacturing method of the tape carrier for semiconductor devices which concerns on this Embodiment. FIG. 5 is a diagram illustrating a flow of main processes in the method for manufacturing the tape carrier for a semiconductor device according to the present embodiment, following FIG. 4. It is a figure which shows an example of the variation of the tape carrier for semiconductor devices which concerns on this Embodiment, and its manufacturing method. It is a figure which shows the ball shear test result in the tape carrier for semiconductor devices which concerns on one Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 3 Tape carrier 11 for semiconductor devices Ball pad 12 Wiring pattern 13 Connection pad 14 Device hole 16 Metal conductor material layer 17 Insulating film substrate 20 Reinforcing copper layer 21 Blind via hole 22a Blind via 24 Electrolytic gold / nickel plating layer

Claims (7)

A wiring pattern and connection pads are formed on one of the front and back surfaces of the insulating film substrate,
An electrolytic plating layer is formed on the surface of at least the connection pad of the wiring pattern and the connection pad,
From the conductive material for feeding the electrolytic plating, connected to at least one of the wiring pattern and the connection pad from the surface opposite to the one surface on which the wiring pattern is formed in the insulating film substrate. Blind vias are provided,
A tape carrier for a semiconductor device, characterized in that no power supply wiring for electrolytic plating exists on both surfaces of the insulating film substrate. In the tape carrier for semiconductor devices according to claim 1,
The tape carrier for a semiconductor device, wherein the blind via is made of a conductive metal formed by conformal plating. In the tape carrier for semiconductor devices according to claim 1 or 2,
A tape carrier for a semiconductor device, wherein the electrolytic plating layer is an electrolytic gold plating layer or an electrolytic gold / nickel plating layer. The peelable layer in an insulating film substrate having a peelable layer made of a conductor material that has a metal conductor material layer for forming a wiring pattern and a connection pad on one side and is provided on a surface opposite to the one side. Drilling a blind via hole from the surface to the metal conductor material layer,
Forming a blind via made of a conductive material connected from the peelable layer through the blind via hole to the metal conductive material layer;
Patterning the metal conductor material layer to form a wiring pattern and connection pads;
Forming the electrolytic plating layer on the surface of at least one of the wiring pattern and the connection pad by an electrolytic plating method, using the peelable layer and the blind via as a power supply conductor for an electrolytic plating current;
A method of manufacturing a tape carrier for a semiconductor device, comprising: forming the peelable layer from the insulating film substrate after forming the electrolytic plating layer. In the manufacturing method of the tape carrier for semiconductor devices according to claim 4,
In addition to using the peelable layer as the power supply conductor, the tape carrier for a semiconductor device is also used as a reinforcing layer for reinforcing the mechanical strength of the tape carrier for the semiconductor device in the middle of manufacture. Production method. In the manufacturing method of the tape carrier for semiconductor devices according to claim 4 or 5,
A method of manufacturing a tape carrier for a semiconductor device, wherein the blind via is formed by conformal plating. In the manufacturing method of the tape carrier for semiconductor devices according to any one of claims 4 to 6,
A method of manufacturing a tape carrier for a semiconductor device, wherein the electrolytic plating layer is formed by an electrolytic gold plating method or an electrolytic gold / nickel plating method.

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