JP2008288236A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

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JP2008288236A
JP2008288236A JP2007128831A JP2007128831A JP2008288236A JP 2008288236 A JP2008288236 A JP 2008288236A JP 2007128831 A JP2007128831 A JP 2007128831A JP 2007128831 A JP2007128831 A JP 2007128831A JP 2008288236 A JP2008288236 A JP 2008288236A
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diode
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diodes
output terminal
semiconductor integrated
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JP5192726B2 (en
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Daisuke Kurihara
大介 栗原
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New Japan Radio Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which secondary harmonics are hardly generated and high-frequency characteristics are excellent. <P>SOLUTION: The semiconductor integrated circuit is provided with an electrostatic protection circuit in which a first diode connected in a forward direction and a second diode connected in a backward direction are connected in series between an input/output terminal and a ground terminal, the anode width of diodes and the number of connected diodes are set so as to cancel secondary harmonics to be generated from the first and second diodes, a bias voltage is applied to the diodes, and a resistive element is connected in parallel to the diodes. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、静電破壊から半導体集積回路を保護する静電保護回路を備えた半導体集積回路に関し、特に静電保護回路からの２次高調波の発生を抑制することができる半導体集積回路に関する。   The present invention relates to a semiconductor integrated circuit including an electrostatic protection circuit that protects a semiconductor integrated circuit from electrostatic breakdown, and more particularly to a semiconductor integrated circuit that can suppress the generation of second harmonics from the electrostatic protection circuit.

高周波用の半導体集積回路は静電耐圧が低い場合が多く、入出力端子と接地端子との間に保護ダイオードを用いた静電保護回路がしばしば用いられる。図９には、入出力端子に保護ダイオードを用いた静電保護回路を接続した従来の半導体集積回路の一例を示す。図９に示す静電保護回路は、高周波回路１の入出力端子２と接地端子３との間に、順方向に接続したダイオード４と逆方向に接続したダイオード５が直列に接続されている。このような半導体集積回路では、入出力端子２に直流電圧や交流電圧が加わってもダイオードには電流が流れず、サージ電圧のように高い電圧が加わったとき、ダイオード４とダイオード５がオン状態となり、電流が接地端子３に流れ、高周波回路１を静電破壊から保護することができる。この種の半導体集積回路は、例えば、特許文献１に開示されている。
特開２００２−５０６４０号公報 High-frequency semiconductor integrated circuits often have a low electrostatic withstand voltage, and an electrostatic protection circuit using a protection diode between an input / output terminal and a ground terminal is often used. FIG. 9 shows an example of a conventional semiconductor integrated circuit in which an electrostatic protection circuit using a protection diode is connected to an input / output terminal. In the electrostatic protection circuit shown in FIG. 9, a diode 4 connected in the forward direction and a diode 5 connected in the reverse direction are connected in series between the input / output terminal 2 and the ground terminal 3 of the high-frequency circuit 1. In such a semiconductor integrated circuit, even when a DC voltage or an AC voltage is applied to the input / output terminal 2, no current flows through the diode, and when a high voltage such as a surge voltage is applied, the diode 4 and the diode 5 are turned on. Thus, the current flows to the ground terminal 3, and the high frequency circuit 1 can be protected from electrostatic breakdown. This type of semiconductor integrated circuit is disclosed in, for example, Patent Document 1.
Japanese Patent Laid-Open No. 2002-50640

ところで、保護ダイオードを用いた静電保護回路を備えた半導体集積回路では、保護ダイオードから不要な高調波が発生することが知られている。図９に示す半導体集積回路では、入出力端子２が接地電位と同じ場合には、入力する高周波信号の正の周期と負の周期で、ダイオード４とダイオード５から発生する２次高調波が相互に打ち消し合い（相殺し）、入出力端子２に２次高調波はほとんど発生しない。しかし、入出力端子２に正の直流電圧が印加されている場合、ダイオード４は順バイアスされ、ダイオード５は逆バイアスされた状態となる。このような状態で高周波信号が入出力端子２に入力すると、正の周期と負の周期とで歪が異なり、入出力端子２に相殺されない２次高調波が残り、高周波特性を悪化させるという問題があった。本発明はこのような問題を解消し、静電保護回路で発生した２次高調波を相殺することができる静電保護回路を備えた半導体集積回路を提供することを目的とする。   Incidentally, it is known that unnecessary harmonics are generated from the protection diode in the semiconductor integrated circuit including the electrostatic protection circuit using the protection diode. In the semiconductor integrated circuit shown in FIG. 9, when the input / output terminal 2 is the same as the ground potential, the second harmonics generated from the diode 4 and the diode 5 are mutually in the positive cycle and the negative cycle of the input high-frequency signal. Are canceled (cancelled), and almost no second harmonic is generated at the input / output terminal 2. However, when a positive DC voltage is applied to the input / output terminal 2, the diode 4 is forward-biased and the diode 5 is reverse-biased. When a high-frequency signal is input to the input / output terminal 2 in such a state, the distortion differs between the positive period and the negative period, and second harmonics that are not canceled out by the input / output terminal 2 remain, thereby deteriorating the high-frequency characteristics. was there. It is an object of the present invention to provide a semiconductor integrated circuit including an electrostatic protection circuit that can solve such problems and cancel out the second harmonic generated in the electrostatic protection circuit.

上記目的を達成するため、本願請求項１に係る発明は、入出力端子を有する高周波回路と、前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように前記第１のダイオードのアノード幅と前記第２のダイオードのアノード幅をそれぞれ設定した静電保護回路と、を備えたことを特徴とする。   To achieve the above object, the invention according to claim 1 of the present application is a high-frequency circuit having an input / output terminal, and one or more first diodes connected in a forward direction between the input / output terminal and the ground terminal. And one or more second diodes connected in the opposite direction are connected in series, and the anode width of the first diode so as to cancel the second harmonic generated from the first and second diodes. And an electrostatic protection circuit in which the anode width of each of the second diodes is set.

本願請求項２に係る発明は、入出力端子を有する高周波回路と、前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように前記第１のダイオードの数と前記第２のダイオードの数をそれぞれ設定した静電保護回路と、を備えたことを特徴とする。   In the invention according to claim 2, the high-frequency circuit having the input / output terminal and one or more first diodes connected in the forward direction are connected in the reverse direction between the input / output terminal and the ground terminal. The number of the first diodes and the number of the second diodes are connected in series with one or more second diodes so as to cancel the second harmonic generated from the first and second diodes. And an electrostatic protection circuit in which each is set.

本願請求項３に係る発明は、入出力端子を有する高周波回路と、前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように前記第１のダイオードの数と前記第２のダイオードの数及び前記第１のダイオードのアノード幅と前記第２のダイオードのアノード幅をそれぞれ設定した静電保護回路と、を備えたことを特徴とする。   The invention according to claim 3 of the present application is connected in the reverse direction with a high-frequency circuit having an input / output terminal and one or more first diodes connected in the forward direction between the input / output terminal and the ground terminal. The number of the first diodes and the number of the second diodes are connected in series with one or more second diodes so as to cancel the second harmonic generated from the first and second diodes. And an electrostatic protection circuit in which the anode width of the first diode and the anode width of the second diode are respectively set.

本願請求項４に係る発明は、入出力端子を有する高周波回路と、前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように少なくとも２つの前記ダイオードの接続点にバイアス電圧を印加する手段を備えた静電保護回路と、を備えたことを特徴とする。   In the invention according to claim 4 of the present application, a high-frequency circuit having an input / output terminal, and one or more first diodes connected in the forward direction between the input / output terminal and the ground terminal are connected in the reverse direction. Means for connecting one or more second diodes in series and applying a bias voltage to the connection point of at least two of the diodes so as to cancel second harmonics generated from the first and second diodes And an electrostatic protection circuit comprising:

本願請求項５に係る発明は、入出力端子を有する高周波回路と、前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記ダイオードに並列に抵抗素子を接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように前記抵抗素子の抵抗値を設定した静電保護回路と、を備えたことを特徴とする。   In the invention according to claim 5 of the present application, a high-frequency circuit having an input / output terminal, and one or more first diodes connected in the forward direction between the input / output terminal and the ground terminal are connected in the reverse direction. One or more second diodes are connected in series, a resistance element is connected in parallel to the diode, and the resistance element of the resistance element is canceled so as to cancel the second harmonic generated from the first and second diodes. And an electrostatic protection circuit in which a resistance value is set.

本発明によれば、静電保護回路が接続されている入出力端子に正の直流電圧が印加されている場合であっても、順方向に接続した１個以上の第１のダイオードから発生する２次高調波と逆方向に接続した１個以上の第２のダイオードから発生する２次高調波が、正の周期と負の周期で相殺され、入出力端子に２次高調波はほとんど発生しない。   According to the present invention, even when a positive DC voltage is applied to the input / output terminal to which the electrostatic protection circuit is connected, it is generated from one or more first diodes connected in the forward direction. Secondary harmonics generated from one or more second diodes connected in the opposite direction to the secondary harmonics cancel each other out in a positive cycle and a negative cycle, and almost no secondary harmonics are generated at the input / output terminals. .

具体的に本発明では、静電保護回路を構成するダイオードのアノード幅や接続するダイオードの数を、所定の幅や数に設定する。またダイオードに所定のバイアス電圧を印加する。さらに所定の抵抗値の抵抗素子をダイオードと並列に接続する。このような静電保護回路は、従来の静電保護回路をわずかに変更するだけで良く、非常に簡便な構成で大きな効果が得られるという利点もある。   Specifically, in the present invention, the anode width of the diode constituting the electrostatic protection circuit and the number of connected diodes are set to a predetermined width and number. A predetermined bias voltage is applied to the diode. Further, a resistance element having a predetermined resistance value is connected in parallel with the diode. Such an electrostatic protection circuit requires only a slight modification of the conventional electrostatic protection circuit, and has an advantage that a great effect can be obtained with a very simple configuration.

本発明の半導体集積回路は、２次高調波の発生がほとんどなく、高周波特性の優れた半導体集積回路を提供することができる。   The semiconductor integrated circuit of the present invention can provide a semiconductor integrated circuit that has almost no generation of the second harmonic and has excellent high frequency characteristics.

以下、本発明の半導体集積回路について、詳細に説明する。   Hereinafter, the semiconductor integrated circuit of the present invention will be described in detail.

図１は本発明の第１の実施例の説明図である。図１に示すように、静電保護回路は、高周波回路１の入出力端子２と接地端子３との間に、順方向に接続したダイオード４（請求項１の第１のダイオードに相当）と、逆方向に接続したダイオード５（請求項１の第２のダイオードに相当）が直列に接続した構成となっている。ここで、本実施例の静電保護回路では、ダイオード４のアノード幅とダイオード５のアノード幅が異なる構成となっている。   FIG. 1 is an explanatory diagram of a first embodiment of the present invention. As shown in FIG. 1, the electrostatic protection circuit includes a diode 4 (corresponding to the first diode of claim 1) connected in the forward direction between the input / output terminal 2 and the ground terminal 3 of the high-frequency circuit 1. The diode 5 connected in the reverse direction (corresponding to the second diode of claim 1) is connected in series. Here, in the electrostatic protection circuit of the present embodiment, the anode width of the diode 4 and the anode width of the diode 5 are different.

このような構成の半導体集積回路では、従来の静電保護回路同様、入出力端子２に交流信号が入力されてもダイオードには電流が流れない。一方、サージ電圧のように高い電圧が加わるとダイオードを介して接地端子に電流が流れ、静電破壊を防止することができる。   In the semiconductor integrated circuit having such a configuration, like the conventional electrostatic protection circuit, even if an AC signal is input to the input / output terminal 2, no current flows through the diode. On the other hand, when a high voltage such as a surge voltage is applied, a current flows to the ground terminal via the diode, and electrostatic breakdown can be prevented.

入出力端子２に正の直流バイアスを印加した場合、ダイオード４は順バイアスされ、ダイオード５は逆バイアスされる。本実施例では、ダイオード４とダイオード５のアノード幅を、このバイアス状態で入出力端子２に高周波信号が入力したとき、それぞれのダイオードから発生する２次高調波が入力信号の正の周期と負の周期で相殺されるように設定する。設定方法は、バイアス条件等を考慮したシミュレーションによる。   When a positive DC bias is applied to the input / output terminal 2, the diode 4 is forward biased and the diode 5 is reverse biased. In this embodiment, when the high-frequency signal is input to the input / output terminal 2 in this bias state, the second harmonics generated from the respective diodes are negative and negative in the input signal. It is set so that it is canceled out with a period of. The setting method is based on simulation in consideration of bias conditions and the like.

具体的には、入出力端子２を３Ｖにバイアスし、ダイオード４のアノード幅を大きくしたとき、入出力端子に発生する２次高調波のシミュレーション結果を図２に示す。ダイオード４のアノード幅をダイオード５のアノード幅の２．５倍程度にした時、２次高調波が大幅に抑制できることがわかる。なお、図９で説明した静電保護回路において、ダイオード４、５のアノード幅を共に大きくした場合についても同様のシミュレーションを行った結果を図１０に示す。図１０に示すように、ダイオードのアノード幅を単に大きくするだけでは、２次高調波の発生は抑制できなかった。   Specifically, FIG. 2 shows a simulation result of the second harmonic generated at the input / output terminal when the input / output terminal 2 is biased to 3V and the anode width of the diode 4 is increased. It can be seen that when the anode width of the diode 4 is about 2.5 times the anode width of the diode 5, the second harmonic can be significantly suppressed. In the electrostatic protection circuit described with reference to FIG. 9, FIG. 10 shows the result of the same simulation performed when both the anode widths of the diodes 4 and 5 are increased. As shown in FIG. 10, the generation of the second harmonic could not be suppressed simply by increasing the anode width of the diode.

以上説明したように、直列に接続したダイオードのアノード幅を所定の値に設定することで、２次高調波の発生を抑制できることが確認された。このような２次高調波の抑制効果は、ダイオード４のアノード幅をダイオード５のアノード幅より大きくする場合に限らず、逆にダイオード５のアノード幅をダイオード４のアノード幅より大きくしても良い。アノード幅の比率は、入出力端子のバイアス電圧、ダイオードの特性等によって決定されるので、半導体集積回路の動作に応じて、最適な条件に設定すればよい。   As described above, it was confirmed that the generation of the second harmonic can be suppressed by setting the anode width of the diodes connected in series to a predetermined value. Such a suppression effect of the second harmonic is not limited to the case where the anode width of the diode 4 is made larger than the anode width of the diode 5, and conversely, the anode width of the diode 5 may be made larger than the anode width of the diode 4. . Since the ratio of the anode width is determined by the bias voltage of the input / output terminal, the characteristics of the diode, and the like, it may be set to an optimum condition according to the operation of the semiconductor integrated circuit.

なお、交流信号の振幅が大きく、ダイオードに電流が流れてしまう場合には、ダイオードを複数直列に接続させればよく、その場合もそれぞれのダイオードのアノード幅は、シミュレーションから最適な条件を設定することができる。   If the amplitude of the AC signal is large and current flows through the diode, a plurality of diodes may be connected in series. In this case, the anode width of each diode is set to an optimum condition from simulation. be able to.

図３は本発明の第２の実施例の説明図である。図３に示すように、静電保護回路は、高周波回路１の入出力端子２と接地端子３との間に、順方向に接続したダイオード４（請求項２の第１のダイオードに相当）と、逆方向に接続したダイオード５及びダイオード６（請求項２の第２のダイオードに相当）が直列に接続した構成となっている。ここで、本実施例の静電保護回路では、順方向に接続したダイオードの数と逆方向に接続したダイオードの数が異なる構成となっている。   FIG. 3 is an explanatory diagram of the second embodiment of the present invention. As shown in FIG. 3, the electrostatic protection circuit includes a diode 4 (corresponding to the first diode of claim 2) connected in the forward direction between the input / output terminal 2 and the ground terminal 3 of the high-frequency circuit 1. The diode 5 and the diode 6 (corresponding to the second diode of claim 2) connected in the opposite direction are connected in series. Here, in the electrostatic protection circuit of the present embodiment, the number of diodes connected in the forward direction is different from the number of diodes connected in the reverse direction.

このような構成の半導体集積回路では、従来の静電保護回路同様、入出力端子２に交流信号が入力されてもダイオードには電流が流れない。一方、サージ電圧のように高い電圧が加わるとダイオードを介して接地端子に電流が流れ、静電破壊を防止することができる。   In the semiconductor integrated circuit having such a configuration, like the conventional electrostatic protection circuit, even if an AC signal is input to the input / output terminal 2, no current flows through the diode. On the other hand, when a high voltage such as a surge voltage is applied, a current flows to the ground terminal via the diode, and electrostatic breakdown can be prevented.

入出力端子２に正の直流バイアスを印加した場合、ダイオード４は順バイアスされ、ダイオード５及びダイオード６は逆バイアスされる。本実施例では、順方向に接続したダイオードの数と逆方向に接続したダイオードの数を、このバイアス状態で入出力端子２に高周波信号が入力したとき、それぞれのダイオードから発生する２次高調波が入力信号の正の周期と負の周期で相殺されるように設定する。設定方法は、バイアス条件等を考慮したシミュレーションによる。   When a positive DC bias is applied to the input / output terminal 2, the diode 4 is forward-biased, and the diode 5 and the diode 6 are reverse-biased. In this embodiment, the number of diodes connected in the forward direction and the number of diodes connected in the reverse direction are the second harmonic generated from each diode when a high frequency signal is input to the input / output terminal 2 in this bias state. Is set so as to cancel out in the positive and negative periods of the input signal. The setting method is based on simulation in consideration of bias conditions and the like.

具体的には、入出力端子２を３Ｖにバイアスし、図３に示す半導体集積回路の入力端子に発生する２次高調波のシミュレーション結果は、−１１２ｄＢｃであった（図４において、順方向のアノード幅が１の場合に相当）。図９で説明した静電保護回路において、ダイオードの数が１個ずつ（同一）である場合のシミュレーション結果は、−９５ｄＢｃであり（ダイオードのアノード幅が１の場合に相当）ダイオードの数を変えることで、２次高調波を抑制できることがわかる。   Specifically, the input / output terminal 2 is biased to 3 V, and the simulation result of the second harmonic generated at the input terminal of the semiconductor integrated circuit shown in FIG. 3 is −112 dBc (in FIG. Equivalent to an anode width of 1). In the electrostatic protection circuit described with reference to FIG. 9, the simulation result when the number of diodes is one by one (same) is −95 dBc (corresponding to the case where the anode width of the diode is 1), and the number of diodes is changed. This shows that the second harmonic can be suppressed.

以上説明したように、順方向に接続したダイオードの数と逆方向に接続したダイオードの数を変えることで、２次高調波の発生を抑制できることが確認された。このような２次高調波の抑制効果は、順方向に接続したダイオードの数より逆方向に接続したダイオードの数を大きくする場合に限らず、逆に順方向に接続したダイオードの数を多くしても良い。しかしながら、直列に接続されるダイオードの数が増えれば、高調波の発生は低減できるものの、静電保護回路であるためには、保護する高周波回路の静電耐圧より耐圧が低くなければならない。本実施例の場合、マイナスのサージが印加した場合、静電保護回路の耐圧はダイオード４の逆耐圧で決まる。従って、図３に示すように順方向に接続したダイオードの数を逆方向に接続したダイオードの数より少なくすると、より低い静電耐圧の高周波回路を保護することができ、好適である。   As described above, it was confirmed that the generation of second harmonics can be suppressed by changing the number of diodes connected in the forward direction and the number of diodes connected in the reverse direction. Such a second harmonic suppression effect is not limited to the case where the number of diodes connected in the reverse direction is made larger than the number of diodes connected in the forward direction, but conversely, the number of diodes connected in the forward direction is increased. May be. However, if the number of diodes connected in series increases, the generation of harmonics can be reduced, but in order to be an electrostatic protection circuit, the withstand voltage must be lower than the electrostatic withstand voltage of the high-frequency circuit to be protected. In the present embodiment, when a negative surge is applied, the withstand voltage of the electrostatic protection circuit is determined by the reverse withstand voltage of the diode 4. Therefore, it is preferable that the number of diodes connected in the forward direction is smaller than the number of diodes connected in the reverse direction as shown in FIG.

次に第３の実施例について説明する。前述の第２の実施例では、ダイオードのアノード幅は一定である場合について説明したが、図３に示す構成において、さらに順方向に接続したダイオードのアノード幅と逆方向に接続したダイオードのアノード幅が異なる構成とすることもできる。   Next, a third embodiment will be described. In the above-described second embodiment, the case where the anode width of the diode is constant has been described. However, in the configuration shown in FIG. 3, the anode width of the diode further connected in the reverse direction to the anode width of the diode connected in the forward direction is further described. It is also possible to adopt different configurations.

このような構成の半導体集積回路では、従来の静電保護回路同様、入出力端子２に交流信号が入力されてもダイオードには電流が流れない。一方、サージ電圧のように高い電圧が加わるとダイオードを介して接地端子に電流が流れ、静電破壊を防止することができる。   In the semiconductor integrated circuit having such a configuration, like the conventional electrostatic protection circuit, even if an AC signal is input to the input / output terminal 2, no current flows through the diode. On the other hand, when a high voltage such as a surge voltage is applied, a current flows to the ground terminal via the diode, and electrostatic breakdown can be prevented.

入出力端子２に正の直流バイアスを印加した場合、ダイオード４は順バイアスされ、ダイオード５及びダイオード６は逆バイアスされる。本実施例では、順方向に接続したダイオードの数と逆方向に接続したダイオードの数、及びダイオードのアノード幅を、このバイアス状態で入出力端子２に高周波信号が入力したとき、それぞれのダイオードから発生する２次高調波が入力信号の正の周期と負の周期で相殺されるように設定する。設定方法は、バイアス条件等を考慮したシミュレーションによる。   When a positive DC bias is applied to the input / output terminal 2, the diode 4 is forward-biased, and the diode 5 and the diode 6 are reverse-biased. In the present embodiment, the number of diodes connected in the forward direction, the number of diodes connected in the reverse direction, and the anode width of the diode are determined from the respective diodes when a high frequency signal is input to the input / output terminal 2 in this bias state. It is set so that the generated second-order harmonics are canceled out in the positive cycle and the negative cycle of the input signal. The setting method is based on simulation in consideration of bias conditions and the like.

具体的には、入出力端子２を３Ｖにバイアスし、図３に示す半導体集積回路においてダイオード４のアノード幅を大きくしたとき、入出力端子に発生する２次高調波のシミュレーション結果を図４に示す。ダイオード４のアノード幅をダイオード５、６のアノード幅の１．３倍程度にしたとき、２次高調波を大幅に抑制できることがわかる。   Specifically, when the input / output terminal 2 is biased to 3V and the anode width of the diode 4 is increased in the semiconductor integrated circuit shown in FIG. 3, the simulation result of the second harmonic generated at the input / output terminal is shown in FIG. Show. It can be seen that when the anode width of the diode 4 is about 1.3 times the anode width of the diodes 5 and 6, the second harmonic can be significantly suppressed.

以上説明したように、順方向に接続したダイオードの数と逆方向に接続したダイオードの数、ダイオード４のアノード幅を所定の大きさとすることで、２次高調波の発生を抑制できることが確認された。このような２次高調波の抑制効果は、本実施例に限らず、例えばダイオード５のアノード幅をダイオード４のアノード幅より大きくしても良い。アノード幅の比率は、入出力端子のバイアス電圧、ダイオードの特性等によって決定されるので、半導体集積回路の動作に応じて、最適な条件に設定すればよい。また、順方向に接続したダイオードの数を多くしても良い。しかしながら、直列に接続されるダイオードの数が増えれば、高調波の発生は低減できるものの、静電保護回路であるためには、保護する高周波回路の静電耐圧より耐圧が低くなければならない。本実施例の場合、マイナスのサージが印加した場合、静電保護回路の耐圧はダイオード４の逆耐圧で決まる。従って、図３に示すように順方向に接続したダイオードの数を逆方向に接続したダイオードの数より少なくすると、より低い静電耐圧の高周波回路を保護することができ、好適である。   As described above, it is confirmed that the generation of the second harmonic can be suppressed by setting the number of diodes connected in the forward direction, the number of diodes connected in the reverse direction, and the anode width of the diode 4 to a predetermined size. It was. Such an effect of suppressing the second harmonic is not limited to the present embodiment. For example, the anode width of the diode 5 may be larger than the anode width of the diode 4. Since the ratio of the anode width is determined by the bias voltage of the input / output terminal, the characteristics of the diode, and the like, it may be set to an optimum condition according to the operation of the semiconductor integrated circuit. Further, the number of diodes connected in the forward direction may be increased. However, if the number of diodes connected in series increases, the generation of harmonics can be reduced, but in order to be an electrostatic protection circuit, the withstand voltage must be lower than the electrostatic withstand voltage of the high-frequency circuit to be protected. In the present embodiment, when a negative surge is applied, the withstand voltage of the electrostatic protection circuit is determined by the reverse withstand voltage of the diode 4. Therefore, it is preferable that the number of diodes connected in the forward direction is smaller than the number of diodes connected in the reverse direction as shown in FIG.

図５は本発明の第４の実施例の説明図である。図５に示すように、静電保護回路は、高周波回路１の入出力端子２と接地端子３との間に、順方向に接続したダイオード４（請求項４の第１のダイオードに相当）と、逆方向に接続したダイオード５及びダイオード６（請求項４の第２のダイオードに相当）が直列に接続した構成となっている。ここで、本実施例の静電保護回路では、ダイオード４とダイオード５の間にバイアス端子７を、ダイオード５とダイオード６の間に別のバイアス端子８を設け、図示しないバイアス印加手段からバイアス電圧を印加する構成となっている。   FIG. 5 is an explanatory diagram of the fourth embodiment of the present invention. As shown in FIG. 5, the electrostatic protection circuit includes a diode 4 (corresponding to a first diode in claim 4) connected in the forward direction between the input / output terminal 2 and the ground terminal 3 of the high-frequency circuit 1. The diode 5 and the diode 6 (corresponding to the second diode of claim 4) connected in the reverse direction are connected in series. Here, in the electrostatic protection circuit of the present embodiment, a bias terminal 7 is provided between the diode 4 and the diode 5, and another bias terminal 8 is provided between the diode 5 and the diode 6. Is applied.

このような構成の半導体集積回路では、従来の静電保護回路同様、入出力端子２に交流信号が入力されてもダイオードには電流が流れない。一方、サージ電圧のように高い電圧が加わるとダイオードを介して接地端子に電流が流れ、静電破壊を防止することができる。   In the semiconductor integrated circuit having such a configuration, like the conventional electrostatic protection circuit, even if an AC signal is input to the input / output terminal 2, no current flows through the diode. On the other hand, when a high voltage such as a surge voltage is applied, a current flows to the ground terminal via the diode, and electrostatic breakdown can be prevented.

入出力端子２に正の直流バイアスを印加した場合、ダイオード４は順バイアスされ、ダイオード５及びダイオード６は逆バイアスされる。本実施例では、バイアス端子７、８に印加するバイアス電圧を、このバイアス状態で入出力端子２に高周波信号が入力したとき、それぞれのダイオードから発生する２次高調波が入力信号の正の周期と負の周期で相殺されるように設定する。設定方法は、入出力端子のバイアス条件等を考慮したシミュレーションによる。   When a positive DC bias is applied to the input / output terminal 2, the diode 4 is forward-biased, and the diode 5 and the diode 6 are reverse-biased. In this embodiment, when a bias voltage applied to the bias terminals 7 and 8 is input to the input / output terminal 2 in this bias state, the second harmonic generated from each diode is a positive period of the input signal. And set to cancel in a negative cycle. The setting method is based on simulation considering the bias conditions of the input / output terminals.

具体的には、入出力端子２に３Ｖをバイアスし、図５に示す半導体集積回路においてバイアス端子８に印加するバイアス電圧を変化させたとき、入出力端子に発生する２次高調波のシミュレーション結果を図６に示す。バイアス端子８に印加するバイアス電圧を２．８Ｖ程度にしたとき、２次高調波を大幅に抑制できることがわかる。   Specifically, the simulation result of the second harmonic generated at the input / output terminal when 3V is biased to the input / output terminal 2 and the bias voltage applied to the bias terminal 8 is changed in the semiconductor integrated circuit shown in FIG. Is shown in FIG. It can be seen that when the bias voltage applied to the bias terminal 8 is about 2.8 V, the second harmonic can be significantly suppressed.

以上説明したように、バイアス端子８に印加するバイアス電圧を所定の値に設定することで、２次高調波の発生を抑制できることが確認された。このような２次高調波の抑制効果は、バイアス端子８にバイアス電圧を印加する場合に限らず、バイアス端子７、８のいずれか、あるいは両方にバイアス電圧を印加する構成としたり、直列に接続するダイオードの数を増やし、バイアス端子の数を増やしたり種々変更しても良い。バイアス端子に印加するバイアス電圧は、入出力端子のバイアス電圧、ダイオードの特性等によって決定されるので、半導体集積回路の動作に応じて、最適な条件に設定すればよい。   As described above, it was confirmed that the generation of the second harmonic can be suppressed by setting the bias voltage applied to the bias terminal 8 to a predetermined value. Such an effect of suppressing the second harmonic is not limited to the case where a bias voltage is applied to the bias terminal 8, but a configuration in which a bias voltage is applied to one or both of the bias terminals 7 and 8, or a series connection is made. The number of diodes may be increased, the number of bias terminals may be increased, or various changes may be made. Since the bias voltage applied to the bias terminal is determined by the bias voltage of the input / output terminal, the characteristics of the diode, and the like, it may be set to an optimum condition according to the operation of the semiconductor integrated circuit.

図７は本発明の第５の実施例の説明図である。図７に示すように、静電保護回路は、高周波回路１の入出力端子２と接地端子３との間に、順方向に接続したダイオード４（請求項５の第１のダイオードに相当）と、逆方向に接続したダイオード５、ダイオード６（請求項５の第２のダイオードに相当）が直列に接続した構成となっている。ここで、本実施例の静電保護回路では、ダイオード４、５、６それぞれに並列に抵抗素子９、１０、１１を接続する構成となっている。   FIG. 7 is an explanatory diagram of the fifth embodiment of the present invention. As shown in FIG. 7, the electrostatic protection circuit includes a diode 4 (corresponding to the first diode of claim 5) connected in the forward direction between the input / output terminal 2 and the ground terminal 3 of the high-frequency circuit 1. The diode 5 and the diode 6 (corresponding to the second diode of claim 5) connected in the reverse direction are connected in series. Here, in the electrostatic protection circuit of this embodiment, the resistance elements 9, 10, and 11 are connected in parallel to the diodes 4, 5, and 6, respectively.

このような構成の半導体集積回路では、従来の静電保護回路同様、入出力端子２に交流信号が入力されてもダイオードには電流が流れない。一方、サージ電圧のように高い電圧が加わるとダイオードを介して接地端子に電流が流れ、静電破壊を防止することができる。   In the semiconductor integrated circuit having such a configuration, like the conventional electrostatic protection circuit, even if an AC signal is input to the input / output terminal 2, no current flows through the diode. On the other hand, when a high voltage such as a surge voltage is applied, a current flows to the ground terminal via the diode, and electrostatic breakdown can be prevented.

入出力端子２に正の直流バイアスを印加した場合、ダイオード４は順バイアスされ、ダイオード５及びダイオード６は逆バイアスされる。本実施例では、抵抗素子９、１０、１１の抵抗値を、このバイアス状態で入出力端子２に高周波信号が入力したとき、それぞれのダイオードから発生する２次高調波が入力信号の正の周期と負の周期で相殺させるように設定する。設定方法は、入出力端子のバイアス条件等を考慮したシミュレーションによる。   When a positive DC bias is applied to the input / output terminal 2, the diode 4 is forward-biased, and the diode 5 and the diode 6 are reverse-biased. In this embodiment, when a high frequency signal is input to the input / output terminal 2 in this bias state with respect to the resistance values of the resistance elements 9, 10, and 11, the second harmonic generated from each diode is a positive period of the input signal. And set to cancel in a negative cycle. The setting method is based on simulation considering the bias conditions of the input / output terminals.

具体的には、入出力端子２に３Ｖをバイアスし、図７に示す半導体集積回路において抵抗素子９の抵抗値を５ｋΩ、抵抗素子１０の抵抗値を１０ｋΩとし、抵抗素子１１の抵抗値を変化させたとき、入出力端子に発生する２次高調波のシミュレーション結果を図８に示す。抵抗素子１１の抵抗値を２４０ｋΩ程度としたとき、２次高調波を大幅に抑制できることがわかる。   Specifically, the input / output terminal 2 is biased with 3 V, the resistance value of the resistance element 9 is 5 kΩ, the resistance value of the resistance element 10 is 10 kΩ in the semiconductor integrated circuit shown in FIG. FIG. 8 shows the simulation result of the second harmonic generated at the input / output terminal when the frequency is set. It can be seen that when the resistance value of the resistance element 11 is about 240 kΩ, the second harmonic can be significantly suppressed.

以上説明したように、抵抗素子１１の抵抗値を所定の値に設定することで、２次高調波の発生を抑制できることが確認された。このような２次高調波の抑制効果は、抵抗素子１１の抵抗値が変化させる場合に限らず、抵抗素子９、１０の抵抗値を変化させる等種々変更しても良い。抵抗素子の抵抗値は、バイアス電圧、ダイオードの特定等によって決定されるので、半導体集積回路の動作に応じて、最適な条件に設定すればよい。   As described above, it was confirmed that the generation of the second harmonic can be suppressed by setting the resistance value of the resistance element 11 to a predetermined value. Such an effect of suppressing the second harmonic is not limited to the case where the resistance value of the resistance element 11 is changed, but may be variously changed such as changing the resistance value of the resistance elements 9 and 10. Since the resistance value of the resistance element is determined by the bias voltage, the specification of the diode, and the like, it may be set to an optimum condition according to the operation of the semiconductor integrated circuit.

本発明の第１の実施例の説明図である。It is explanatory drawing of the 1st Example of this invention. 本発明の第１の実施例で入出力端子に発生する２次高調波のシミュレーション結果である。It is a simulation result of the 2nd harmonic generated in an input / output terminal in the 1st example of the present invention. 本発明の第２の実施例の説明図である。It is explanatory drawing of the 2nd Example of this invention. 本発明の第２の実施例及び第３の実施例で入出力端子に発生する２次高調波のシミュレーション結果である。It is a simulation result of the 2nd harmonic generated in an input-output terminal in the 2nd example and the 3rd example of the present invention. 本発明の第４の実施例を示す図である。It is a figure which shows the 4th Example of this invention. 本発明の第４の実施例で入出力端子に発生する２次高調波のシミュレーション結果である。It is a simulation result of the 2nd harmonic generated in an input / output terminal in the 4th example of the present invention. 本発明の第５の実施例を示す図である。It is a figure which shows the 5th Example of this invention. 本発明の第５の実施例で入出力端子に発生する２次高調波のシミュレーション結果である。It is a simulation result of the 2nd harmonic generated in an input / output terminal in the 5th example of the present invention. 従来の半導体集積回路の説明図である。It is explanatory drawing of the conventional semiconductor integrated circuit. 従来の半導体集積回路の２次高調波のシミュレーション結果である。It is a simulation result of the second harmonic of the conventional semiconductor integrated circuit.

符号の説明Explanation of symbols

１：高周波回路
２：入出力端子
３：接地端子
４、５、６：ダイオード
７、８：バイアス端子
９、１０、１１：抵抗 1: High frequency circuit 2: Input / output terminal 3: Ground terminals 4, 5, 6: Diode 7, 8: Bias terminals 9, 10, 11: Resistance

Claims (5)

入出力端子を有する高周波回路と、
前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように前記第１のダイオードのアノード幅と前記第２のダイオードのアノード幅をそれぞれ設定した静電保護回路と、
を備えたことを特徴とする半導体集積回路。 A high frequency circuit having input and output terminals;
Between the input / output terminal and the ground terminal, one or more first diodes connected in the forward direction and one or more second diodes connected in the reverse direction are connected in series, and the first And an electrostatic protection circuit in which the anode width of the first diode and the anode width of the second diode are respectively set so as to cancel the second harmonic generated from the second diode,
A semiconductor integrated circuit comprising: 入出力端子を有する高周波回路と、
前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように前記第１のダイオードの数と前記第２のダイオードの数をそれぞれ設定した静電保護回路と、
を備えたことを特徴とする半導体集積回路。 A high frequency circuit having input and output terminals;
Between the input / output terminal and the ground terminal, one or more first diodes connected in the forward direction and one or more second diodes connected in the reverse direction are connected in series, and the first And an electrostatic protection circuit in which the number of the first diodes and the number of the second diodes are set so as to cancel the second harmonic generated from the second diode,
A semiconductor integrated circuit comprising: 入出力端子を有する高周波回路と、
前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように前記第１のダイオードの数と前記第２のダイオードの数及び前記第１のダイオードのアノード幅と前記第２のダイオードのアノード幅をそれぞれ設定した静電保護回路と、
を備えたことを特徴とする半導体集積回路。 A high frequency circuit having input and output terminals;
Between the input / output terminal and the ground terminal, one or more first diodes connected in the forward direction and one or more second diodes connected in the reverse direction are connected in series, and the first And the number of the first diodes, the number of the second diodes, the anode width of the first diode, and the anode width of the second diode so as to cancel out the second harmonic generated from the second diode. Each with an electrostatic protection circuit
A semiconductor integrated circuit comprising: 入出力端子を有する高周波回路と、
前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように少なくとも２つの前記ダイオードの接続点にバイアス電圧を印加する手段を備えた静電保護回路と、
を備えたことを特徴とする半導体集積回路。 A high frequency circuit having input and output terminals;
Between the input / output terminal and the ground terminal, one or more first diodes connected in the forward direction and one or more second diodes connected in the reverse direction are connected in series, and the first And an electrostatic protection circuit comprising means for applying a bias voltage to the connection point of at least two of the diodes so as to cancel the second harmonic generated from the second diode;
A semiconductor integrated circuit comprising: 入出力端子を有する高周波回路と、
前記入出力端子と接地端子との間に、順方向に接続した１個以上の第１のダイオードと、逆方向に接続した１個以上の第２のダイオードとを直列に接続し、前記ダイオードに並列に抵抗素子を接続し、前記第１及び第２のダイオードから発生する２次高調波を相殺するように前記抵抗素子の抵抗値を設定した静電保護回路と、
を備えていることを特徴とする半導体集積回路。 A high frequency circuit having input and output terminals;
One or more first diodes connected in the forward direction and one or more second diodes connected in the reverse direction are connected in series between the input / output terminal and the ground terminal, An electrostatic protection circuit in which a resistance element is connected in parallel, and a resistance value of the resistance element is set so as to cancel second harmonics generated from the first and second diodes;
A semiconductor integrated circuit comprising:
JP2007128831A 2007-05-15 2007-05-15 Semiconductor integrated circuit Expired - Fee Related JP5192726B2 (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011037101A1 (en) * 2009-09-24 2011-03-31 株式会社村田製作所 Electronic circuit device
WO2019015076A1 (en) * 2017-07-21 2019-01-24 惠科股份有限公司 Driving device for display panel
JP2021522691A (en) * 2018-05-04 2021-08-30 ロベルト・ボッシュ・ゲゼルシャフト・ミト・ベシュレンクテル・ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ Protection circuit against electrostatic discharge
US12009358B2 (en) 2018-05-04 2024-06-11 Robert Bosch Gmbh Protective circuit against electrostatic discharges

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JP2004320682A (en) * 2002-08-16 2004-11-11 Advanced Telecommunication Research Institute International Design method of array antenna, variable reactance circuit, and electronic circuit
JP2007013031A (en) * 2005-07-04 2007-01-18 Toshiba Corp High-frequency semiconductor circuit and radio communication equipment
JP2007042793A (en) * 2005-08-02 2007-02-15 New Japan Radio Co Ltd Semiconductor device

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JP2004320682A (en) * 2002-08-16 2004-11-11 Advanced Telecommunication Research Institute International Design method of array antenna, variable reactance circuit, and electronic circuit
JP2007013031A (en) * 2005-07-04 2007-01-18 Toshiba Corp High-frequency semiconductor circuit and radio communication equipment
JP2007042793A (en) * 2005-08-02 2007-02-15 New Japan Radio Co Ltd Semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011037101A1 (en) * 2009-09-24 2011-03-31 株式会社村田製作所 Electronic circuit device
WO2019015076A1 (en) * 2017-07-21 2019-01-24 惠科股份有限公司 Driving device for display panel
US11322931B2 (en) 2017-07-21 2022-05-03 HKC Corporation Driving device of display panel
JP2021522691A (en) * 2018-05-04 2021-08-30 ロベルト・ボッシュ・ゲゼルシャフト・ミト・ベシュレンクテル・ハフツングＲｏｂｅｒｔ Ｂｏｓｃｈ Ｇｍｂｈ Protection circuit against electrostatic discharge
JP7133035B2 (en) 2018-05-04 2022-09-07 ロベルト・ボッシュ・ゲゼルシャフト・ミト・ベシュレンクテル・ハフツング Protection circuit against electrostatic discharge
US12009358B2 (en) 2018-05-04 2024-06-11 Robert Bosch Gmbh Protective circuit against electrostatic discharges

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