JP2008287094A - Display panel driving device and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new method for obtaining a horizontal zoom function in an output video with respect to a display panel driving device and a display device with the display panel driving device. <P>SOLUTION: The display panel driving device is equipped with: a horizontal synchronizing circuit generating a pulse signal synchronized with a horizontal synchronizing signal; a phase comparing circuit comparing phases of the pulse signal with a phase comparing signal; a frequency control circuit generating a frequency control signal so as to control the frequency of a clock signal based on the result of comparing phases; a modulation signal generating circuit generating a frequency modulating signal to modulate the frequency of the clock signal synchronized with the horizontal synchronizing signal; a modulation signal adding circuit adding the frequency modulating signal to the frequency control signal; an oscillator oscillating the clock signal according to the frequency control signal with addition of the frequency modulating signal; and a frequency dividing circuit dividing the clock signal to generate the phase comparing signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display panel driving device and a display device.

  An example of a liquid crystal panel driving method is analog panel driving. In analog panel driving, a video signal is sampled by a sampling clock, and the sampled video is output to a liquid crystal panel. The video signal includes, for example, primary color signals such as R signal, G signal, and B signal, and synchronization signals such as horizontal synchronization signal and vertical synchronization signal. When sampling, the sampling points are equally spaced and the number of samplings is the same as the number of panel pixels, so that the sampled video is output at the same magnification in the horizontal direction.

  At this time, the output video can be compressed / expanded for each region in the horizontal direction by changing the interval between the sampling points for each region without changing the number of samplings. For example, in a region where sampling points are densely taken, the video signal is sampled in small increments, so the output video is expanded in the horizontal direction, and in a region where sampling points are sparsely taken, the video signal is greatly divided. Therefore, the output video is compressed in the horizontal direction. In the analog panel drive, the horizontal zoom function of the output video is realized by such a principle.

  Here, display processing for displaying a 4: 3 video signal on a 16: 9 wide liquid crystal panel will be described. 4: 3 represents the video ratio of the video signal, and 16: 9 represents the screen ratio of the wide liquid crystal panel. When the video signal is displayed on the wide liquid crystal panel as it is, the video is displayed by being stretched by about 33% in the horizontal direction. In this case, the video ratio changes, and the visual appearance of the video is not good. As a method of maintaining the original 4: 3 video ratio, a method of displaying the video without stretching it in the horizontal direction by making both ends of the display area of the panel black is widely used. However, this method wastes the display area of the panel.

  In view of this, a wide zoom system has been adopted in which an image is displayed on the entire area of the panel while maintaining the original image ratio at the center of the panel. In the wide zoom system, the original image ratio is maintained at the center of the panel, and the image is gradually stretched as it moves away from the center of the panel in the horizontal direction. For example, assuming that the magnification at the center is A, the magnification between the center and the edge is B, and the magnification at the edge is C, these relationships are A ≦ B ≦ C. As described above, in the wide zoom method, different magnifications (zoom magnifications) are set for the center portion and the end portion of the panel.

  In order to change the zoom magnification of the output video, for example, the interval between sampling points may be changed by changing the frequency of the sampling clock. The sampling clock is generally generated by a timing controller based on a clock called DOTCLK. Since the timing controller uses DOTCLK as an internal reference clock, it cannot generate a pulse signal faster than DOTCLK. In addition, since the video signal generally includes three primary color signals of R signal, G signal, and B signal, the sampling clock is generally generated by dividing DOTCLK by 3. A method for changing the frequency of the sampling clock is disclosed in Patent Document 1, for example.

  In order to change the frequency of the sampling clock, for example, the frequency of dividing when the sampling clock is generated by dividing DOTCLK may be changed. However, this method can generate only an integer multiple pulse or 1 / integer multiple pulse of DOTCLK. When the wide zoom method is performed using such pulses, the magnification of the video cannot be changed continuously, and the change in the magnification of the video becomes discontinuous. When this happens, the boundary of the image becomes conspicuous at the magnification change point, and the quality of the image deteriorates.

As a countermeasure, a method of making the boundary inconspicuous by changing the magnification in small increments can be considered. However, this method has a problem that the circuit scale of the timing controller increases due to the complexity of the frequency dividing process. This method also has a problem that a faint boundary remains, which is not an essential solution. Further, regarding the zoom magnification in the case of outputting an image over the entire screen, the zoom magnification X of the entire screen in the wide zoom display needs to be equal to the zoom magnification X0 of the entire screen in the normal display. This is because if X is larger than X0, the video image protrudes from the screen, and if X is smaller than X0, the screen is left behind. Therefore, when wide zoom display is realized by changing the frequency division number of DOTCLK, it is necessary to make the zoom magnification X equal to the zoom magnification X0. Therefore, the above method has a further problem that the frequency division number of DOTCLK cannot be freely selected.
JP 2004-46161 A

  The present invention relates to a display panel driving device and a display device, and an object thereof is to propose a new technique for realizing a horizontal zoom function of an output video.

  The present invention includes, for example, a horizontal synchronization circuit that generates a pulse signal synchronized with a horizontal synchronization signal, a phase comparison circuit that performs phase comparison between the pulse signal and a phase comparison signal, and a clock based on a comparison result of the phase comparison. A frequency control circuit for generating a frequency control signal for controlling the frequency of the signal, a modulation signal generation circuit for generating a frequency modulation signal for modulating the frequency of the clock signal in synchronization with the horizontal synchronization signal, and A modulation signal addition circuit that adds the frequency modulation signal to a frequency control signal; an oscillator that oscillates the clock signal according to the frequency control signal to which the frequency modulation signal is added; A display panel driving device comprising: a frequency divider that generates a phase comparison signal.

  The present invention includes, for example, a horizontal synchronization circuit that generates a pulse signal synchronized with a horizontal synchronization signal, a phase comparison circuit that performs phase comparison between the pulse signal and a phase comparison signal, and a clock based on a comparison result of the phase comparison. A frequency control circuit for generating a frequency control signal for controlling the frequency of the signal, a modulation signal generation circuit for generating a frequency modulation signal for modulating the frequency of the clock signal in synchronization with the horizontal synchronization signal, and A modulation signal addition circuit that adds the frequency modulation signal to a frequency control signal; an oscillator that oscillates the clock signal according to the frequency control signal to which the frequency modulation signal is added; A frequency divider for generating a phase comparison signal and a sampling clock generator for generating a sampling clock signal using the clock signal And the circuit is a display device characterized by comprising a display panel for synchronization with the screen display on the sampling clock signal.

  The present invention relates to a display panel driving device and a display device, and proposes a new method for realizing a horizontal zoom function of an output video.

  FIG. 1 is a system configuration diagram of the liquid crystal display device 101. The liquid crystal display device 101 of FIG. 1 includes a liquid crystal panel driving device 111 and a liquid crystal panel 112. The liquid crystal display device 101 is an embodiment of the display device, the liquid crystal panel driving device 111 is an embodiment of the display panel driving device, and the liquid crystal panel 112 is an embodiment of the display panel.

  The liquid crystal panel drive device 111 is an integrated circuit device that drives the liquid crystal panel 112. The liquid crystal panel driving device 111 includes a synchronization processing unit 121 that generates a clock signal (DOTCLK) and a timing controller 122 that generates a sampling clock signal. Here, the driving method of the liquid crystal panel 112 is analog panel driving.

  2A and 2B are each a modified embodiment of the liquid crystal display device 101 of FIG. In the liquid crystal display device 101 of FIG. 1, the timing controller 122 is provided in the liquid crystal panel driving device 111, whereas in the liquid crystal display device 101 of FIG. 2A, the timing controller 122 is provided in the liquid crystal panel 112. Yes. In the liquid crystal display device 101 of FIG. 2B, the timing controller 122 is provided separately from the panel driving device 111 and the liquid crystal panel 112.

  Hereinafter, the liquid crystal display device 101 of FIG. 1 will be described, but the following description can also be applied to the liquid crystal display device 101 of FIGS. 2A and 2B.

  FIG. 3A shows a state in which a 4: 3 video signal is displayed as it is on a 4: 3 liquid crystal panel. Here, the screen ratio of the liquid crystal panel 112 is 16: 9. Therefore, when the video signal is displayed as it is on the liquid crystal panel 112 of FIG. 1, the video is displayed by being stretched 33% in the horizontal direction as shown in FIG. 3B. On the other hand, FIG. 3C shows a state in which an image is displayed without being stretched in the horizontal direction by making both ends of the display area of the liquid crystal panel 112 of FIG. 1 black.

  The liquid crystal display device 101 in FIG. 1 has a horizontal zoom function of output video, and can output video by a wide zoom method. In particular, the liquid crystal display device 101 of FIG. 1 is not capable of wide zoom display in which the boundary of magnification change is conspicuous as shown in FIG. . A method for realizing such a wide zoom display will be described later.

  Hereinafter, the configuration and operation of the liquid crystal display device 101 of FIG. 1 will be described. Note that the liquid crystal display device 101 in FIG. 1 handles synchronization signals such as a horizontal synchronization signal and a vertical synchronization signal. FIG. 1 shows a state in which a synchronization signal is input to the synchronization processing unit 121. Primary color signals such as R, G, and B signals as video signals are input to the liquid crystal panel 112 by separate processing. In FIG. 1, the primary color signal is omitted in FIG.

  The synchronization processing unit 121 of FIG. 1 includes a first phase comparison circuit 131, a first oscillator 132, a first frequency divider 133, and a pulse generation circuit 134. These circuit blocks constitute a horizontal synchronization circuit 135.

  A horizontal synchronization signal is input to the synchronization processing unit 121. The phase comparison circuit 131 is a circuit that performs phase comparison between the horizontal synchronization signal and the phase comparison signal. The oscillator 132 is a circuit that oscillates a clock signal having a frequency corresponding to the comparison result of the phase comparison. The frequency divider 133 is a circuit that divides the clock signal to generate the phase comparison signal. The pulse generation circuit 134 is a circuit that generates a pulse signal synchronized with the horizontal synchronization signal using the phase comparison signal synchronized with the horizontal synchronization signal. As described above, the horizontal synchronization circuit 135 generates a pulse signal synchronized with the horizontal synchronization signal.

  The operation of these circuit blocks will be described.

  The oscillator 132 is an oscillation circuit that oscillates a signal by self-adjusted self-running oscillation control. The clock signal oscillated by the oscillator 132 is divided by the frequency dividing circuit 133. The frequency divider circuit 133 outputs a signal having substantially the same frequency as the horizontal synchronization signal. The phase comparison circuit 131 receives the horizontal synchronization signal as a reference signal and the phase comparison signal output from the frequency divider circuit 133. Here, the frequency of the horizontal synchronizing signal is about 15 kHz. The phase comparison circuit 131 performs phase comparison between the horizontal synchronization signal and the phase comparison signal. Subsequently, the phase comparison circuit 131 controls the oscillation frequency of the oscillator 132 by feeding back the phase comparison result to the oscillator 132 to synchronize the phase of the horizontal synchronization signal and the phase comparison signal. Thereby, a clock signal and a phase comparison signal synchronized with the horizontal synchronization signal are obtained. The clock signal is used as an internal reference clock of the synchronization processing unit 121. The frequencies of the clock signal and the phase comparison signal are here about 10 MHz and about 15 kHz, respectively.

  A signal synchronized with the horizontal synchronizing signal is input from the frequency dividing circuit 133 to the pulse generating circuit 134. The signal is a phase comparison signal here, but it may be a signal other than the phase comparison signal. The pulse generation circuit 134 generates various pulse signals synchronized with the horizontal synchronization signal by using the signal synchronized with the horizontal synchronization signal. The pulse generation circuit 134 generates, for example, a pulse signal supplied to a second phase comparison circuit 141 described later and a pulse signal supplied to a zoom data circuit 151 described later. The former pulse signal and the latter pulse signal are different pulse signals here, but the same pulse signal may be used.

  Note that the phase comparison circuit 131, the oscillator 132, and the frequency dividing circuit 133 constitute a charge pump type PLL. The phase comparison circuit 131 performs a detection operation (phase comparison operation) only during the detection period (phase comparison period). The phase comparison circuit 131 performs phase comparison by charging and discharging the PLL detection filter during the pulse Hi period and the pulse Lo period. A voltage corresponding to the phase difference between the horizontal synchronization signal and the phase comparison signal is generated at the output terminal of the phase comparison circuit 131. The voltage corresponds to the phase comparison result. If the phase difference is 0, the voltage is equal to the reference voltage, and if the phase difference is not 0, the voltage is higher or lower than the reference voltage (FIG. 4). The oscillation frequency of the oscillator 132 is controlled by the voltage. More specifically, the oscillation frequency of the oscillator 132 is controlled by the voltage difference between the voltage and the reference voltage.

  The synchronization processing unit 121 of FIG. 1 further includes a second phase comparison circuit 141, a frequency control circuit 142, a second oscillator 143, and a second frequency dividing circuit 144.

  A pulse signal synchronized with the horizontal synchronization signal is input to the phase comparison circuit 141. The phase comparison circuit 141 is a circuit that performs phase comparison between the pulse signal and the phase comparison signal. The frequency control circuit 142 is a circuit that generates a frequency control signal based on the comparison result of the phase comparison. The frequency control signal is a signal for controlling the frequency of the clock signal (DOTCLK). The oscillator 143 is a circuit that oscillates the clock signal in response to the frequency control signal (or the frequency control signal to which the frequency modulation signal is added). The frequency dividing circuit 144 is a circuit that divides the clock signal to generate the phase comparison signal.

  The operation of these circuit blocks will be described.

  The oscillator 143 is an oscillation circuit that oscillates a signal by self-adjusted self-running oscillation control. The clock signal oscillated by the oscillator 143 is divided by the frequency dividing circuit 144. The frequency dividing circuit 144 outputs a signal having substantially the same frequency as the pulse signal. The phase comparison circuit 141 receives the pulse signal serving as a reference signal and the phase comparison signal output from the frequency dividing circuit 144. The phase comparison circuit 141 performs a phase comparison between the pulse signal and the phase comparison signal, and operates to synchronize the phase between the pulse signal and the phase comparison signal. The phase comparison result output from the phase comparison circuit 141 is input to the frequency control circuit 142. The phase comparison result may be a DC current signal or a DC voltage signal. The frequency control circuit 142 outputs a frequency control signal corresponding to the phase comparison result. The frequency control signal may be a DC current signal or a DC voltage signal. The oscillation frequency of the oscillator 143 is controlled by the frequency control signal.

  In this way, DOTCLK synchronized with the pulse signal is obtained. The frequency of DOTCLK is set based on the panel resolution. The frequency control circuit 142 can generate frequency control signals corresponding to various panel resolutions. Further, a frequency modulation signal can be superimposed on the frequency control signal. Thereby, the oscillation frequency of the oscillator 143 can be modulated. The frequency modulation signal will be described later.

  The phase comparison circuit 141, the frequency control circuit 142, the oscillator 143, and the frequency divider circuit 144 constitute a charge pump type PLL. The phase comparison circuit 141 performs the detection operation (phase comparison operation) only during the detection period (phase comparison period). The phase comparison circuit 141 performs phase comparison by charging and discharging the PLL detection filter during the pulse Hi period and the pulse Lo period. A voltage corresponding to the phase difference between the pulse signal and the phase comparison signal is generated at the output terminal of the phase comparison circuit 141. The voltage corresponds to the phase comparison result. If the phase difference is 0, the voltage is equal to the reference voltage, and if the phase difference is not 0, the voltage is higher or lower than the reference voltage (FIG. 4). The frequency control circuit 142 generates a frequency control signal based on the voltage, that is, controls the oscillation frequency of the oscillator 143 based on the voltage. More specifically, the frequency control circuit 142 generates a frequency control signal based on the voltage difference between the voltage and the reference voltage, that is, sets the oscillation frequency of the oscillator 143 based on the voltage difference between the voltage and the reference voltage. Control.

  The synchronization processing unit 121 in FIG. 1 further includes a zoom data circuit 151 that is an example of a modulation signal generation circuit, a zoom control circuit 152 that is an example of a modulation signal addition circuit, and a low-pass filter 153.

  The zoom data circuit 151 receives a pulse signal synchronized with the horizontal synchronizing signal. The zoom data circuit 151 is a circuit that generates a frequency modulation signal synchronized with the horizontal synchronization signal by using the pulse signal. The frequency modulation signal is a signal for modulating the frequency of the clock signal (DOTCLK). The zoom control circuit 152 is a circuit that adds the frequency modulation signal to the frequency control signal. The low-pass filter 153 is a low-pass filter for filtering the frequency modulation signal. The zoom control circuit 152 adds the frequency modulation signal to the frequency control signal via the low pass filter 153.

  The timing controller 122 of FIG. 1 includes a sampling clock generation circuit 161 and a drive pulse generation circuit 162.

  A clock signal (DOTCLK) oscillated by the second oscillator 143 is input to the timing controller 122. The sampling clock generation circuit 161 is a circuit that generates a sampling clock signal using the clock signal. The drive pulse generation circuit 162 is a circuit that generates various drive pulses using the clock signal. The sampling clock signal and the driving pulse are input to the liquid crystal panel 112. The liquid crystal panel 112 performs screen display related to the video signal in synchronization with the sampling clock signal and controlled by the driving pulse.

  FIG. 5 is a waveform diagram of DOTCLK and the sampling clock. 5A and 5C represent DOTCLK before modulation and DOTCLK after modulation, respectively. 5B and 5D represent sampling clocks generated using DOTCLK of FIGS. 5A and 5C, respectively. The sampling clocks of FIGS. 5B and 5D are obtained by dividing the DOTCLK of FIGS. 5A and 5C by 3, respectively.

  The liquid crystal display device 101 of FIG. 1 can modulate the frequency of DOTCLK by adding a frequency modulation signal to the frequency control signal. The liquid crystal display device 101 of FIG. 1 can modulate the frequency of DOTCLK to an arbitrary frequency by such analog processing. According to such frequency modulation, the change in the frequency of DOTCLK becomes smooth (FIG. 5C), and similarly, the change in the frequency of the sampling clock also becomes smooth (FIG. 5D). As a result, a wide zoom display that suppresses the occurrence of the boundary of the magnification change as shown in FIG. 3E is realized.

  On the other hand, FIG. 6 is a system configuration diagram of the liquid crystal display device 101 of the comparative example. The liquid crystal display device 101 of FIG. 6 includes a sampling zoom control circuit 201 instead of the zoom data circuit 151, the zoom control circuit 152, and the low-pass filter 153. The sampling zoom control circuit 201 receives DOTCLK oscillated by the second oscillator 143, modulates the frequency of the DOTCLK by dividing the DOTCLK, and supplies the DOTCLK whose frequency is modulated to the sampling clock generation circuit 161. Supply.

  FIG. 7 is a waveform diagram of DOTCLK and sampling clock in the comparative example. 7A and 7B represent the DOTCLK and the sampling clock before modulation, respectively. 7C and 7D represent sampling clocks generated by modulating the frequency of DOTCLK in FIG. 7A. When the frequency of the sampling clock is changed from the frequency of FIG. 7C to the frequency of FIG. 7D, a sampling clock as shown in FIG. 7E is generated. As described above, in the comparative example, when the frequency of DOTCLK is modulated, the change in the frequency of the sampling clock is not smooth. Therefore, a wide zoom display in which the boundary of the magnification change is conspicuous as shown in FIG. 3D is obtained.

  In the comparative example, it is necessary to divide the display screen into a plurality of areas as shown in FIG. 3D. FIG. 3D shows one area of magnification A, two areas of magnification B, and two areas of magnification C. As described above, the comparative example has a disadvantage that the boundary between these regions is conspicuous. On the other hand, in this embodiment, it is not necessary to divide the display area into a plurality of areas, and the frequency of DOTCLK can be freely modulated. Therefore, in this embodiment, deterioration of the image quality due to the occurrence of the boundary is suppressed, and a smooth wide zoom display is realized. Further, in this embodiment, an individual circuit configuration for each magnification is unnecessary, and the circuit scale does not increase even if the frequency modulation is complicated.

  In this embodiment, it is not necessary to provide the sampling zoom control circuit 201 as shown in FIG. Therefore, in this embodiment, a normal timing controller can be used as it is as the timing controller 122. In this embodiment, since the frequency of DOTCLK, which is the internal reference clock of the timing controller 122, is modulated, it is necessary to adjust the timing of pulse generation. However, this timing adjustment is the same operation as the timing adjustment in the initial setting. Therefore, it is not necessary to add a special circuit configuration to the timing controller 122.

  Hereinafter, the zoom data circuit 151, the zoom control circuit 152, and the low-pass filter 153 in FIG. 1 will be described in more detail.

(1) Zoom Data Circuit The zoom data circuit 151 in FIG. 1 will be described.

  The zoom data circuit 151 is a circuit that acquires and outputs a compression / expansion pattern, and outputs a compression / expansion pattern that satisfies a constraint condition described later. The zoom data circuit 151 may acquire the compression / expansion pattern from the inside of the liquid crystal panel driving device 111 or from the outside. In the former case, for example, the compression / expansion pattern is stored in the storage area as a preset different for each zoom mode. In the latter case, the compression / decompression pattern is input from the data input terminal. The compression / decompression pattern is output to the zoom control circuit 152 in the form of a frequency modulation signal. The frequency modulation signal is generated based on the pulse signal and is a signal synchronized with the horizontal synchronization signal. The frequency modulation signal may be a current signal or a voltage signal.

(2) Zoom Control Circuit The zoom control circuit 152 in FIG. 1 will be described.

  The second phase comparison circuit 141 is, for example, a charge pump type PLL, and the phase comparison result by the second phase comparison circuit 141 is output as, for example, a DC voltage signal. The frequency control circuit 142 decreases the oscillation frequency of the second oscillator 143 if the DC voltage is higher than the reference voltage, and increases the oscillation frequency of the second oscillator 143 if the DC voltage is lower than the reference voltage. Such control is performed through a frequency control signal. When the phase synchronization is completed, the DC voltage becomes equal to the reference voltage. Although the phase comparison is performed only in the phase comparison period (FIG. 4), the second oscillator 143 always refers to the DC voltage. Therefore, although the oscillation frequency of the second oscillator 143 varies linearly with respect to the DC voltage, the phase synchronization is not lost unless the DC voltage varies during the phase comparison period.

  The frequency control circuit 142 outputs a frequency control signal. The zoom control circuit 152 adds the frequency modulation signal to the frequency control signal after the phase synchronization is completed, that is, after the phase comparison result by the second phase comparison circuit 141 is equal to the reference voltage. The frequency control signal added with the frequency modulation signal is input to the second oscillator 143.

  FIG. 8A shows a first waveform example of the frequency modulation signal. FIG. 8A shows the reference voltage together with the frequency modulation signal. FIG. 8A further illustrates a horizontal period, a video period, a phase comparison period, and a non-phase comparison period. As shown in FIG. 8A, the non-phase comparison period is a period other than the phase comparison period in the horizontal period, that is, a period obtained by removing the phase comparison period from the horizontal period.

  Here, the frequency modulation signal is assumed to be the following signal. As shown in FIG. 8A, the frequency modulation signal is a signal that vibrates positively and negatively with the reference voltage as a reference. The waveform of the frequency modulation signal in the video period is symmetrical with respect to the center of the video period as shown in FIG. 8A. The reason for making the waveform symmetrical in this way is to prevent the center of the image from shifting horizontally from the center of the screen as shown in FIG. 9A.

  The frequency modulation signal is added to the frequency control signal. When the frequency modulation signal is higher than the reference voltage, the oscillation frequency of the oscillator 143 decreases. When the frequency modulation signal is lower than the reference voltage, the oscillation frequency of the oscillator 143 increases. In this way, the frequency of DOTCLK is modulated according to the signal pattern of the frequency modulation signal.

  The frequency modulation signal is further provided with the following restrictions. If the DC voltage in the phase comparison period varies between when the frequency modulation is performed and when the frequency modulation is not performed, the phase synchronization relationship is broken. Therefore, it is necessary to suppress the fluctuation of the DC voltage within the horizontal period. The fluctuation of the DC voltage in the phase comparison period does not occur if the cumulative amount of charge / discharge by the frequency modulation signal becomes zero. Specifically, the waveform of the frequency modulation signal in the non-phase comparison period is such that the area of the portion A above the reference voltage and the area of the portion B below the reference voltage are equal as shown in FIG. 8A. If so, the above voltage fluctuation does not occur. That is, if the area of the part A and the area of the part B shown in FIG. 8A are equal, the above voltage fluctuation does not occur.

  As long as the above constraint conditions are observed, the waveform of the frequency modulation signal may be another waveform. For example, the waveform of the frequency modulation signal may not be a waveform having a uniform step as shown in FIG. 8A but a waveform having a non-uniform step as shown in FIG. 8B. Further, the waveform of the frequency modulation signal may not be a waveform that is vertically symmetrical with respect to the reference voltage as shown in FIG. 8A, but may be a waveform that is vertically asymmetric with respect to the reference voltage as shown in FIG. 8C. Further, the waveform of the frequency modulation signal may be a linear waveform as shown in FIG. 8D instead of a step-shaped waveform as shown in FIG. 8A.

  Here, the frequency modulation signal is further restricted to be a signal synchronized with the horizontal synchronization signal. As described above, the waveform of the frequency modulation signal in the video period is symmetrical with respect to the center of the video period as shown in FIG. 8A. The reason why the waveform is symmetrical is to prevent the center of the video from shifting horizontally from the center of the screen as shown in FIG. 9A. However, even if the waveform is symmetric, the center of the video is not prevented from shifting unless the frequency modulation signal is synchronized with the horizontal synchronization signal (see FIG. 9B). That is, if the frequency modulation signal is not synchronized with the horizontal synchronization signal, the meaning of making the waveform symmetrical is lost. For this reason, in this embodiment, the pulse signal synchronized with the horizontal synchronizing signal is supplied to the zoom data circuit 151 to synchronize the frequency modulation signal with the horizontal synchronizing signal. FIG. 9B is an example of an image when the waveform is symmetrical, but the frequency modulation signal is not synchronized with the horizontal synchronization signal.

  When adding the frequency control signal and the frequency modulation signal, these signals may be current signals or voltage signals, but are preferably current signals. The reason is that the resistance of these signals to noise can be increased. In this case, the relationship between the frequency modulation signal and the reference voltage as shown in FIGS. 8A to 8D may be set when the frequency modulation signal is a voltage signal, or may be set when the frequency modulation signal is a current signal. Good. In the former case, the frequency modulation signal is converted from a voltage signal to a current signal before being added to the frequency control signal. In the latter case, the frequency modulation signal is set by converting the reference voltage into a current.

(3) Low-pass filter The low-pass filter 153 in FIG. 1 will be described.

  As shown in FIGS. 8A to 8D, the waveform of the frequency modulation signal may be a step-shaped waveform or a linear waveform. However, when the waveform has a step shape, when the frequency control signal and the frequency modulation signal are added, a steep change occurs in the addition result. Therefore, in this embodiment, the frequency modulation signal is filtered by the low-pass filter 153 before adding the frequency control signal and the frequency modulation signal. This relaxes the response and prevents DOTCLK from being affected by the occurrence of jitter.

1 is a system configuration diagram of a liquid crystal display device (Example). FIG. It is a system block diagram of a liquid crystal display device (modification example). It is a system block diagram of a liquid crystal display device (modification example). A state in which a 4: 3 video signal is displayed on a 4: 3 liquid crystal panel is shown. This represents a state in which a 4: 3 video signal is displayed on a 16: 9 liquid crystal panel. An example of black band display is shown. An example of a wide zoom display is shown. An example of a wide zoom display is shown. It is a figure for demonstrating a phase comparison result and a reference voltage. It is a wave form diagram of DOTCLK and a sampling clock (Example). It is a system block diagram of a liquid crystal display device (comparative example). It is a wave form diagram of DOTCLK and a sampling clock (comparative example). It is a 1st waveform example of a frequency modulation signal. It is a 2nd waveform example of a frequency modulation signal. It is a 3rd example of a waveform of a frequency modulation signal. It is a 4th waveform example of a frequency modulation signal. It is a figure for demonstrating the shift | offset | difference of the center of an image | video. It is a figure for demonstrating the shift | offset | difference of the center of an image | video.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Liquid crystal display device 111 Liquid crystal panel drive device 112 Liquid crystal panel 121 Synchronization processing part 122 Timing controller 131 1st phase comparison circuit 132 1st oscillator 133 1st frequency divider circuit 134 Pulse generation circuit 135 Horizontal synchronization circuit 141 2nd Phase comparison circuit 142 frequency control circuit 143 second oscillator 144 second frequency dividing circuit 151 zoom data circuit 152 zoom control circuit 153 low-pass filter 161 sampling clock generation circuit 162 drive pulse generation circuit 201 sampling zoom control circuit

Claims (5)

A horizontal synchronization circuit that generates a pulse signal synchronized with the horizontal synchronization signal;
A phase comparison circuit for performing phase comparison between the pulse signal and the phase comparison signal;
A frequency control circuit for generating a frequency control signal for controlling the frequency of the clock signal based on the comparison result of the phase comparison;
A modulation signal generation circuit that generates a frequency modulation signal for modulating the frequency of the clock signal in synchronization with the horizontal synchronization signal;
A modulation signal addition circuit for adding the frequency modulation signal to the frequency control signal;
An oscillator that oscillates the clock signal in response to the frequency control signal to which the frequency modulation signal has been added;
A display panel driving apparatus comprising: a frequency dividing circuit that divides the clock signal to generate the phase comparison signal.   The display panel driving apparatus according to claim 1, wherein a waveform of the frequency modulation signal in a video period is symmetrical with respect to a center of the video period. The frequency control signal is generated based on a voltage difference between a voltage corresponding to a comparison result of the phase comparison and a reference voltage,
2. The waveform of the frequency modulation signal in a non-phase comparison period is such that an area of a portion above the reference voltage is equal to an area of a portion below the reference voltage. Or the display panel driving device according to 2; Comprising a low pass filter for filtering the frequency modulated signal;
4. The display panel driving device according to claim 1, wherein the modulation signal addition circuit adds the frequency modulation signal to the frequency control signal via the low-pass filter. 5. . A horizontal synchronization circuit that generates a pulse signal synchronized with the horizontal synchronization signal;
A phase comparison circuit for performing phase comparison between the pulse signal and the phase comparison signal;
A frequency control circuit for generating a frequency control signal for controlling the frequency of the clock signal based on the comparison result of the phase comparison;
A modulation signal generation circuit that generates a frequency modulation signal for modulating the frequency of the clock signal in synchronization with the horizontal synchronization signal;
A modulation signal addition circuit for adding the frequency modulation signal to the frequency control signal;
An oscillator that oscillates the clock signal in response to the frequency control signal to which the frequency modulation signal has been added;
A frequency divider that divides the clock signal to generate the phase comparison signal;
A sampling clock generation circuit that generates a sampling clock signal using the clock signal;
And a display panel that displays a screen in synchronization with the sampling clock signal.

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