JP2003345331A - Clock generation circuit for image display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a clock generation circuit for image display which generates a display clock which has a plurality of independent periods for fine adjustment of a character display size of an image to be displayed within a picture in one vertical synchronizing period. <P>SOLUTION: A frequency division circuit A 50 generates a clock A for comparison obtained by dividing the frequency of the display clock by N, and a frequency division circuit B 60 generates a clock B for comparison obtained by dividing the frequency of the display clock by N', and a selector circuit 70 selects one of two clocks for comparison on the basis of a display clock switching signal outputted from a display clock switching circuit 80. When display of a picture DSPA is terminated, the display clock switching circuit 80 outputs the display clock switching signal to the selector circuit 70 in order to switch a clock for comparison, and the clock for comparison outputted from the selector circuit 70 to a phase comparator 10 is switched. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display clock used during a screen display period of an image display device, and more particularly to an image display clock generation circuit for generating display clocks having different cycles. Is.

[0002]

2. Description of the Related Art The screen display of an image display device is controlled by a vertical synchronizing signal and a horizontal synchronizing signal. One vertical synchronization period (1V period) is a display period of one screen, and within the period, horizontal scanning is performed a plurality of times based on the horizontal synchronization signal to display the screen. When displaying a character or an image on such an image display device, it is common to control a screen display by generating a display clock synchronized with a horizontal synchronization signal using a PLL (Phase Locked Loop) circuit. .

A screen display device using a PLL circuit as an image display clock generation circuit will be described with reference to FIGS. FIG. 7 is a block diagram showing the configuration of the PLL circuit. The PLL circuit includes a phase comparator 110, a charge pump 120, a loop filter 130, and a VCO (Volt
An age controlled oscillator circuit 140 and a frequency dividing circuit 150 are provided.

The phase comparator 110 compares the phase of the horizontal synchronizing signal with the comparison clock generated by dividing the display clock by the frequency dividing circuit 150, and outputs a phase error signal.

The charge pump 120 comprises a phase comparator 11
The phase error signal output from 0 is boosted to a level at which the voltage of the VCO circuit 140 can be controlled.

The loop filter 130 blocks high frequency components of the signal boosted by the charge pump 120.

The VCO circuit 140 includes a loop filter 13
Transmission control is performed based on the output from 0, and a display clock is generated.

The frequency dividing circuit 150 divides the display clock to generate a comparison clock.

FIG. 8 is a block diagram showing the configuration of a screen display signal generation circuit for generating a screen display signal using the display clock generated by the PLL circuit shown in FIG. The screen display signal generation circuit includes a horizontal screen display signal generation circuit 160 that generates a control signal for horizontal screen display, and a vertical screen display signal generation circuit 170 that generates a control signal for vertical screen display. ing.

The horizontal screen display signal generation circuit 160 is
The horizontal synchronizing signal is used as a trigger to count the display clock, and the horizontal screen display signal A for the first screen and the horizontal screen display signal B for the second screen are output at desired timing.

FIG. 9 is a block diagram showing a configuration of the horizontal screen display signal generation circuit 160 shown in FIG. The horizontal screen display signal generation circuit 160 includes HP register circuits 161a and 161b and display clock pulse counter circuits 162a and 162b. HP register circuit 161a and display clock pulse counter circuit 16
2a generates a horizontal screen display signal A, and the HP register circuit 161b and the display clock pulse counter circuit 1
62b and the horizontal screen display signal B are generated.

The horizontal display start position of the first screen is set in the HP register circuit 161a. The horizontal display start position of the second screen is set in the HP register circuit 161b.

Display clock pulse counter circuit 162
The counter value of a is reset when the horizontal synchronizing signal is at "L" level, and the horizontal display start position of the first screen set in the HP register circuit 161a is set as an initial value. When the horizontal synchronizing signal is at "H" level, the display clock is counted and the horizontal screen display signal A is output at a desired timing.

Display clock pulse counter circuit 162
For b, the counter value is reset when the horizontal synchronizing signal is at the “L” level, and the horizontal display start position of the second screen set in the HP register circuit 161b is set as an initial value. When the horizontal synchronizing signal is at "H" level, the display clock is counted and the horizontal screen display signal B is output at a desired timing.

The vertical screen display signal generation circuit 170 includes
The vertical synchronizing signal is used as a trigger to count display clock pulses, and the vertical screen display signal A for the first screen and the vertical screen display signal B for the second screen are output at desired timings.

FIG. 10 is a block diagram showing the configuration of the vertical screen display signal generation circuit 170 shown in FIG. The vertical screen display signal generation circuit 170 includes VP register circuits 171a and 171b and horizontal sync pulse counter circuits 172a and 172b. The vertical direction screen display signal A is generated by the VP register circuit 171a and the horizontal synchronizing pulse counter circuit 172a, and the VP register circuit 17 is generated.
A vertical screen display signal B is generated by 1b and the horizontal synchronizing pulse counter circuit 172b.

In the VP register circuit 171a, the vertical display start position of the first screen is set. The vertical display start position of the second screen is set in the VP register circuit 171b.

The horizontal synchronizing pulse counter circuit 172a includes
When the vertical synchronizing signal is at "L" level, the counter value is reset, and the vertical display start position of the first screen set in the VP register circuit 171a is set as an initial value. When the vertical sync signal is at "H" level, the horizontal sync signal is counted and the vertical screen display signal A is obtained at a desired timing.
Is output.

The horizontal sync pulse counter circuit 172b is
The counter value is reset when the vertical synchronizing signal is at "L" level, and the vertical display start position of the second screen set in the VP register circuit 171b is set as an initial value. When the vertical synchronizing signal is at "H" level, the horizontal synchronizing signal is counted and the vertical direction screen display signal B is obtained at a desired timing.
Is output.

The operation of the screen display device will be described with reference to the time charts of FIGS. 11 to 13 by taking the case of displaying the two screens DSPA and DSPB as an example. Screen DS
It is assumed that PA is displayed from the scanning line L line to the scanning line m line of the plurality of scanning lines in the 1V period, and the screen DSPB is displayed from the scanning line n line to the scanning line p line.

The operation of the image display device is as follows. The operation of the PLL circuit for generating the display clock and the horizontal screen display signals A and B and the vertical screen display signal A using the display clock generated by the PLL circuit. The operation of the screen display signal generation circuit for generating B can be divided.

First, the operation of the PLL circuit for generating the display clock will be described. The phase comparator 110 compares the horizontal synchronizing signal and the phase of the comparison clock generated by dividing the display clock by the frequency dividing circuit 150, and outputs a phase error signal to the charge pump 120.

When the phase error signal is input, the charge pump 120 stores the input phase error signal, and the VCO
The voltage is boosted to a level at which the voltage of the circuit 140 can be controlled and output to the loop filter 130.

The loop filter 130 removes high frequency components of the signal output from the charge pump 120, and VC
The voltage control signal is output to the O circuit 140.

The VCO circuit 140 includes a loop filter 13
Based on the voltage control signal input from 0, the oscillation frequency is adjusted to generate the display clock of the cycle T. VC
The O circuit 140 outputs the display clock of the cycle T to the frequency dividing circuit 150 and the screen display signal generating circuit.

When the display clock is input, the frequency dividing circuit 150 counts the display clock, generates a comparison clock of one horizontal synchronization period (1H period) period, and outputs it to the phase comparator 110.

Next, the operation of the horizontal screen display signal generation circuit 160 of the screen display signal generation circuit will be described with reference to the time chart of FIG. The horizontal screen display signal generation circuit 160 receives the horizontal synchronization signal and the display clock generated by the PLL circuit. At time t1,
When the horizontal synchronizing signal of the scanning line L line which starts the display of the screen DSPA becomes "L", the control unit (not shown) of the image display device causes the HP register circuit 161a to display the screen D.
The display start time t2 of SPA is set. Specifically, the display start time of the screen DSPA is converted by the display clock of the cycle T, and the number of display start clocks is set in the HP register circuit 161a. In this case, the number of display clocks from time t1 to time t2 is the display start clock number of the screen DSPA. Further, the display clock pulse counter circuit 162a is reset and then starts counting the display clock.

At time t2, if the count number of the display clock pulse counter circuit 162a and the display start clock number set in the HP register circuit 161a match, the display clock pulse counter circuit 162a becomes
The horizontal screen display signal A is set to "H". After that, at time t3, the display of the screen DSPA ends, so the display clock pulse counter circuit 162a sets the horizontal screen display signal A to "L".

Such an operation is repeated from the scanning line L line displaying the screen DSPA to the scanning line m line, and each scanning line line displays the screen DSPA (H-
DSPA) The horizontal screen display signal A is set to "H".

At time t5, when the horizontal synchronizing signal of the scanning line n line which starts the display of the screen DSPB becomes "L", the control unit (not shown) of the image display device sets HP.
The time t6 when the display of the screen DSPB is started is set in the register circuit 161b. Specifically, the screen DSP
Convert the display start time of B with the display clock of cycle T,
The number of display start clocks is set in the HP register circuit 161b. In this case, the number of display clocks from time t5 to time t6 becomes the number of display start clocks of the screen DSPB. The display clock pulse counter circuit 162b is reset and then starts counting the display clock.

At time t6, when the count number of the display clock pulse counter circuit 162b and the display start clock number set in the HP register circuit 161b match, the display clock pulse counter circuit 162b becomes
The horizontal screen display signal B is set to "H". After that, at time t7, the display of the screen DSPB ends, so the display clock pulse counter circuit 162b sets the horizontal screen display signal A to "L".

Such an operation is repeated from the scanning line n line for displaying the screen DSPB to the scanning line p line, and each scanning line line displays the screen DSPB (H-
DSPB) The horizontal screen display signal B is set to "H".

Next, the operation of the vertical direction screen display signal generation circuit 170 of the screen display signal generation circuit will be described with reference to the time chart of FIG. The vertical screen display signal generation circuit 170 includes a vertical sync signal, a horizontal sync signal, and a PL sync signal.
The display clock generated by the L circuit is input. When the vertical synchronizing signal becomes “L” at time t0, the control unit (not shown) of the image display device causes the VP register circuit 171a to scan the scanning line L for starting the display of the screen DSPA.
A line start time t1 and a scan line m line start time t4 for ending the display are set. Specifically, the number of horizontal synchronizing signals from the vertical synchronizing signal to the scanning line L line and the scanning line m line is set. Further, the horizontal synchronizing pulse counter circuit 172a is reset, and when the vertical synchronizing signal changes to "H", counting of the horizontal synchronizing signal is started.

At time t1, the count number of the horizontal synchronizing pulse counter circuit 172a and the VP register circuit 171.
When the values of a match, the horizontal sync pulse counter circuit 17
2a sets the vertical screen display signal A to "H". At time t4, when the count number of the horizontal synchronizing pulse counter circuit 172a and the value set in the VP register circuit 171a match, the horizontal synchronizing pulse counter circuit 172a.
Sets the vertical screen display signal A to "L".

At the time t5, the count number of the horizontal synchronizing pulse counter circuit 172b and the VP register circuit 171.
When the values of b match, the horizontal sync pulse counter circuit 17
2b sets the vertical screen display signal B to "H". At time t8, when the count number of the horizontal synchronizing pulse counter circuit 172b and the value set in the VP register circuit 171b match, the horizontal synchronizing pulse counter circuit 172b.
Sets the vertical screen display signal B to "L".

In this way, the vertical screen display signal generation circuit 170 sets the vertical screen display signal A to "H" during the period (V-DSPA) from the scanning line L line where the screen DSPA is displayed to the scanning line m line. Then, the vertical screen display signal B is set to "H" during a period (V-DSPB) from the scanning line n line where the screen DSPB is displayed to the scanning line p line.

FIG. 13 is a conceptual diagram of a screen displayed on the image display device according to the above-described operation. The screen DSPA is displayed while the vertical screen display signal A and the horizontal screen display signal A are "H", and the screen DSPB is displayed while the vertical screen display signal B and the horizontal screen display signal B are "H". Has been done. The horizontal character size of the two screens DSPA and DSPB is the same. That is, since the number of clocks for displaying the screen DSPA and the screen DSPB in the horizontal direction is fixed, and the cycles of the display clocks used by the two screens are the same, the period H of the horizontal screen display signal A is “H” The period H-DSPB is equal to the period -DSPA and the horizontal screen display signal B is "H".

[0038]

As described above, in the conventional technique using the PLL circuit as the image display clock generation circuit,
Since the cycle of the display clock output over the 1V period for displaying one screen is constant, there is a problem that the horizontal character display size width displayed on one screen is limited. It is possible to expand the display clock generated by the image display clock generation circuit by an integral multiple (one-fold double, double-fold, ... N-double), but since it is not possible to make delicate adjustments, there are various character display size widths. It lacks in sex.

The present invention has been made in view of the above,
An object of the present invention is to obtain an image display clock generation circuit that generates a display clock having a plurality of independent cycles in order to finely adjust the character display size of the image displayed on the screen during one vertical synchronization period.

[0040]

In order to achieve the above object, an image display clock generation circuit according to the present invention comprises:
A phase comparator that compares the phase of the horizontal synchronizing signal and the comparison clock generated by the frequency divider circuit, and a display clock that adjusts the oscillation frequency based on the phase comparison result of the horizontal synchronizing signal and the comparison clock. In the image display clock generation circuit, which includes a VCO circuit that generates a clock and a frequency divider circuit that divides the display clock to a predetermined value and generates the comparison clock, the display clock has different values. A plurality of frequency dividing circuits that generate a plurality of comparison clocks by frequency division; a display clock switching circuit that generates a control signal that selects one of the plurality of comparison clocks; And a selector circuit for selecting one from the plurality of comparison clocks.

According to the present invention, the comparison clocks having different cycles are generated by the plurality of frequency dividing circuits, and the display clock switching circuit selects the comparison clock from the plurality of comparison clocks. The oscillation frequency of the VCO circuit is controlled based on the selected comparison clock and horizontal synchronization signal.

In the image display clock generation circuit according to the next invention, in the above invention, when the display clock switching circuit displays a plurality of images within a vertical synchronization signal period, the horizontal synchronization signal is predetermined. It is characterized in that the control signal is switched at the timing counted by the number.

According to the present invention, the display clock switching circuit switches the control signal at a timing when the horizontal synchronizing signal is counted by a predetermined number when displaying a plurality of images within the vertical synchronizing signal period. I have to.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of an image display clock generation circuit according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of the image display clock generation circuit of this embodiment. The image display clock generation circuit according to the present embodiment includes a phase comparator 10
, Charge pump 20, loop filter 30, V
CO circuit 40, frequency dividing circuit A50, frequency dividing circuit B60
A selector circuit 70 and a display clock switching circuit 80.

The phase comparator 10 compares the phases of the horizontal synchronizing signal and the comparison clock selected by the selector circuit 70, and outputs a phase error signal.

The charge pump 20 boosts the phase error signal output from the phase comparator 10 to a level at which the voltage of the VCO circuit 40 can be controlled.

The loop filter 30 includes the charge pump 2
The high frequency component of the signal boosted at 0 is cut off.

The VCO circuit 40 controls transmission based on the output signal of the loop filter 30 and generates a display clock.

The frequency dividing circuit A50 is a frequency divider capable of setting up to N frequency division and divides the display clock generated by the VCO circuit 40 into a predetermined value.

The frequency dividing circuit B60 is a frequency divider capable of setting up to N'frequency division, and divides the display clock generated by the VCO circuit 40 into a predetermined value.

The display clock switching circuit 80 starts counting the number of pulses of the horizontal synchronizing signal triggered by the vertical synchronizing signal, and generates the display clock switching signal on a desired scanning line.

FIG. 2 shows a display clock switching circuit 80.
2 shows an example of the circuit configuration of FIG. The display clock switching circuit 80 is composed of a flip-flop circuit 90,
The display clock switching signal is switched by using the vertical screen display signal A generated by the screen display signal generation circuit (see FIG. 8) used in the conventional technique as a trigger. This display clock switching signal is a horizontal synchronization pulse counter circuit 172b of the vertical screen display signal generation circuit 170 shown in FIG.
It is also used to generate the reset signal.

The selector circuit 70, based on the display clock switching signal input from the display clock switching circuit 80, outputs the comparison clock A output from the frequency dividing circuit A50 or the comparison clock output from the frequency dividing circuit B60. Either one of the clocks for clock B is selected.

FIG. 3 shows an example of the circuit configuration of the selector circuit 70. The selector circuit 70 includes a NOR gate 7
1 to 73 and inverters 74 and 75. When the display clock switching signal is “L”, the comparison clock A is used as the comparison clock, and when the display clock switching signal is “H”, the comparison clock A is used. The comparison clock B is output to.

Referring to the time charts of FIGS. 4 to 7,
The operation of the screen display device in which the image display clock generation circuit and the screen display signal generation circuit of the present embodiment are combined will be described. The screens to be displayed are the same as those of the above-described conventional technique, and the two screens DSPA and the screen DSPB are changed from the scan line L line of a plurality of scan lines within a 1V period to the scan line m line,
It is assumed that PB is displayed from the scan line n line to the scan line p line. Further, the operation of the screen display signal generation circuit is the same as that of the conventional technique, and therefore detailed description thereof is omitted here.

As shown in FIG. 4, at time t0, the vertical synchronizing signal becomes "L", and the screen DSPA and the screen DSP are displayed.
The 1V period for displaying B is started and the vertical synchronizing signal is "L".
When changed to, the horizontal sync pulse counter circuits 172a and 172b of the vertical screen display signal generation circuit 170 are reset, and the vertical screen display signals A and B are set to "L". Further, the display clock switching circuit 80 of the image display clock generation circuit sets the display clock switching signal to "L".

When the display clock switching signal output from the display clock switching circuit 80 changes to "L", the selector circuit 70 outputs the comparison clock A generated by the frequency dividing circuit A50 to the phase comparator 10. To do.

The phase comparator 10 compares the horizontal synchronizing signal with the phase of the comparison clock output from the selector circuit 70, and when the phase of the comparing clock is delayed with respect to the horizontal synchronizing signal, the VCO circuit. When the phase difference of the comparison clock leads the signal for increasing the oscillation frequency of 40 relative to the horizontal synchronizing signal, the signal for decreasing the oscillation frequency of the VCO circuit 40 is output as the phase error signal.

When the phase error signal is input, the charge pump 20 stores the input phase error signal, boosts it to a level at which the voltage of the VCO circuit 40 can be controlled, and outputs it to the loop filter 30.

The loop filter 30 includes the charge pump 2
The high frequency component of the signal output from 0 is removed, and the voltage control signal is output to the VCO circuit 40.

The VCO circuit 40 adjusts the oscillation frequency on the basis of the voltage control signal input from the loop filter 30 and generates the display clock of the cycle T. The VCO circuit 40 outputs a display clock to the frequency dividing circuit A50, the frequency dividing circuit B60, and the screen display signal generating circuit.

The frequency dividing circuit A50 divides the display clock input from the VCO circuit 40 by N and selects the selector circuit 70.
The comparison clock A is output to.

The frequency dividing circuit B60 divides the display clock input from the VCO circuit 40 by N ', and the selector circuit 7
The comparison clock B is output to 0.

As described above, the image display clock generation circuit supplies the display clock having the cycle T until the display clock switching signal of the display clock switching circuit 80 changes (until it changes to the signal for selecting the frequency dividing circuit B60). Generate,
The display clock is output to the screen display signal generation circuit.

At time t1, when the horizontal synchronizing signal of the scanning line L line for displaying the screen DSPA changes to "L", the vertical screen display signal generating circuit 170 sets the vertical screen display signal A to "H". . At time t4, when the horizontal synchronizing signal of the scanning line m line at which the display of the screen DSPA ends becomes “L”, the vertical screen display signal generation circuit 170 sets the vertical screen display signal A to “L”. That is, the vertical screen display signal generation circuit 170 sets the vertical screen display signal A to "H" during the V-DSPA period from time t1 to time t4.

When the vertical screen display signal A changes to "L", the display clock switching circuit 80 of the image display clock generation circuit sets the display clock switching signal to "H". When the display clock switching signal changes to “H”, the selector circuit 70 generates the comparison clock output to the phase comparator 10 from the comparison clock A generated by the frequency dividing circuit A50 in the frequency dividing circuit B60. The clock is switched to the comparison clock B. As a result, the phase comparator 1
0 indicates that the display clock generated by the VCO circuit 40 is N ′.
The phases of the divided comparison clock B and the horizontal synchronizing signal are compared, and the oscillation frequency of the VCO circuit 40 is adjusted via the charge pump 20 and the loop filter 30. That is,
Since the comparison clock has changed from the comparison clock A to the comparison clock B, the VCO circuit 40 causes the cycle T ′.
Generates the display clock for.

On the other hand, in the horizontal synchronizing pulse counter circuit 172b of the vertical screen display signal generation circuit 170 of the screen display signal generation circuit, the display clock switching signal output from the display clock switching circuit 80 changes to "H". It is reset at the timing, and then the counting of the horizontal synchronizing signal is started.

At time t5, when the horizontal synchronizing signal of the scanning line n line which displays the screen DSPB changes to "L", the vertical screen display signal generating circuit 170 sets the vertical screen display signal B to "H". . At time t8, when the horizontal synchronizing signal of the scanning line p line at which the display of the screen DSPB ends becomes “L”, the vertical screen display signal generation circuit 170 sets the vertical screen display signal B to “L”. That is, the vertical screen display signal generation circuit 170 sets the vertical screen display signal B to "H" during the period of V-DSPB from time t5 to time t8.

At time t9, when the 1V period ends and the vertical synchronizing signal changes to "L", the display clock switching circuit 80 of the image display clock generating circuit is reset and the display clock switching signal is set to "L". To As a result, the selector circuit 70 switches the comparison clock output to the phase comparator 10 from the comparison clock B output from the frequency dividing circuit B60 to the comparison clock A output from the frequency dividing circuit A50. Since the comparison clock input to the phase comparator 10 has changed, the display clock output from the VCO circuit 40 has a cycle T ′.
To cycle T.

On the other hand, as shown in FIG. 5, in the horizontal screen display signal generation circuit 160 of the screen display signal generation circuit, the horizontal synchronizing signal of the scanning line L line for starting the display of the screen DSPA changes to "L". The counting of the display clock of the cycle T is started from the time t1, and the display time t2 of the screen DSPA.
Then, the horizontal screen display signal A is set to "H". At time t3 when the display of the screen DSPA ends, the horizontal screen display signal generation circuit 160 sets the horizontal screen display signal A to “L”. That is, the horizontal screen display signal generation circuit 160 determines that the H-DSPA from time t2 to time t3.
During this period, the horizontal screen display signal A is set to "H". Such an operation is repeated until the scanning line m line where the display of the screen DSPA ends.

When the display of the screen DSPA of the scanning lines m lines is completed and the vertical direction screen display signal A changes to "L", it is output from the display clock switching circuit 80 of the image display clock generation circuit as described above. The display clock switching signal is changed from “L” to “H”, and the comparison clock selected by the selector circuit 70 is the comparison clock A.
To the comparison clock B, and the cycle of the display clock switches from the cycle T to the cycle T ′.

At a time t5, when the horizontal synchronizing signal of the scanning line n line which starts the display of the screen DSPB changes to "L", the horizontal screen display signal generating circuit 160 counts the display clock of the period T '. Start and screen DSP
At time t6 when the display of B is started, the horizontal screen display signal B is set to "H". At time t7 when the display of the screen DSPB ends, the horizontal screen display signal generation circuit 160
Sets the horizontal screen display signal B to "L". That is, the horizontal screen display signal generation circuit 160 determines that the time t6.
The horizontal screen display signal B is set to "H" during the period of H-DSPB from time t7 to time t7. This kind of operation is displayed on screen DS
The process is repeated up to the scanning line p line where the display of PB is completed.

FIG. 6 is a conceptual diagram of the screen DSPA and the screen DSPB displayed on the image display device according to the above-described operation. The screen DSPA is displayed while the horizontal blanking line is in the vertical direction screen display signal A and the horizontal direction screen display signal A is "H", and the vertical return screen display signal B and the horizontal direction screen display signal B is in the "H" period. The screen DSPB is displayed. In the case of the conventional screen display shown in FIG. 13, the horizontal screen display signal A and the horizontal screen display signal B for performing horizontal control for displaying the screen DSPA and the screen DSPB become "H". Period H-DSPA and Period H
-DSPB times were the same. That is, the two screens were displayed in the same character size. However, when the image display clock generation circuit of the present invention is used, the screen DSP
A and a screen DSPB are horizontally controlled to display a horizontal screen display signal A and a horizontal screen display signal B are "H", a period H-DSPA and a period H-DSP.
B's time is different. This is because the number of display clocks required to display the screen DSPA and the screen DSPB is the same, but the period of the display clock differs between the period T and the period T '. Therefore, the two screens are displayed in different character sizes.

As described above, in the present embodiment, the frequency dividing circuit A
50 is a comparison clock A obtained by dividing the display clock by N.
The frequency dividing circuit B60 respectively generates a comparison clock B by dividing the display clock by N ', and outputs these two types of comparison clocks based on the display clock switching signal output from the display clock switching circuit 80. When the display of the screen DSPA is completed, the display clock switching circuit 80 outputs a display clock switching signal to the selector circuit 70 so as to switch the comparison clock, and the selector circuit 70 selects. To switch the comparison clock output to the phase comparator 10. As a result, the oscillation frequency of the VCO circuit 40 that generates the display clock is changed to change the cycle of the display clock. Therefore, the display clock having a different cycle even within the 1V period is not provided, without having a plurality of PLL circuits. Therefore, the character display size of the image displayed on the screen during one vertical synchronization period can be set to various character sizes without being limited to an integral multiple of the display clock.

[0076]

As described above, according to the present invention, the comparison clocks having different cycles are generated by the plurality of frequency dividing circuits, and the display clock switching circuit is configured to generate the plurality of comparison clocks. Since the comparison clock is selected from the above and the oscillation frequency of the VCO circuit is controlled on the basis of the selected comparison clock and the horizontal synchronizing signal, it is not necessary to have a plurality of PLL circuits and display for different cycles is possible. You can get the clock.

According to the next invention, the display clock switching circuit switches the control signal at the timing when the horizontal synchronizing signal is counted by a predetermined number when displaying a plurality of images within the vertical synchronizing signal period. Therefore, the character display size of the image displayed on the screen during one vertical synchronization period can be set to various character sizes without being limited to an integral multiple of the display clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image display clock generation circuit of the present invention.

FIG. 2 is a block diagram showing a configuration of a display clock switching circuit shown in FIG.

3 is a block diagram showing a configuration of a selector circuit shown in FIG.

FIG. 4 is a time chart for explaining the operation of the image display clock generation circuit of the present invention.

FIG. 5 is a time chart for explaining the operation of the image display clock generation circuit of the present invention.

FIG. 6 is a conceptual diagram of a display screen of an image display device using the image display clock generation circuit of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional image display clock generation circuit using a PLL circuit.

FIG. 8 is a block diagram showing a configuration of a conventional image display signal generation circuit.

9 is a block diagram showing a configuration of a horizontal screen display signal generation circuit shown in FIG.

10 is a block diagram showing a configuration of a vertical screen display signal generation circuit shown in FIG.

FIG. 11 is a time chart for explaining the operation of the conventional image display clock generation circuit.

FIG. 12 is a time chart for explaining the operation of the conventional image display clock generation circuit.

FIG. 13 is a conceptual diagram of a display screen of an image display device using a conventional image display clock generation circuit.

[Explanation of symbols]

10,110 Phase comparator, 20,120 Charge pump, 30,130 Loop filter, 40,140 V
CO circuit, 50 frequency dividing circuit A, 60 frequency dividing circuit B, 70
Selector circuit, 71, 72, 73 NOR gate, 7
4,75 inverter, 80 display clock switching circuit, 90 flip-flop circuit, 150 frequency dividing circuit, 160 horizontal screen display signal generating circuit, 161
a, 161b HP register circuit, 162a, 162b
Clock pulse counter circuit for display, 170 Vertical screen display signal generation circuit, 171a, 171b VP register circuit, 172a, 172b Horizontal sync pulse counter circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 5/26 G09G 5/26 E H03L 7/08 H04N 5/06 Z H04N 5/06 H03L 7/08 N F-term (reference) 5C020 AA40 CA15 5C080 BB05 DD21 EE21 JJ02 JJ03 JJ04 5C082 AA01 BA02 BC19 CA33 CA34 CA81 CA84 CB05 MM10 5J106 PP03 QQ01 RR06 RR20

Claims (2)

[Claims] 1. A phase comparator for comparing the phases of a horizontal synchronizing signal and a comparison clock generated by a frequency divider circuit, and an oscillation frequency based on a result of phase comparison between the horizontal synchronizing signal and the comparison clock. An image display clock generation circuit comprising: a VCO circuit that adjusts and generates a display clock; and a frequency divider circuit that divides the display clock to a predetermined value to generate the comparison clock. A plurality of frequency dividing circuits for generating a plurality of comparison clocks by respectively dividing the clocks with different values; and a display clock switching circuit for generating a control signal for selecting one of the plurality of comparison clocks. An image display clock generation circuit, further comprising: a selector circuit that selects one from the plurality of comparison clocks based on the control signal. 2. The display clock switching circuit switches the control signal at a timing when the horizontal synchronizing signal is counted by a predetermined number when displaying a plurality of images within a vertical synchronizing signal period. The image display clock generation circuit according to claim 1.