JP2008282933A - Interconnection of semiconductor device, and method of forming the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide narrow-pitch interconnections of a semiconductor device, and to provide a method of forming the same. <P>SOLUTION: The semiconductor device includes first interconnections 13, which are formed on a substrate 11 and have a side face slanted, in such a manner as to be widened upwards from the substrate 11 side and second interconnections 15 which are separated from the first interconnections 13 by insulating films 14 and have a side face slanted, in such a manner as to widen toward the substrate 11 side from above. Thus, an interconnection pitch L1, which is half the mask pattern pitch can be obtained. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a wiring of a semiconductor device and a method for forming the same.

  Corresponding to miniaturization and high integration of semiconductor devices, there is a need for a wiring and a method for forming the wiring that can form a narrow pitch wiring pattern accurately and easily.

  In conventional wiring, an inorganic insulating film is formed on a wiring layer such as an Al alloy, a resist film formed on the inorganic insulating film is patterned, and the inorganic insulating film is etched using the resist film as a mask. It was formed by etching the wiring layer as a mask.

  However, as the wiring pitch becomes narrower, it is becoming difficult to form the wiring at a predetermined pitch because the resist resolution and processing technique are limited.

  On the other hand, a wiring of a semiconductor device including an interlayer film for forming a buried wiring groove that can be processed with a very narrow wiring pitch and a method for forming the wiring are known (for example, see Patent Document 1).

In the wiring of the semiconductor device disclosed in Patent Document 1 and the manufacturing method thereof, the first insulating interlayer film formed on the semiconductor substrate has a wedge-shaped convex cross section with a spacing approximately half the desired wiring spacing. The shape portion is formed on the surface thereof.
A second insulating interlayer film is formed in a wave shape on the first insulating interlayer film so as to cover the convex portion of the first insulating interlayer film, and a wiring is formed in a groove formed by the second insulating interlayer film. A layer is formed.

However, the wiring structure of a semiconductor device and the method for forming the same disclosed in Patent Document 1 have a problem that it is difficult to increase the height of the convex portion because the wedge-shaped convex portion has a steep inclination angle. is there. Further, the wedge-shaped convex portion having a narrow cross section may be damaged during the process.
As a result, there is a problem that it is difficult to form a wiring having a high aspect ratio.
JP 2006-80230 A

  A narrow pitch semiconductor device wiring and a method of forming the same are provided.

  The wiring of the semiconductor device of one embodiment of the present invention is formed on the substrate, separated from the first wiring by the first wiring having a side surface inclined in a divergent shape from the substrate side toward the upper side, and the upper side And a second wiring having a side surface inclined in a divergent shape toward the substrate side.

  According to another aspect of the present invention, there is provided a method for forming a wiring of a semiconductor device, comprising: forming a plurality of first resist films having a first pattern on a silicon nitride film formed on a substrate; The silicon nitride film is anisotropically etched by adjusting the selection ratio between the first resist film and the silicon nitride film using the mask as a mask, and has a plurality of side surfaces inclined in a divergent shape from above toward the substrate side Leaving the silicon nitride film, removing the first resist film, filling the silicon nitride film with a silicon oxide film, removing the excess silicon oxide film, and exposing the silicon nitride film; Forming a second resist film having a second pattern equal to the first pattern on the silicon nitride film, and using the second resist film as a mask, The silicon oxide film is anisotropically etched by adjusting the selection ratio between the dyst film and the silicon oxide film, leaving the silicon oxide film on the inclined side surface of the silicon nitride film, and upward from the substrate side. Forming a first groove having a side surface inclined in a divergent shape toward the end, removing the second resist film, and selectively removing the exposed silicon nitride film, from above to the substrate side. A step of forming a second groove having side surfaces inclined in a divergent shape, and a first groove separated by the left silicon oxide film embedded in the first groove and the second groove, respectively. Forming a wiring and a second wiring.

  According to the present invention, a wiring of a semiconductor device having a narrow pitch and a method for forming the wiring can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  A wiring of a semiconductor device and a method for forming the same according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing wiring of a semiconductor device, and FIGS. 2 to 6 are cross-sectional views showing the forming method in the order of steps.

  As shown in FIG. 1, the wiring 10 of the semiconductor device of this embodiment is formed on a substrate (semiconductor substrate) 11 via an insulating film 12, for example, a silicon oxide film, and spreads upward from the substrate 11 side. And a second wiring 15 having a side surface that is separated by an insulating film 14, for example, a silicon oxide film, and has a side surface that slopes toward the substrate 11. ing. Hereinafter, the insulating film 14 is also referred to as a spacer.

  Further, an interlayer insulating film 16 for protecting the first wiring 13 and the second wiring 15 is formed on the first wiring 13 and the second wiring 15.

The first wiring 13 has a tapered side surface and a trapezoidal cross section. The second wiring 15 has a shape obtained by turning the first wiring 13 upside down.
In the first wiring 13 and the second wiring 15, the upper end portion 17 of the first wiring 13 and the lower end portion 18 of the second wiring 15 facing each other across the insulating film 14 are both on a straight line 19 perpendicular to the substrate 11. It is formed as follows.

  For example, the wiring pitch L1 of the first wiring 13 and the second wiring 15 is 0.3 μm, the trapezoidal upper base is 0.1 μm, the lower base is 0.3 μm, the height is 0.2 μm, and the thickness of the insulating film 14 The first wiring 13 and the second wiring 15 having a line and space (L / S) of 1: 1 can be obtained by setting the distance to 0.1 μm.

  Further, an internal circuit (not shown) having a wiring pitch of 2L1 or more is formed in the internal circuit region 20 around the first wiring 13 and the second wiring 15.

Next, a method for forming the wiring 10 of the semiconductor device will be described.
As shown in FIG. 2A, a silicon oxide film 12 having a thickness of about 0.2 μm is formed on a substrate 11 (not shown) by, for example, a CVD (Chemical Vapor Deposition) method. For example, a silicon nitride film 31 having a thickness of about 0.2 μm is formed by plasma CVD, for example, and a first resist film 32 is formed on the silicon nitride film 31.

  Next, as shown in FIG. 2B, a first photomask 33 is used in which the first max pattern width L2 is equal to the wiring pitch L1, and the first max pattern pitch L3 is twice the first max pattern width L2. A plurality of first resist films 34 are formed by patterning by exposure and development by photolithography.

As shown in FIG. 8, the first photomask 33 is a photomask that has a pattern only in a region having a narrow wiring pitch such as a memory cell and has a low coverage.
For example, in the first photomask 33, a first max pattern 33a having a plurality of line-shaped patterns having a width L2 and a pitch L3 is formed in the center portion, and the first photomask 33 corresponds to a circuit region 20 such as a decoder formed around the memory cell. Further, no pattern is formed in the peripheral region 33b.

Next, as shown in FIG. 2C, the silicon nitride film 31 is anisotropically etched using the first resist film 34 as a mask.
In the anisotropic etching, RIE using a mixed gas of oxygen gas for etching the first resist film 34 and fluorine-based gas (CHF ₃ , CF ₄ , SF _6, etc.) for etching the silicon nitride film 31 is performed. (Reactive Ion Etching) is performed under the condition that the selection ratio between the silicon nitride film 31 and the first resist film 34 is small.

That is, the difference between the etching rate of the silicon nitride film 31 and the etching rate of the first resist film 34 is reduced so that the first resist film 34 is etched while the silicon nitride film 31 is etched.
As a result, since the coverage of the first resist film 34 in the RIE etching region is low, the silicon nitride film 35 becomes thinner as the first resist film 34 becomes thinner.

As a result, a plurality of silicon nitride films 35 having side surfaces inclined in a divergent shape from the top toward the 11 substrate side are left.
The inclination angle of the side surface of the silicon nitride film 35 is adjusted to a half-value angle of about 30 ° by adjusting the selection ratio.

  Next, as shown in FIG. 3A, the remaining portion of the first resist film 34 is removed using, for example, an ashing technique using low damage H2 / He.

  Next, as shown in FIG. 3B, a silicon oxide film 36 is formed by, eg, CVD, and the silicon nitride film 35 is embedded with the silicon oxide film 36.

  Next, as shown in FIG. 3C, the excess silicon oxide film 36 is polished up to the surface of the silicon nitride film 35 by CMP (Chemical Mechanical Polishing) to expose the silicon nitride film 35.

  Next, as shown in FIG. 4A, a second resist film 37 is formed on the substrate 11 (not shown).

  Next, as shown in FIG. 4B, a second photomask 38 having a second max pattern width L4 equal to the first max pattern width L2 and a second max pattern pitch L5 equal to the first max pattern pitch L3 is formed. A plurality of second resist films 39 are formed by patterning by exposure and development by photolithography.

As shown in FIG. 9, the second photomask 38 is a photomask having a high coverage with a pattern of a region having a narrow wiring pitch such as a memory cell and a pattern of a region having a wide wiring pitch such as a peripheral circuit. is there.
For example, in the second photomask 38, a second max pattern 38a having a plurality of line patterns having a width L4 and a pitch L5 is formed in the center, and a circuit region 20 such as a decoder is provided in a peripheral region 38b around the memory cell. The pattern according to is formed.

Next, as shown in FIG. 4C, the silicon oxide film 36 is anisotropically etched using the second resist film 39 as a mask until the silicon oxide film 12 is exposed.
In the anisotropic etching, the silicon oxide film 36 and the second resist film are formed by an RIE method using a mixed gas of oxygen gas for etching the second resist film 39 and a chlorine-based gas for etching the silicon oxide film 36. This is performed under the condition that the selection ratio of 39 is small.

That is, the difference between the etching rate of the silicon oxide film 36 and the etching rate of the second resist film 39 is reduced so that the second resist film 39 is etched while the silicon oxide film 36 is etched.
As a result, since the coverage of the second resist film 39 in the RIE etching region is high, the second resist film 39 is not so thin and the silicon oxide film 36 is preferentially thinned.

  As a result, the silicon oxide film 40 is left on the side surface of the silicon nitride film 35, and a first groove 41 having a side surface inclined in a divergent shape from the substrate 11 side upward is formed.

  The inclination angle of the side surface of the silicon oxide film 36 is adjusted to be approximately the same as that of the silicon nitride film 35 by adjusting the selection ratio.

  A layer serving as a stopper for anisotropic etching is not particularly provided between the silicon oxide film 36 and the silicon oxide film 12, but the anisotropic etching can be appropriately performed by managing the etching conditions (time, etc.). .

  Next, as shown in FIG. 5A, the remaining portion of the second resist film 39 is removed using, for example, an ashing technique using low damage H2 / He.

Next, as shown in FIG. 5B, the silicon nitride film 35 is selectively removed by isotropic etching.
The isotropic etching is performed, for example, by a CDE (Chemical Dry Etching) method under conditions with a high selectivity of the silicon oxide film 40 to the silicon nitride film 35.

As a result, a second groove 42 is formed which is separated by the silicon oxide film 40 and has a side surface inclined in a divergent shape from the upper side toward the substrate 11 side.
Next, as shown in FIG. 5C, a copper (Cu) film 43 is formed by, for example, an electroless plating method, and the silicon oxide film 40 is embedded with the copper (Cu) film 43.

  Next, as shown in FIG. 6A, the excess copper (Cu) film 43 is polished to the surface of the silicon oxide film 40 by CMP to expose the silicon oxide film 40.

  As a result, copper (Cu) is embedded in the first groove 41 and the second groove 42 and is separated by the insulating film 14 from the first wiring 13 having a side surface inclined in a divergent shape upward from the substrate 11 side. As a result, the second wiring 15 having a side surface inclined in a divergent shape from the upper side toward the substrate 11 side is formed.

  The wiring pitch L1 between the first wiring 13 and the second wiring 15 is ½ of the first mask pattern pitch L3 and the second mask pattern pitch L5, and a wiring pitch narrower than the mask pattern pitch can be obtained.

  Next, as shown in FIG. 6B, an interlayer insulating film 44 serving as a protective film, for example, a TEOS (Tetra Ethyl Ortho Silicate) film by a CVD method is formed on the first wiring 13 and the second wiring 15.

  As a result, the first wiring 13 and the second wiring 15 function as wirings that connect between logic elements (not shown) of the semiconductor device (not shown).

  As described above, in this embodiment, the side surface of the first wiring 13 is inclined from the substrate 11 side upward toward the upper side and separated by the edge film 14, and the side surface of the second wiring 15 is separated from the substrate 11 from above. It is inclined in a divergent shape toward the side.

As a result, the wiring pitch L1 of the first wiring 13 and the second wiring 15 is set to a narrow pitch that is ½ of the first and second mask pattern pitches L3 and L5 of the first and second photomasks 33 and 38. Can do.
Therefore, the wiring 10 of the semiconductor device having a narrower pitch than the mask pattern pitch and the method for forming the same are obtained.

  Although the case where the wiring 10 is a single-layer wiring has been described here, the wiring 10 can be formed into a multilayer wiring by repeating the steps shown in FIGS.

  That is, as shown in FIG. 7A, the same silicon nitride film 51 as the silicon nitride film 31 is formed on the interlayer insulating film 44.

  Next, as shown in FIG. 7B, a wiring 52 having the first wiring 13 and the second wiring 15 separated by the insulating film 14 is formed according to the steps shown in FIGS. By forming the interlayer insulating film 53 on the two-layer wiring, a two-layer wiring is obtained.

  The wiring 10 and the wiring 52 are connected through a via 54. For example, the first wiring 13 of the wiring 10 is connected to the first wiring 13 of the wiring 52, and the second wiring 15 of the wiring 10 is connected to the second wiring 15 of the wiring 52.

  Similarly, as shown in FIG. 7C, according to the steps shown in FIGS. 2 to 6, the wiring 55 having the first wiring 13 and the second wiring 15 separated by the insulating film 14 is formed. A three-layer wiring is obtained by forming the interlayer insulating film 56 on the substrate.

  The wiring 52 and the wiring 55 are connected through a via 57. For example, the first wiring 13 of the wiring 52 is connected to the first wiring 13 of the wiring 55, and the second wiring 15 of the wiring 52 is connected to the second wiring 15 of the wiring 55.

  Further, by shifting the lower wiring and the upper wiring by the wiring pitch L1, the first wiring of the lower wiring and the second wiring of the upper wiring are connected, or the second wiring of the lower wiring and the upper wiring are connected. The first wiring can also be connected.

Although the case where the wiring widths of the first wiring 13 and the second wiring 15 are the same has been described, they may be different.
The wiring lengths and wiring patterns of the first wiring 13 and the second wiring 15 are not particularly limited and can be freely formed.

  FIG. 10 is a cross-sectional view showing wiring of a semiconductor device according to the second embodiment of the present invention. In the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different portions will be described.

  The difference between the present embodiment and the first embodiment is that the cross section of the first wiring has a triangular shape and the cross section of the second wiring has a shape obtained by vertically inverting the first wiring.

  That is, as shown in FIG. 10, in the wiring 60 of the semiconductor device of this embodiment, the first wiring 61 has a tapered side surface and a triangular cross section. The second wiring 62 has a shape obtained by inverting the first wiring 61 upside down.

  In the first wiring 61 and the second wiring 62, a straight line 65 connecting the upper end portion 63 of the first wiring 61 and the lower end portion 64 of the second wiring 62 facing each other with the insulating film 14 interposed therebetween is perpendicular to the substrate 11. It arrange | positions so that it may exist on the straight line 65. FIG.

  Thereby, the 1st wiring 61 and the 2nd wiring 62 whose line and space (L / S) are 1: 1 are obtained.

The wiring pitch L7 of the first wiring 61 and the second wiring 62 is narrowed to ½ of the third max pattern pitch L8.
By setting the third max pattern pitch L8 to ½ of the first and second mask pitch patterns L3 and L5, the wiring pitch L7 becomes a narrow pitch that is ½ of the wiring pitch L1. Thereby, it is possible to obtain the wiring 60 having a narrower pitch than the wiring 10.

  The wiring 60 of the present embodiment is not connected to another wiring through a via in the middle of the wiring 60, but a connection pad is provided at the end of the wiring 60 and the connection pad is connected to another wiring through the via. Suitable for

  Further, when the lower wiring and the upper wiring are shifted by the wiring pitch L7 and the wiring 60 is formed into a multilayer wiring, the first wiring of the lower wiring and the second wiring of the upper wiring can be connected.

  As described above, in this embodiment, the cross section of the first wiring 61 is triangular, and the cross section of the second wiring 62 separated by the insulating film 14 is a shape obtained by inverting the first wiring 61. As a result, there is an advantage that the wiring 60 having a narrower pitch than the wiring 10 can be obtained.

Sectional drawing which shows the wiring of the semiconductor device which concerns on Example 1 of this invention. Sectional drawing which shows the wiring formation process of the semiconductor device which concerns on Example 1 of this invention in order. Sectional drawing which shows the wiring formation process of the semiconductor device which concerns on Example 1 of this invention in order. Sectional drawing which shows the wiring formation process of the semiconductor device which concerns on Example 1 of this invention in order. Sectional drawing which shows the wiring formation process of the semiconductor device which concerns on Example 1 of this invention in order. Sectional drawing which shows the wiring formation process of the semiconductor device which concerns on Example 1 of this invention in order. Sectional drawing which shows the wiring formation process of the semiconductor device which concerns on Example 1 of this invention in order. 1 is a diagram showing a first photomask of a semiconductor device according to Example 1 of the present invention. FIG. 5 is a diagram illustrating a second photomask of the semiconductor device according to the first embodiment of the invention. Sectional drawing which shows the wiring of the semiconductor device which concerns on Example 2 of this invention.

Explanation of symbols

10, 52, 55, 60 Wiring 11 Semiconductor substrate 12, 14 Insulating film 13, 61 First wiring 15, 62 Second wiring 16, 44, 53, 56 Interlayer insulating film 17, 63 Upper end 18, 64 Lower end 19, 65 Straight line 31, 51 Silicon nitride film 32, 34 First resist film 33 First photomask 33a First mask pattern 33b, 38b Peripheral region 36, 40 Silicon oxide film 37, 39 Second resist film 38 Second photomask 38a First 2 mask pattern 41 1st groove | channel 42 2nd groove | channel 43 Copper (Cu)
54, 57 Vias L1, L7 Wiring pitch L2 First mask pattern width L3 First mask pattern pitch L4 Second mask pattern width L5 Second mask pattern pitch L6 Spacer width L8 Third mask pattern pitch

Claims (5)

A first wiring formed on a substrate and having a side surface inclined in a divergent shape from the substrate side upward;
A second wiring having a side surface that is separated from the first wiring by an insulating film and inclined in a divergent shape from above toward the substrate;
A wiring for a semiconductor device, comprising:   2. The wiring of a semiconductor device according to claim 1, wherein a cross section of the first wiring is trapezoidal or triangular, and a cross section of the second wiring is a shape obtained by inverting the first wiring.   3. The semiconductor device according to claim 2, wherein an upper end portion of the first wiring and a lower end portion of the second wiring facing each other with the insulating film interposed therebetween are on the same straight line perpendicular to the substrate. Wiring.   A plurality of the first wirings and the second wirings are formed on the substrate via an interlayer insulating film, and at least the lower first wirings or the second wirings are connected to the upper first wirings or vias vias. The wiring of the semiconductor device according to claim 1, wherein the wiring is electrically connected to the second wiring. Forming a plurality of first resist films having a first pattern on a silicon nitride film formed on a substrate;
Using the first resist film as a mask, the silicon nitride film is anisotropically etched by adjusting the selection ratio between the first resist film and the silicon nitride film, and inclined in a divergent shape from above to the substrate side Leaving a plurality of silicon nitride films having side surfaces formed;
Removing the first resist film, embedding the silicon nitride film with a silicon oxide film, removing the excess silicon oxide film, and exposing the silicon nitride film;
Forming a second resist film having a second pattern equal to the first pattern on the silicon nitride film;
Using the second resist film as a mask, the silicon oxide film is anisotropically etched by adjusting the selection ratio between the second resist film and the silicon oxide film, and the silicon oxide film is formed on the inclined side surface of the silicon nitride film. Leaving a film and forming a first groove having a side surface inclined in a divergent shape from the substrate side upward;
Removing the second resist film, selectively removing the exposed silicon nitride film, and forming a second groove having a side surface inclined in a divergent shape from above toward the substrate side;
Embedding a metal film in each of the first groove and the second groove, and forming a first wiring and a second wiring separated by the left silicon oxide film;
A method of forming a wiring of a semiconductor device, comprising:

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