JP2008281641A - Control method of display driver and driving method of display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method of display driver capable of suppressing noise radiated from a display panel and to provide a driving method of the display panel. <P>SOLUTION: Each display driver for applying a driving pulse by which the display panel should be driven to each of two or more electrodes of electrodes. That is, when the driving pulses are applied simultaneously to the respective electrodes of display panels, each display driver is controlled such that the timing of falling edge in the driving pulses is differentiated from every two or more semiconductor chips (semiconductor chip group) on which the respective drivers are mounted. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display driver control method for sending a drive pulse for driving a display panel in which capacitive light emitting elements are arranged to the display panel, and a method for driving the display panel.

   A display device (see Patent Document 1) on which a plasma display panel (PDP) is mounted as a display panel using a plasma element as a capacitive light emitting element has been commercialized.

  FIG. 1 is a diagram showing a schematic configuration of such a display device.

In FIG. 1, a PDP 10 as a display panel includes row electrodes Y _{1 to} Y _n and X ₁ that form a row electrode pair corresponding to each display line (n rows) in one screen with a pair of X and Y. To X _n and column electrodes D _{1 to} D _m that are orthogonal to the row electrode pairs and correspond to each column (m columns) of one screen across the dielectric layer and the discharge space. Discharge cells as capacitive light emitting elements are formed at the intersections between one pair of row electrodes (X, Y) and one column electrode D.

  The drive control circuit 50 converts the luminance level indicated by the video signal into pixel data for each pixel, and supplies this to the address driver 20. Further, the drive control circuit 50 supplies various control signals for driving the PDP 10 to gradation based on the subfield method to each of the X row electrode driver 30 and the Y row electrode driver 40. As a result, the address driver 20, the X row electrode driver 30, and the Y row electrode driver 40 are shown in FIG. 2 in each of a plurality of subfields each including an address period and a sustain period for each field or frame in the video signal. The PDP 10 is driven as shown.

That is, in the address period of each subfield, the address driver 20 generates a pixel data pulse having a voltage value corresponding to the logic level for each pixel data bit, and this is generated for each display line (m). The pixel data pulse group DP is sequentially applied to the column electrodes D _{1 to} D _m of the PDP 10. In FIG. 2, an excerpt only the pixel data pulse group DP _j of m pixel data pulses corresponding to the discharge cells belonging respectively to the j display line of the PDP10 in the first to n-th display line Show. Furthermore, in the address period, Y row electrode driver 40, a write (or erase) the pixel data in synchronism with the pixel data pulse group DP and scan pulse SP to be selected display lines to be row electrodes Y ₁ ~ sequentially alternatively applied to Y _n, respectively. Here, in the discharge cells belonging to the row electrode Y to which the scan pulse SP is applied, an address discharge is selectively generated according to the pulse voltage of the pixel data pulse, and wall charges are formed (or erased). . As a result, each discharge cell is set to one of a state in which wall charges exist (lighting mode) and a state in which no wall charges exist (light-off mode).

The sustain period, X row electrode driver 30 and the Y row electrode driver 40 repeatedly many times corresponding to the luminance weight of each subfield, such as sustain pulses IP _X and IP _Y to the row electrodes X ₁ to X 2 It is applied to each of _n and row electrodes Y ₁ to Y _n. At this time, in response to the application of the sustain pulse, only the discharge cells set in the lighting mode are repeatedly subjected to the sustain discharge, and the light emission state associated with the discharge is maintained.

In at least one subfield of each subfield, the operation in the reset period is executed prior to the address period. In the reset period, the Y row electrode driver 40 generates a reset pulse RP _Y as shown in FIG. 2 and applies it to all the row electrodes Y. As a result, a reset discharge is generated in all the discharge cells, and the residual wall charge amount in each discharge cell is initialized.

Here, as shown in FIG. 3, the Y row electrode driver 40 includes a reset driver unit RSD for generating the reset pulse RP _Y , a scan driver unit SCD for generating the scan pulse SP, and a sustain pulse IP _Y. A sustain driver SUD unit (see FIG. 4 of Patent Document 1) for generation is mounted.

As shown in FIG. 2, in the reset period, both the switching element S17 of the reset driver unit RSD and the switching element S21 of the scan driver unit SCD are switched from the off state to the on state. As a result, the voltage Vh generated at the positive terminal of the power source B6 provided in the scan driver unit SCD is applied to the row electrode Y via the switching element S21. Therefore, as shown in FIG. Transition to the state. At this time, the positive voltage Vs of the power source B3 of the sustain driver unit SUD is applied to the row electrode Y via the resistor R1 and the power source B6. Therefore, the voltage on the row electrode Y gradually increases with the passage of time from the state of the voltage Vh as shown in FIG. 2 due to the time constant between the load capacitance C _{0 of the} PDP 10 and the resistor R1. When the voltage on the row electrode Y reaches the voltage (Vs + Vh) generated by the series connection of the power supply B3 and the power supply B6, the switching elements S17 and S21 are switched to the OFF state, and the switching elements S18 and S22 are switched from the OFF state. Switch to the on state. As a result, a current path CR2 including the switching elements S22 and S18, the resistor R2, and the diode D7 is formed, and the voltage on the row electrode Y gradually decreases as shown in FIG.

That is, in the reset period, by the two power supply (B3, B6) connected in series, and generates a reset pulse RP _y having a peak voltage as shown in FIG. 2 (Vs + Vh), which row electrodes Y ₁ to Y _n It is applied to each at once. At this time, depending on the application of the reset pulse RP _y, simultaneously reset discharge in all discharge cells is caused. Then, the charging / discharging current accompanying this reset discharge flows into the PDP 10 all at once through the row electrodes Y _{1 to} Y _n , and noise noise is radiated from the casing of the PDP 10 due to the influence. .
Japanese Patent Laid-Open No. 2004-199026

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a display driver control method and a display panel drive method capable of suppressing noise radiated from the display panel. It is.

  The display driver control method according to claim 1 controls each of the n display drivers that applies a drive pulse for driving the display panel to each of n (n: integer of 2 or more) electrodes of the display panel. A method of controlling a display driver, wherein the display driver is mounted on k (k: integer less than or equal to n) semiconductor chips, and the drive pulse is applied to each of the n electrodes simultaneously. The display driver is controlled so that the timing of the falling edge in the drive pulse is different for each semiconductor chip or for each semiconductor chip group.

  According to a second aspect of the present invention, there is provided a display driver control method comprising: n display drivers that apply a drive pulse for driving a display panel to each of n (n: integer of 2 or more) electrodes of the display panel. A method of controlling a display driver to be controlled, wherein the display driver is mounted on k (k: integer less than or equal to n) semiconductor chips, and the driving pulse is applied to each of the n electrodes simultaneously. First, the display driver is controlled so that the timing of the falling edge in the drive pulse is different for each semiconductor chip or for each semiconductor chip group.

  According to a fourth aspect of the present invention, there is provided a display driver control method comprising: applying n drive drivers for driving a display panel to each of n (n: an integer of 2 or more) electrodes of the display panel; A control method for a display driver to be controlled, each of which includes a first power source that generates a first potential corresponding to a peak potential of the drive pulse, and a switching element that applies the first potential to the electrode in response to a control signal Are mounted on k (k: an integer less than or equal to n) semiconductor chips, and when the drive pulse is applied to each of the n electrodes simultaneously, The switching element is controlled so that the timing of stopping the application differs for each semiconductor chip or for each semiconductor chip group.

  According to a fifth aspect of the present invention, there is provided a display driver control method in which each of n display drivers for applying a drive pulse for driving a display panel to each of n (n: an integer of 2 or more) electrodes of the display panel. A control method for a display driver to be controlled, each of which includes a first power source that generates a first potential corresponding to a peak potential of the drive pulse, and a switching element that applies the first potential to the electrode in response to a control signal Are mounted on k (k: an integer less than or equal to n) semiconductor chips, and when the drive pulse is applied to each of the n electrodes simultaneously, The switching element is controlled so that the timing of starting the application differs for each semiconductor chip or for each semiconductor chip group.

  The display panel driving method according to claim 7 is a display panel in which display cells are formed at intersections of a plurality of row electrode pairs and a plurality of column electrodes arranged to intersect the row electrode pairs. And a data pulse corresponding to the luminance level indicated by the input video signal is applied to each of the column electrodes, and a base pulse is applied to each row electrode of each of the row electrode pairs. An addressing step for setting each of the display cells to one of a lighting mode and a light-off mode by alternately applying a scanning pulse to each one of the row electrodes while applying The timing of the falling edge in the pulse is made different for each row electrode group composed of a plurality of row electrodes.

  The display panel driving method according to claim 8 is a display panel in which display cells are formed at intersections of a plurality of row electrode pairs and a plurality of column electrodes arranged to cross the row electrode pairs. A display panel driving method comprising: a reset step of initializing the state of each of the display cells by applying a reset pulse to each one of the row electrodes of each of the row electrode pairs; The timing of the falling edge is made different for each row electrode group composed of a plurality of row electrodes.

  Each display driver that applies a drive pulse for driving the display panel to each of the plurality of electrodes of the display panel is controlled as follows. That is, when the drive pulse is applied to each electrode of the display panel at the same time, the timing of the falling edge in the drive pulse is different for each of a plurality of semiconductor chips (or semiconductor chip groups) on which the display driver is mounted. Control each display driver. According to such control, even when a drive pulse is applied to all the electrodes of the display panel at the same time, the amount of current flowing into the display panel at the same time as the drive pulse is applied is temporally dispersed. . Therefore, radiation noise from the display panel casing that is generated by a steep large current flow is suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 4 is a diagram showing a schematic configuration of a plasma display device adopting a display driver control method and a display panel drive method according to the present invention.

In FIG. 4, the PDP 10 as a plasma display panel has column electrodes D _{1 to} D _m extending in the vertical direction (vertical direction) of the two-dimensional display screen, respectively, and extending in the horizontal direction (horizontal direction). and X and the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n Y are arranged alternately is formed. Note that one display line of the PDP 10 is displayed by a pair of row electrodes X and Y adjacent to each other. That is, the PDP 10 includes a first display line composed of row electrodes X ₁ and Y ₁ , a second display line composed of row electrodes X ₂ and Y ₂ ,..., An nth display line composed of row electrodes X _n and Y _n. Is provided. A discharge space filled with a discharge gas is provided between the _first to nth display lines and the column electrodes D _{1 to} D _m, and each intersection of the row electrode and the column electrode including the discharge space is provided. A discharge cell (display cell) corresponding to the pixel is formed in the part.

  The drive control circuit 500 converts the input video signal into pixel data for each pixel, and divides this pixel data into each bit digit to obtain pixel data bits. Then, the drive control circuit 500 supplies pixel data bits to the address driver 20 for each display line (m) in the same bit digit. Further, the drive control circuit 500 sends various control signals (described later) to the address driver 20, the X row electrode driver 30, and the Y row electrode driver in order to drive the PDP 10 in accordance with a light emission drive sequence based on the subfield method as shown in FIG. 400 is supplied to each. The light emission drive sequence shown in FIG. 5 includes N subfields SF1 to SF (SF) each including an address period W and a sustain period I for each field or frame (hereinafter referred to as a unit display period) in the input video signal. N), the PDP 10 is driven in gradation. In the light emission drive sequence shown in FIG. 5, the reset period R is included only in the first subfield SF1.

  Each of the address driver 20, the X row electrode driver 30, and the Y row electrode driver 400 receives various drive pulses as shown in FIG. 6 in the reset period R, address period W, and sustain period I, respectively, as shown in FIG. Applied to X and Y.

That is, first, in the reset period R, the X row electrode driver 30 applies a reset pulse RP _X having a negative polarity peak potential as shown in FIG. 6 to each of the row electrodes X _{1 to} X _n . Moreover, in the reset period R, in synchronism with the reset pulse RP _X, Y row electrode driver 400 generates a reset pulse RP _Y having a positive peak potential as shown in FIG. 6, which row electrodes Y ₁ ~ Applied to each of Y _n . In response to the application of these reset pulses RP _X and RP _Y , a reset discharge is generated in all the discharge cells, and the residual wall charge amount in each discharge cell is initialized to a predetermined value.

Next, in the address period W, the address driver 20 generates a pixel data pulse having a voltage value corresponding to the logic level for each pixel data bit, and this is generated as pixel data for one display line (m). A pulse group DP is sequentially applied to the column electrodes D _{1 to} D _m of the PDP 10 as shown in FIG. Further, in the address period W, the Y-row electrode driver 400 displays a negative scan pulse SP to be used to select a display line to be written (or erased) of pixel data in synchronization with each pixel data pulse group DP. As shown in FIG. 6, the row electrodes Y _{1 to} Y _n are sequentially and alternatively applied. Here, in the discharge cells belonging to the row electrode Y to which the scan pulse SP is applied, an address discharge is selectively generated according to the pulse voltage of the pixel data pulse, and wall charges are formed (or erased). . As a result, each discharge cell is set to one of a state in which wall charges exist (lighting mode) and a state in which no wall charges exist (light-off mode).

In the sustain period I, X row electrode driver 30 and the Y-row electrode driver 400 repeats the number of times corresponding to the luminance weight of each subfield, the sustain pulses IP _X and IP _Y as shown in FIG. 6 the row electrodes X ₁ ~ X _n and each of the row electrodes Y _{1 to} Y _n are applied. At this time, in response to the application of the sustain pulse, only the discharge cells set in the lighting mode are repeatedly subjected to the sustain discharge, and the light emission state associated with the discharge is maintained.

The operation of generating the reset pulse RP _Y , the scan pulse SP, and the sustain pulse IP _Y by the Y row electrode driver 400 will be described below.

  FIG. 7 is a diagram showing a part of the internal configuration of the Y row electrode driver 400.

As shown in FIG. 7, the Y row electrode driver 400 includes a sustain driver SUD, a reset driver RSD, an offset driver OFD, a switching element S15, a phase difference pulse output control unit TC, and scan drivers SCD _{1 to} SCD _n .

Sustain driver SUD sends this by generating the sustain pulse IP _Y on the connection line CL1. The reset driver RSD generates a reset pulse and sends it to the connection line CL2. The offset driver OFD applies a negative offset potential corresponding to the negative peak potential portion in the scan pulse SP to the connection line CL2. When the switching element S15 is set to an on state in accordance with the switching signal SW15 supplied from the drive control circuit 500, the connection lines CL1 and CL2 are electrically connected to each other.

The scan drivers SCD _{1 to} SCD _n are provided in association with the row electrodes Y _{1 to} Y _n of the PDP 10, respectively. Each of the scan drivers SCD generates the scan pulse SP using the negative offset potential generated by the offset driver OFD, and sends it to the row electrode Y.

Each of the scan drivers SCD _{1 to} SCD _n plays a role of relaying and supplying the sustain pulse IP _Y generated by the sustain driver SUD to the row electrode Y. Further, each of the scan drivers SCD _{1 to} SCD _n generates a reset pulse RP _Y with an increased peak potential of the reset pulse generated by the reset driver RSD, and sends this to the corresponding row electrode Y. It also has functions.

That is, the scan drivers SCD _{1 to} SCD _n function as display drivers that send various drive pulses (reset pulse RP _Y , scan pulse SP, sustain pulse IP _Y ) to drive the display of the PDP 10 to the PDP 10.

As shown in FIG. 7, the sustain driver SUD includes a power supply B1, switching elements S11 to S14, coils L3 and L4, diodes D3 and D4, and a capacitor C2. One end of the capacitor C2 is set to a PDP ground potential as a ground potential of the PDP 10. Switching elements S11 to S14 made of bipolar transistors are set to one of an on state and an off state in accordance with switching signals SW11 to SW14 supplied from drive control circuit 500, respectively. At this time, when the switching element S11 is set to the on state, the potential generated at the other end of the capacitor C2 is applied to the connection line CL1 via the coil L3 and the diode D3. When the switching element S12 is set to the on state, the potential on the connection line CL1 is applied to the other end of the capacitor C2 through the coil L4 and the diode D4. At this time, the capacitor C2 is charged by the potential on the connection line CL1. When the switching element S13 is set to the on state, the positive power supply potential _VSUS generated by the power supply B1 is applied to the connection line CL1. When the switching element S14 is set to the on state, the connection line CL1 is set to the PDP ground potential.

The reset driver RSD includes a power supply B2, switching elements S17 and S18, resistors R1 and R2, and a diode D7. Switching elements S17 and S18 made of bipolar transistors are set to one of an on state and an off state in accordance with switching signals SW17 and SW18 supplied from drive control circuit 500, respectively. At this time, when the switching element S17 is set to the ON state, the positive power supply potential _Vrst generated by the power supply B2 is applied to the connection line CL2 via the resistor R1. On the other hand, when the switching element S18 is set to the on state, the connection line CL2 is grounded via the resistor R2 and the diode D7.

The offset driver OFD includes a power supply B3, a switching element S19, and a resistor R3. The switching element S19 is set to one of an on state and an off state according to the switching signal SW19 supplied from the drive control circuit 500. Here, when the switching element S19 is set to the ON state, the negative power source potential (−V _ofs ) generated by the power source B3 is set as an offset potential (−V _ofs ) on the connection line CL2 via the resistor R3. Applied.

The phase difference pulse output control unit TC switches the switching signals SW21 _{1 to} SW21 _n supplied from the drive control circuit 500 while the time difference output enable signal OC1 supplied from the drive control circuit 500 is at the logic level 0. signal GS21 ₁ ~GS21 _n scan drivers SCD ₁ ~SCD _n supplied to each as. On the other hand, during the period in which the time difference output enable signal OC1 is at the logic level 1, the phase difference pulse output control unit TC scans the simultaneous pulse signal OC2 supplied from the drive control circuit 500 as the switching signals SW21 _{1 to} SW21 _n. The drivers SCD _{1 to} SCD _n are supplied to each. Furthermore, during the period time difference output enable signal OC1 is logic level 1, the scan driver phase difference pulse output control unit TC is a signal obtained by inverting the logic level of the simultaneous pulse signal OC2, as a switching signal SW22 ₁ ~SW22 _n SCD _{1 to} SCD _n are supplied to each. In this case, when sending the switching signal SW21 ₁ ~SW21 _n and SW22 ₁ ~SW22 _n respectively corresponding to simultaneously pulse signal OC2 to the scan driver SCD ₁ ~SCD _n each phase difference pulse output control unit TC, a scan driver SCD Each of the semiconductor chips in which the semiconductor chip is constructed has a different transmission timing for each of a plurality of semiconductors.

For example, as shown in FIG. 8, when n scan drivers SCD _{1 to} SCD _n are mounted on three semiconductor chips IC1 to IC3, the phase difference pulse output control unit TC has three types as shown in FIG. The switching signals SW21 and SW22 are sent to each of the scan drivers SCD _{1 to} SCD _n at the timing shown in FIG.

That is, the phase difference pulse output control unit TC uses the signals obtained by delaying the simultaneous pulse signal OC2 by a predetermined first time T1 as shown in FIG. 9 as the switching signals GS21 _{1 to} GS21 _{(n / 3)} , and the semiconductor chip IC1. Are supplied to each of the scan drivers SCD _{1 to} SCD _{(n / 3)} constructed. Furthermore, the phase difference pulse output control unit TC uses the signals obtained by inverting the logic level of the signal obtained by delaying the simultaneous pulse signal OC2 by the first time T1 as the switching signals GS22 _{1 to} GS22 _{(n / 3)} , and the semiconductor chip IC1. Are supplied to each of the scan drivers SCD _{1 to} SCD _{(n / 3)} constructed.

Further, the phase difference pulse output control unit TC switches a signal obtained by delaying the simultaneous pulse signal OC2 by a predetermined second time T2 larger than the first time T1, as shown in FIG. 9, to the switching signal GS21 _{(1 + n / 3) to} GS21 _{(2n / 3)} are supplied to each of the scan drivers SCD _{(1 + n / 3) to} SCD _{(2n / 3)} built in the semiconductor chip IC2. Further, the phase difference pulse output control unit TC converts the signal obtained by inverting the logic level of the signal obtained by delaying the simultaneous pulse signal OC2 by the second time T2 to the switching signals GS22 _{(1 + n / 3) to} GS22 _{(2n / 3 ). )} Is supplied to each of the scan drivers SCD _{(1 + n / 3) to} SCD _{(2n / 3)} built in the semiconductor chip IC2.

Further, the phase difference pulse output control unit TC switches a signal obtained by delaying the simultaneous pulse signal OC2 by a third time T3 larger than the second time T2 as shown in FIG. 9 to the switching signal GS21 _{(1 + 2n / 3 ) To} GS21 _n are supplied to the scan drivers SCD _{(1 + 2n / 3) to} SCD _n built in the semiconductor chip IC3. Further, the phase difference pulse output control unit TC uses the signals obtained by inverting the logic level of the signal obtained by delaying the simultaneous pulse signal OC2 by the third time T3 as the switching signals GS22 _{(1 + 2n / 3) to} GS22 _n as a semiconductor. This is supplied to each of the scan drivers SCD _{(1 + 2n / 3) to} SCD _n built in the chip IC3.

The scan drivers SCD _{1 to} SCD _n have the same configuration, and each includes a power supply B 4 that generates a DC power supply potential V _h and switching elements S 21 and S 22 as bipolar transistors. The switching elements S21 and S22 are set to one of an on state and an off state, respectively, according to the switching signals GS21 and GS22 supplied from the phase difference pulse output control unit TC. At this time, the switching element S21 is set to ON state, the potential power B4 is obtained by adding the potential of the connection line CL2 to a DC power supply potential V _h that occurred, the row electrode Y through the switching elements S21 Applied. On the other hand, when the switching element S22 is set to the on state, the potential on the connection line CL2 is applied to the row electrode Y through the switching element S22. For example, the switching element S21 of the scan driver SCD ₁ is turned off when the switching signal GS21 ₁ supplied from the phase difference pulse output control unit TC has a potential corresponding to the logic level 0. On the other hand, if it has a potential switching signal GS21 ₁ is corresponding to the logical level 1, the switching element S21 in the scan driver SCD ₁ are turned on, the row potentials obtained by adding the voltage on the power source potential V _h to the connection line CL2 applied to the electrodes Y _1. The switching element S22 of the scan driver SCD ₁ is turned off when the switching signal GS22 ₁ supplied from the phase difference pulse output control unit TC has a potential corresponding to the logic level 0. On the other hand, if it has a potential switching signal GS22 ₁ is corresponding to the logical level 1, the switching element S22 of the scan driver SCD ₁ is turned on, applying a potential on a connection line CL2 to the row electrodes Y _1.

The drive control circuit 500 supplies the switching signals SW11 to SW22, the time difference output enable signal OC1, and the simultaneous pulse signal OC2 to the Y-row electrode driver 400, thereby controlling each of the switching elements S11 to S22 as shown in FIG. . In FIG 10, an excerpt only SCD ₁ of the scan driver SCD ₁ ~SCD _n are independently provided for each respective row electrodes Y ₁ to Y _n, indicates its operation.

In FIG. 10, during the sustain period I, the drive control circuit 500 fixes the switching element S15 to the ON state, the logic level 0 time difference output enable signal OC1, the logic level 0 switching signals SW21 _{1 to} SW21 _n and the logic level. supplying a first SW22 ₁ ~SW22 _n to the phase difference pulse output control unit TC. At this time, in accordance with the time difference output enable signal OC1 logic level 0, the phase difference pulse output control unit TC is a switching signal SW21 ₁ ~SW21 _n logic level 0, such as the as the respective GS21 ₁ ~GS21 _n, the scan driver SCD ₁ supplies the switching element S21 in ～SCD _n each. Further, during this time, the phase difference pulse output control unit TC supplies the switching signals SW22 _{1 to} SW22 _n of the logic level 1 as described above as GS22 _{1 to} GS22 _{n to} the switching elements S22 of the scan drivers SCD _{1 to} SCD _n, respectively. To do. With this control operation, all of the switching elements S21 and S22 of the scan drivers SCD _{1 to} SCD _n are set to the ON state.

Further, in the sustain period I, the drive control circuit 500 performs on / off control of the switching elements S11 to S14 of the sustain driver SUD according to the switching sequence SSY as shown in FIG. According to the switching sequence SSY, firstly only S11 in the switching elements S11~S14 is turned on, a current coil L3 caused by the charges accumulated in the capacitor C2, the diode D3, the switching element S15 and the scan drivers SCD ₁ ~ flowing to the row electrodes Y ₁ to Y _n through the respective switching element S22 of SCD _n each. As a result, the potential of each row electrode Y gradually rises as shown in FIG. Next, the drive control circuit 500 sets S13 together with the switching element S11 to an on state. Therefore, the power supply potential V _SUS power B1 occurs is applied to the row electrodes Y ₁ to Y _n through the switching element S15 and the scan driver SCD ₁ ~SCD _n each switching element S22. Thereby, the potential on each row electrode Y is fixed to the power supply potential _{VSUS as} shown in FIG. Then, the drive control circuit 500 switches only S12 of the switching elements S11 to S14 to the on state. Therefore, the current accompanying the charge stored in the load capacitance C ₀ between the row electrodes X and Y is passed through the row electrodes Y, the switching elements S22 and S15 of each of the scan drivers SCD _{1 to} SCD _n , the coil L4, and the diode D4. It flows into the capacitor C2. As a result, the potential on each row electrode Y gradually decreases as shown in FIG. By the operation according to the switching sequence SSY, the sustain driver SUD generates a sustain pulse IP _Y having a waveform as shown in FIG. 10, and this is generated via the switching element S15 and the switching element S22 of each scan driver SCD. supplies respectively to the Y ₁ ~Y _n. In the sustain period I, the sustain driver SUD repeatedly executes the operation according to the switching sequence SSY for the number of times corresponding to the luminance weight of the subfield, so that the number of times corresponds to the luminance weight of the subfield. The sustain pulse IP _Y is repeatedly applied to each row electrode Y.

In the address period W shown in FIG. 10, the drive control circuit 500 switches the switching element S15 from the on state to the off state, and fixes the switching element S19 of the offset driver OFD to the on state. Further, the drive control circuit 500 outputs a time difference output enable signal OC1 having a logic level of 0 in the section excluding the head and tail in the address period W and a logic level of 1 in the head and tail. Supply to TC. Further, during this period, the drive control circuit 500 makes a transition from the logic level 0 to the logic level 1 at the head portion in the address period W, and changes from the logic level 1 to the logic level 0 at the tail portion. Is supplied to the phase difference pulse output control unit TC. Further, in the section excluding the head part and the tail part in the address period W, the drive control circuit 500 sequentially switches each of the scan drivers SCD _{1 to} SCD _n as follows: switching signals SW21 _{1 to} SW21 to be controlled. _n and SW22 ₁ ~SW22 _n and supplies the phase difference pulse output control unit TC. That is, while setting the switching element S21 of each of the scan drivers SCD _{1 to} SCD _n to the ON state and S22 to the OFF state, the S21 is turned OFF and the S22 to the ON state for each scan driver SCD sequentially for each predetermined short period. a switching signal SW21 ₁ ~SW21 _n and SW22 ₁ ~SW22 _n to be switched is to supply to the phase difference pulse output control unit TC.

Therefore, within the address period W, the phase difference pulse output control unit TC outputs the simultaneous pulse signal OC2 for a predetermined period (T1, T2 or T2) during the period (leading part and trailing part) where the time difference output enable signal OC1 is at logic level 1. Signals delayed by T3) are supplied as switching signals GS21 _{1 to} GS21 _n to the scan drivers SCD _{1 to} SCD _n, respectively. Further, during this time, the phase difference pulse output control unit TC is scanning a signal obtained by inverting the logic level of simultaneous pulse signal OC2 predetermined period (T1, T2 or T3) only signal delayed as a switching signal GS22 ₁ ~GS22 _n The drivers SCD _{1 to} SCD _n are supplied to each.

On the other hand, in the period in which the time difference output enable signal OC1 is at the logic level 0 within the address period W, the phase difference pulse output control unit TC converts the switching signals SW21 _{1 to} SW21 _n and SW22 _{1 to} SW22 _n to the switching signal GS21, respectively. _{1 ~GS21 n} and GS22 ₁ ~GS22 _n scan drivers SCD ₁ ~SCD _n supplied to each as.

According to such switching control, at the beginning of the address period W, first, the switching elements S21 of each of the scan drivers SCD _{1 to} SCD _n are turned on and S22 is turned off. As a result, a potential obtained by adding the negative offset potential (−V _ofs ) applied to the connection line CL2 via the switching element S19 and the resistor R3 and the positive power source potential V _h generated by the power source B4 ( A base pulse BP as shown in FIG. 10 having a positive peak potential of V _h −V _ofs ) is applied to the row electrode Y via the switching element S21. Next, in the middle part of the address period W, the switching elements S21 and S22 of one SCD in each of the scan drivers SCD _{1 to} SCD _n are switched to the off state and the on state for a predetermined short period, respectively. Thus, the negative offset potential (−V _ofs ) is applied to the row electrode Y via the switching element S19, the resistor R3, and the switching element S22. That is, when the row electrode Y transitions from the potential (V _h −V _ofs ) state to the negative offset potential (−V _ofs ) state, the negative scan pulse SP as shown in FIG. 10 is generated. .

In the reset period R shown in FIG. 10, the drive control circuit 500 switches the switching element S15 from the on state to the off state, and fixes the switching element S19 to the off state. Further, the drive control circuit 500 supplies the time difference output enable signal OC1 of logic level 1 to the phase difference pulse output control unit TC during the reset period R. In the reset period R, first, the drive control circuit 500 supplies the simultaneous pulse signal OC2 that maintains the logic level 1 for a predetermined period to the phase difference pulse output control unit TC. Phase difference pulse output control unit TC supplies such simultaneous pulse signal OC2 predetermined period (T1, T2 or T3) only signal delayed in the scan driver SCD ₁ ~SCD _n each as a switching signal GS21 ₁ ~GS21 _n. Further, during this time, the phase difference pulse output control unit TC is scanning a signal obtained by inverting the logic level of simultaneous pulse signal OC2 predetermined period (T1, T2 or T3) only signal delayed as a switching signal GS22 ₁ ~GS22 _n The drivers SCD _{1 to} SCD _n are supplied to each. Thereby, all the switching elements S21 of each of the scan drivers SCD _{1 to} SCD _n are set to the on state. Then, the voltage is applied to the row electrode Y through each of them, and the potential on the row electrode Y transits from 0 volt to the potential V _{h as shown} in FIG.

Thereafter, the drive control circuit 500 switches the switching element S17 of the reset driver RSD from the off state to the on state. At this time, the power supply potential _Vrst generated by the power supply B2 is applied to the connection line CL2 via the switching element S17 and the resistor R2. As a result, a potential (V _rst + V _h ) obtained by adding the power source potential V _rst to the power source potential V _h is applied to the row electrode Y via the switching element S 21, and the potential on the row electrode Y becomes the potential V V as time passes. It gradually rises from the state of _h toward the power supply potential (V _rst + V _h ).

When the potential on the row electrode Y reaches the potential (V _rst + V _h ), the drive control circuit 500 switches the simultaneous pulse signal OC2 from the logic level 1 to the logic level 0. Thus, the logic level 0 switching signal GS21 and the logic level 1 switching signal GS22 are supplied to all the scan drivers SCD _{1 to} SCD _n . Therefore, the switching element S21 in the scan drivers SCD _{1 to} SCD _n is set to the off state and the switching element S22 is set to the on state. Further, the drive control circuit 500 switches the switching element S17 to the OFF state and sets the switching elements S13 and S15 to the ON state for a predetermined short period as shown in FIG. As a result, the power supply potential _VSUS generated by the power supply B1 is applied to the row electrode Y via the switching elements S13, S15, and S22, so that the potential on the row electrode Y is equal to the power supply potential _VSUS as shown in FIG. Set to state. Thereafter, the drive control circuit 500 switches the switching element S18 to the on state. Thereby, since the connection line CL2 is grounded via the resistor R2 and the diode D7, the potential on the row electrode Y gradually decreases according to the time constant due to the resistor R2 and the load capacitance Co as shown in FIG.

By a series of switching control such as described above, the reset pulse RP _Y is generated with such waveform shown in FIG. 10, which is to be respectively applied to the row electrodes Y ₁ to Y _n.

Here, as shown in FIG. 10, a reset pulse RP when the rising edge in _Y T _U1, and fall time T _D1 of the edge, depending on the on and off switching timing of the switching elements S21 and S22 of the scan driver SCD Yes. As shown in FIG. 10, the rising edge time T _U2 and the falling edge time T _D2 of the base pulse BP within the address period W also depend on the on / off switching timing of the switching elements S21 and S22 of the scan driver SCD. is doing.

At this time, the phase difference pulse output control unit TC determines the edge timings of the switching signals GS21 _{1 to} GS21 _n and GS22 _{1 to} GS22 _n for controlling on / off of the switching elements 21 and S22 of the scan drivers SCD _{1 to} SCD _n, respectively. As shown in FIG. 9, the scan driver SCD is made different for each of the semiconductor chips IC1 to IC3.

That is, for the scan drivers SCD _{1 to} SCD _{(n / 3) of} the semiconductor chip IC1, switching signals GS21 _{1 to} GS21 obtained by delaying the simultaneous pulse signal OC2 by the first time T1 as shown in FIG. Supply as _{(n / 3)} . For the scan drivers SCD _{(1 + n / 3) to} SCD _{(2n / 3) of} the semiconductor chip IC2, as shown in FIG. 11, the simultaneous pulse signal OC2 is set to a second time greater than the first time T1. The signals delayed by time T2 are supplied as switching signals GS21 _{(1 + n / 3) to} GS21 _{(2n / 3)} . For the scan drivers SCD _{(1 + 2n / 3) to} SCD _{n of} the semiconductor chip IC3, as shown in FIG. 11, the simultaneous pulse signal OC2 is delayed by a third time T3 larger than the second time T2. These are supplied as switching signals GS21 _{(1 + 2n / 3) to} GS21 _n .

Therefore, as shown in FIG. 11, the reset pulse RP _Y and time T _D of the time T _U and the falling edge of the rising edge of the base pulse BP each of which is applied to the row electrodes Y ₁ ~Y (n _{/ 3)} And those applied to the row electrodes Y _{(1 + 2/3) to} Y _{( 2n / 3)} and those applied to the row electrodes Y _{(1 + 2n / 3) to} Yn ₎ , respectively. Will be different.

Therefore, the timing of the discharge generated in the discharge cell by the application of the reset pulse RP _Y or the base pulse BP is the row electrode group to which the discharge cell belongs, that is, the row electrodes Y _{1 to} Y _{(n / 3)} and the row electrode. and _{Y (1 + n / 3)} ~Y (2n / 3), consisting respectively different between the row electrodes _{Y (1 + 2n / 3)} ~Y n. As a result, reset discharges for initializing all the discharge cells are generated in a time-dispersed manner, so that the amount of charge / discharge current that flows from each discharge cell into the PDP 10 simultaneously with the reset discharge is reduced. As a result, noise noise generated from the housing of the PDP 10 can be suppressed.

In the above embodiments, so as to vary the reset pulse RP _Y and the base pulse BP each phase of the time T _D of the time T _U and falling edges of the rising edges together, for each semiconductor chip (IC1 to IC3) However, either one of the phases may be different.

For example, as shown in FIG. 12, the phase difference pulse output control unit TC performs the phase of the falling time T _D among the rising edge time T _U and the falling edge time T _D of the reset pulse RP _Y and the base pulse BP. However, the scan drivers SCD may be controlled so as to be different for each of the semiconductor chips IC1 to IC3.

13, the reset pulse RP _Y and the base pulse BP phase difference pulse output control unit TC employed when falling varying only the phase of the time T _D of the edge for each semiconductor chip IC in each, as shown in FIG. 12 It is a figure which shows an example of a hardware constitutions.

  As shown in FIG. 13, the phase difference pulse output control unit TC includes delay circuits DC1 and DC2, selectors SEL1 to SEL6, and an inverter IV.

  The delay circuit DC1 is a first signal obtained by delaying only a so-called falling edge timing by a first time T1, as shown in FIG. 12, at the time of transition from the logic level 0 to 1 in the simultaneous pulse signal OC2 supplied from the drive control circuit 500. The delayed pulse signal is supplied to the selector SEL1 through the delayed output line DL1. The delay circuit DC1 supplies a second delayed pulse signal obtained by delaying only the falling edge timing of the simultaneous pulse signal OC2 by the second time T2 as shown in FIG. 12 to the selector SEL2 via the delay output line DL2. To do. Further, the delay circuit DC1 supplies the selector SEL3 via the delay output line DL3 with the third delayed pulse signal obtained by delaying only the falling edge timing in the simultaneous pulse signal OC2 by the third time T3 as shown in FIG. To do.

While the time difference output enable signal OC1 is at the logic level 0, the selector SEL1 switches the switching signals SW21 _{1 to} SW21 _{(n / 3)} supplied from the drive control circuit 500 to the switching signals GS21 _{1 to} GS21 _{(n / 3), respectively.} Are supplied to each of the scan drivers SCD _{1 to} SCD _{(n / 3)} built in the semiconductor chip IC1. In addition, while the time difference output enable signal OC1 is at the logic level 1, the selector SEL1 receives the first delay pulse signal supplied via the delay output line DL1 of the delay circuit DC1 as the switching signals GS21 _{1 to} GS21 _{(n / As 3)} , the scan drivers SCD _{1 to} SCD _{(n / 3)} provided in the semiconductor chip IC1 are supplied to each.

While the time difference output enable signal OC1 is at the logic level 0, the selector SEL2 uses the switching signals SW21 _{(1 + n / 3) to} SW21 _{(2n / 3)} supplied from the drive control circuit 500 as the switching signal GS21 _{(1 + n / 3) to} GS21 _{(2n / 3)} are supplied to the scan drivers SCD _{(1 + n / 3) to} SCD _{(2n / 3)} built in the semiconductor chip IC2. While the time difference output enable signal OC1 is at the logic level 1, the selector SEL2 outputs the second delay pulse signal supplied via the delay output line DL2 of the delay circuit DC1 to the switching signal GS21 _{(1 + n / 3 ) To} GS21 _{(2n / 3)} are supplied to the scan drivers SCD _{(1 + n / 3) to} SCD _{(2n / 3)} constructed in the semiconductor chip IC2.

While the time difference output enable signal OC1 is at the logic level 0, the selector SEL3 uses the switching signals SW21 _{(1 + 2n / 3) to} SW21 _n supplied from the drive control circuit 500 as the switching signals GS21 _{(1 + 2n / 3). ) To} GS21 _n are supplied to the scan drivers SCD _{(1 + 2n / 3) to} SCD _n built in the semiconductor chip IC3. While the time difference output enable signal OC1 is at the logic level 1, the selector SEL3 receives the third delay pulse signal supplied via the delay output line DL3 of the delay circuit DC1 as the switching signal GS21 _{(1 + 2n / 3 ) To} GS21 _n are supplied to the scan drivers SCD _{(1 + 2n / 3) to} SCD _n built in the semiconductor chip IC3.

  The inverter IV supplies an inverted simultaneous pulse signal OC2V obtained by inverting the logic level of the simultaneous pulse signal OC2 supplied from the drive control circuit 500 to the delay circuit DC2.

  The delay circuit DC2 delays the first delayed inverted pulse signal obtained by delaying only the so-called falling edge timing by the first time T1, as shown in FIG. 12, at the time of transition from the logic level 0 to 1 in the inverted simultaneous pulse signal OC2V. The signal is supplied to the selector SEL4 via the output line DL1. Further, the delay circuit DC2 selects the second delayed inverted pulse signal obtained by delaying only the timing of the falling edge in the inverted simultaneous pulse signal OC2V by the second time T2 as shown in FIG. 12 via the delay output line DL2 and the selector SEL5. To supply. Further, the delay circuit DC2 receives the third delayed inverted pulse signal obtained by delaying only the falling edge timing in the inverted simultaneous pulse signal OC2V by the third time T3 as shown in FIG. 12 via the delay output line DL3. To supply.

While the time difference output enable signal OC1 is at logic level 0, the selector SEL4 uses the switching signals SW22 _{1 to} SW22 _{(n / 3)} supplied from the drive control circuit 500 as the switching signals GS22 _{1 to} GS22 _{(n / 3), respectively.} Are supplied to each of the scan drivers SCD _{1 to} SCD _{(n / 3)} built in the semiconductor chip IC1. In addition, while the time difference output enable signal OC1 is at the logic level 1, the selector SEL4 converts the first delay inversion pulse signal supplied via the delay output line DL1 of the delay circuit DC2 into the switching signals GS22 _{1 to} GS22 _{(n / 3)} is supplied to each of the scan drivers SCD _{1 to} SCD _{(n / 3)} built in the semiconductor chip IC1.

While the time difference output enable signal OC1 is at the logic level 0, the selector SEL5 uses the switching signals SW22 _{(1 + n / 3) to} SW22 _{(2n / 3)} supplied from the drive control circuit 500 as the switching signal GS22 _{(1 + n / 3) to} GS22 _{(2n / 3)} are supplied to the scan drivers SCD _{(1 + n / 3) to} SCD _{(2n / 3)} built in the semiconductor chip IC2. While the time difference output enable signal OC1 is at the logic level 1, the selector SEL5 receives the second delayed inversion pulse signal supplied via the delay output line DL2 of the delay circuit DC2 as the switching signal GS22 _{(1 + n / 3) to} GS22 _{(2n / 3)} are supplied to each of the scan drivers SCD _{(1 + n / 3) to} SCD _{(2n / 3)} built in the semiconductor chip IC2.

While the time difference output enable signal OC1 is at the logic level 0, the selector SEL6 uses the switching signals SW22 _{(1 + 2n / 3) to} SW22 _n supplied from the drive control circuit 500 as the switching signals GS22 _{(1 + 2n / 3). ) To} GS22 _n are supplied to the scan drivers SCD _{(1 + 2n / 3) to} SCD _n constructed in the semiconductor chip IC3. While the time difference output enable signal OC1 is at the logic level 1, the selector SEL6 receives the third delayed inversion pulse signal supplied via the delay output line DL3 of the delay circuit DC2 as the switching signal GS22 _{(1 + 2n / 3) to} GS22 _n are supplied to the scan drivers SCD _{(1 + 2n / 3) to} SCD _n constructed in the semiconductor chip IC3.

  The delay circuits DC1 and DC2 have the same circuit configuration, and each includes resistors R11 to R16, a diode D10, and capacitors C11 to C13 as shown in FIG.

  That is, each of the delay circuits DC1 and DC2 includes a first integration circuit to a third integration circuit as follows. The first integrating circuit includes a resistor R11 connected between the input line INL and the delay output line DL1, and a capacitor C11 having one end connected to the delay output line DL1 and the other end grounded. Become. The second integrating circuit includes a resistor R12 connected between the input line INL and the delay output line DL2, and a capacitor C12 having one end connected to the delay output line DL2 and the other end grounded. Become. The third integrating circuit includes a resistor R13 connected between the input line INL and the delay output line DL3, and a capacitor C13 having one end connected to the delay output line DL3 and the other end grounded. It consists of.

  Further, each of the delay circuits DC1 and DC2 includes a diode D10 whose anode terminal is connected to the input line INL, a resistor R14 connected between the cathode terminal of the diode D10 and the delay output line DL1, and a delay output. A resistor R15 connected between the lines DL1 and DL2 and a resistor R16 connected between the delay output lines DL2 and DL3 are provided.

  Next, the operation by the delay circuits DC1 and DC2 will be described.

  When the simultaneous pulse signal OC2 supplied via the input line INL transitions from the logic level 1 state to the logic level 0, the potential at the anode end of the diode D10 becomes low, so that the capacitors C11, C12, and C13 are discharged. To start. At this time, the discharge current from the capacitor C13 flows into the input line INL via the resistor R16, the resistor R15, the resistor R14, and the diode D10. Further, the discharge current from the capacitor C12 flows into the input line INL via the resistor R15, the resistor R14, and the diode D10. Further, the discharge current from the capacitor C11 flows into the input line INL via the resistor R14 and the diode D10. Therefore, while the discharge current flows, the potentials of the delay output lines DL1 to DL3 are maintained at a high potential corresponding to the logic level 1. That is, while the discharge current is flowing, even if the simultaneous pulse signal OC2 transitions from the logic level 1 state to the logic level 0, the potential on each of the delay output lines DL1 to DL3 corresponds to the logic level 1. Maintained at a high potential. Here, the length of the period during which the discharge current flows from the capacitors C11 to C13 increases as the resistance value existing in the current path through which the discharge current flows increases.

Therefore, the time (T1) and delay from when the simultaneous pulse signal OC2 supplied via the input line INL changes from the logic level 1 state to the logic level 0 until the state is reflected on the delay output line DL1. Each of the time (T2) until reflected on the output line DL2 and the time (T3) until reflected on the delayed output line DL3 are
T1 <T2 <T3
It becomes.

Therefore, as shown in FIG. 12, the timing at which each of the switching signals GS21 _{(1 + 2n / 3) to} GS21 _n corresponding to the signal on the delay output line DL3 transitions from the logic level 1 to 0 is on the delay output line DL2. The switching signals GS21 _{(1 + n / 3) to} GS _{(2n / 3)} corresponding to the signals are later than the timing of transition from the logic level 1 to 0. The timing at which each of the switching signals GS21 _{(1 + n / 3) to} GS _{(2n / 3)} corresponding to the signal on the delay output line DL2 transits from the logic level 1 to 0 is the signal on the delay output line DL1. The corresponding switching signals GS21 _{1 to} GS21 _{(n / 3)} are later than the timing of transition from the logic level 1 to 0.

  On the other hand, when the simultaneous pulse signal OC2 supplied via the input line INL transitions from the logic level 0 state to 1, the potential at the anode end of the diode D10 becomes a high potential. At this time, no discharge is generated by the capacitors C11 to C13, and no current flows through the path of the diode D10 and the resistors R13 to R14. Therefore, during this time, the simultaneous pulse signal OC2 supplied via the input line INL has a slow potential transition when transitioning from the logic level 0 state to 1, but at the same time, the state thereof is delayed output line DL1. Reflected in each of DL3.

Therefore, as shown in FIG. 12, the switching signal GS21 _{(1 + 2n} / 3) corresponding to the signal on the delay output line DL3 ~GS21 _n, the switching signal GS21 corresponding to the signal on the delay output line DL2 _{(1 + n / 3) to} GS21 _{(2n / 3)} and the timing at which the switching signals GS21 _{1 to} GS21 _{(n / 3)} corresponding to the signals on the delay output line DL1 transition from the logic level 0 to 1 are substantially the same.

According to the configuration shown in FIG. 13, only the phase of the falling edge portion (time point T _D ) in the reset pulse RP _Y and the base pulse BP can be made different for each semiconductor chip IC. This is effective when discharges must be generated all at once.

Incidentally, in the case of different reset pulse RP _Y and both phases of the time T _D of the time T _U and the falling edge of the rising edge of the base pulse BP each for each semiconductor chip includes a diode D10 shown in FIG. 13 parallel As shown in FIG. 14, a resistor R10 is connected. 14 is the same as that shown in FIG. 13 except for the point that the resistor R10 is added. At this time, the resistance value of the resistor R10, the amount of phase shift is determined for the time T _U of the reset pulse RP _Y and the rising edge of the base pulse BP respectively.

  Instead of the diode D10 shown in FIG. 13, a switching element S100 made of a p-channel MOS (metal oxide semiconductor) transistor as shown in FIG. 15 may be adopted. In FIG. 15, other configurations are the same as those shown in FIG. 13 except that a switching element S100 is employed instead of the diode D10.

Here, when the configuration shown in FIG. 15 is adopted as the delay circuits DC1 and DC2, the drive control circuit 500 performs switching indicating whether or not to perform a delay operation together with the time difference output enable signal OC1 and the simultaneous pulse signal OC2. The signal QS10 is supplied to each of the delay circuits DC1 and DC2. The switching element S100 of the delay circuits DC1 and DC2 is turned on when a logic level 0 switching signal QS10 indicating that a delay operation is performed is supplied, and electrically connects the input line INL and one end of the resistor R14. Connecting. As a result, the capacitors C11 to C13 start a discharging operation. At this time, a signal obtained by delaying the simultaneous pulse signal OC2 by different periods (T1, T2, T3) while the discharge current is discharged from each capacitor is sent to each of the delay output lines DL1 to DL3. Therefore, as shown in FIG. 11, the reset pulse RP _Y and the base pulse BP each time point T _U of the rising edges in phase, or the falling time T _D of the edge phase, the row electrodes Y ₁ ~Y (n _{/ 3 a),} the row electrodes _{Y (1 + n / 3)} ~Y and _{(2n / 3),} the row electrodes _{Y (1 + 2n / 3)} ~Y n and displaced respectively in.

On the other hand, when the switching signal QS10 having the logic level 1 indicating that the delay operation is not performed is supplied, the switching element S100 is turned off, and the discharging operation in each of the capacitors C11 to C13 does not occur. Thus, this time, the reset pulse RP _Y and the base pulse BP time T _U of the rising edge in each phase or fall time T _D of the edge phase is the same in all the row electrodes Y ₁ to Y _n.

As described above, according to the configuration as shown in FIG. 15, only the arbitrary edge portions of the reset pulse RP _Y and the base pulse BP are shown in FIG. It is possible to cause a phase shift as shown.

In the above embodiment, the operation has been described by taking as an example the case where all the scan drivers SCD _{1 to} SCD _n are mounted on the three semiconductor chips IC _{1 to} IC 3, but the number of semiconductor chips for which the scan driver is to be constructed is described. Is not limited to three.

  In short, when each of the scan drivers provided by the number (n) of the row electrodes Y of the PDP is mounted on K semiconductor chips (K is an integer equal to or less than n), the phase difference pulse output control is performed. The circuit TC controls the on / off of the scan driver at different K timings for each semiconductor chip.

  Further, such K semiconductor chips are grouped into Q (Q is an integer smaller than K) semiconductor chip groups, and the scan driver is controlled to be turned on and off at different timings for each semiconductor chip. May be.

For example, when all the scan drivers SCD _{1 to} SCD _n are mounted on nine semiconductor chips, these are grouped into three semiconductor chip groups ICG 1 to ICG 3. At this time, as shown in FIG. 16, the phase difference pulse output control circuit TC controls on / off of the scan driver at different timings for each of the semiconductor chip groups ICG1 to ICG3.

It is a figure which shows schematic structure of a plasma display apparatus. It is a figure showing the various drive pulses applied to PDP10 shown by FIG. 1, and the production | generation operation | movement of each drive pulse. FIG. 2 is a diagram showing an internal configuration of each of an X row electrode driver 30 and a Y row electrode driver 40 shown in FIG. 1. It is a figure which shows schematic structure of the plasma display apparatus based on this invention. FIG. 5 is a diagram showing an example of a light emission drive sequence when driving a PDP 10 mounted on the plasma display device shown in FIG. 4. FIG. 5 is a diagram showing various drive pulses applied to the PDP 10 in one subfield by the address driver 20, the X row electrode driver 30, and the Y row electrode drive 400 shown in FIG. 3 is a diagram illustrating an example of an internal configuration of a Y row electrode driver 400. FIG. Scan drivers SCD ₁ ~SCD _n is a diagram showing an example of construction of if mounted on three semiconductor chips IC1 to IC3. It is a figure which shows an example of the delay output operation | movement with respect to simultaneous pulse signal OC2 in the phase difference pulse output control part TC. 5 is a diagram illustrating an internal operation of a Y row electrode driver 400. FIG. It is a diagram illustrating an example of a phase difference output of each semiconductor chip in the reset pulse RP _Y and the base pulse BP. It is a diagram showing another example of the phase difference output of each semiconductor chip in the reset pulse RP _Y and the base pulse BP. It is a figure which shows an example of an internal structure of the phase difference pulse output control part TC. It is a figure which shows the modification of the phase difference pulse output control part TC shown by FIG. It is a figure which shows the other modification of the phase difference pulse output control part TC shown by FIG. It is a figure which shows an example of the operation | movement at the time of carrying out on-off control of each scan driver SCD for every semiconductor chip group ICG1-ICG3.

Explanation of symbols

10 PDP
400 Y-row electrode driver SCD Scan driver TC Phase difference pulse output control circuit

Claims (8)

A display driver control method for controlling each of n display drivers that applies a driving pulse for driving a display panel to each of n (n: an integer of 2 or more) electrodes of the display panel,
The display driver is mounted on k (k: an integer less than or equal to n) semiconductor chips,
When the drive pulse is applied to each of the n electrodes simultaneously, the display driver is controlled so that the timing of the falling edge in the drive pulse is different for each semiconductor chip or for each semiconductor chip group. A display driver control method characterized by the above. A display driver control method for controlling each of n display drivers that applies a driving pulse for driving a display panel to each of n (n: an integer of 2 or more) electrodes of the display panel,
The display driver is mounted on k (k: an integer less than or equal to n) semiconductor chips,
When the drive pulse is applied to each of the n electrodes simultaneously, the display driver is controlled so that the timing of the falling edge in the drive pulse is different for each semiconductor chip or for each semiconductor chip group. A display driver control method characterized by the above. When applying the drive pulse to each of the n electrodes simultaneously, the display driver is controlled so that the timing of the rising edge in the drive pulse is also different for each semiconductor chip or for each semiconductor chip group. The display driver control method according to claim 1. A display driver control method for controlling each of n display drivers that applies a driving pulse for driving a display panel to each of n (n: an integer of 2 or more) electrodes of the display panel,
The display driver includes a first power source that generates a first potential corresponding to the peak potential of the drive pulse, and a switching element that applies the first potential to the electrode in response to a control signal. n is an integer less than or equal to n) semiconductor chips,
When applying the drive pulse to each of the n electrodes simultaneously, the switching element is controlled so that the timing of stopping the application of the first potential is different for each semiconductor chip or for each semiconductor chip group. And a display driver control method. A display driver control method for controlling each of n display drivers that applies a driving pulse for driving a display panel to each of n (n: an integer of 2 or more) electrodes of the display panel,
The display driver includes a first power source that generates a first potential corresponding to the peak potential of the drive pulse, and a switching element that applies the first potential to the electrode in response to a control signal. n is an integer less than or equal to n) semiconductor chips,
When the driving pulse is applied to each of the n electrodes all at once, the switching element is controlled so that the timing of starting the application of the first potential differs for each semiconductor chip or for each semiconductor chip group. And a display driver control method. When the driving pulse is applied to each of the n electrodes all at once, the switching element is controlled so that the timing of starting the application of the first potential is also different for each semiconductor chip or for each semiconductor chip group. 5. The display driver control method according to claim 4, wherein: A display panel driving method for driving a display panel in which display cells are formed at intersections between a plurality of row electrode pairs and a plurality of column electrodes arranged to cross the row electrode pairs,
A data pulse corresponding to the luminance level indicated by the input video signal is applied to each of the column electrodes, and a base pulse is applied to each of the row electrodes of each of the row electrode pairs while sequentially applying to each of the one of the row electrodes. Alternatively, an addressing step for setting each of the display cells to one of a lighting mode and a light-off mode by applying a scanning pulse superimposed thereon,
A method of driving a display driver, wherein the timing of the falling edge in the base pulse is made different for each row electrode group composed of a plurality of row electrodes. A display panel driving method for driving a display panel in which display cells are formed at intersections between a plurality of row electrode pairs and a plurality of column electrodes arranged to cross the row electrode pairs,
A reset step of initializing the state of each of the display cells by applying a reset pulse to each one of the row electrodes of each of the row electrode pairs;
A method for driving a display driver, wherein the timing of a falling edge in the reset pulse is made different for each row electrode group composed of a plurality of row electrodes.

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