JP3753249B2 - Display panel drive device - Google Patents

Description

  The present invention relates to a driving device for driving a display panel such as an AC drive type plasma display panel or an electroluminescence display panel.

  Currently, as a wall-mounted TV, a display device using a display panel in which capacitive light emitting elements such as a plasma display panel or an electroluminescence display panel are arranged in a matrix is commercialized.

  FIG. 1 is a diagram showing a schematic configuration of a display device using a plasma display panel as such a display panel.

In FIG. 1, a PDP 10 as a plasma display panel includes row electrodes Y _{1 to} Y _n and X that form a pair of row electrodes corresponding to each row (1st row to nth row) of one screen with a pair of X and Y. _{1 to Xn} . Further, the PDP 10 includes column electrodes Z _{1 to} Z that are orthogonal to the row electrode pairs and correspond to each column (first column to m-th column) of one screen across a dielectric layer and a discharge space (not shown). _m is formed. Note that a discharge cell carrying one pixel is formed at an intersection between one pair of row electrodes (X, Y) and one column electrode Z.

  At this time, each discharge cell has only two states of “light emission” and “non-light emission” depending on whether or not a discharge is generated in the discharge cell. That is, only the luminance corresponding to two gradations, ie, the lowest luminance (non-light emitting state) and the highest luminance (light emitting state) can be expressed.

  Therefore, in order to obtain halftone brightness corresponding to the input video signal, the driving device 100 performs gradation driving using the subfield method for the PDP 10 having such a light emitting element.

  In the subfield method, an input video signal is converted into N-bit pixel data corresponding to each pixel, and a display period of one field is converted into N subfields corresponding to each of the N-bit bit digits. To divide. Each subfield is assigned a number of times of discharge corresponding to the weight of the subfield, and this discharge is selectively caused only in the subfield corresponding to the video signal. At this time, halftone luminance corresponding to the video signal is obtained by the total number of discharges generated in each subfield (within one field display period).

  Note that the selective erasure address method is known as a method of actually driving the PDP using the subfield method.

  FIG. 2 is a diagram showing application timings of various driving pulses applied to the column electrodes and the row electrodes of the PDP 10 within one subfield when the grayscale driving based on the selective erasure address method is performed. is there.

First, the driving device 100 simultaneously applies a negative reset pulse RP _x row electrodes X ₁ to X _n, further a positive reset pulse RP _Y to the row electrodes Y ₁ to Y _n, respectively (simultaneous reset process Rc) .

Depending on the application of these reset pulses RP _x and RP _Y, all the discharge cells in the PDP10 is reset discharge, uniform predetermined amount of wall charge in each discharge cell is formed. Thereby, all the discharge cells are initially set to “light emitting cells”.

Next, the driving device 100 converts the input video signal into, for example, 8-bit pixel data for each pixel. The driving device 100 divides the pixel data for each bit digit to obtain a pixel data bit, and generates a pixel data pulse having a pulse voltage corresponding to the logical level of the pixel data bit. FIG. 2 shows pixel data pulse groups DP _{1 to} DP _n corresponding to each of the first to n-th rows, in which the driving device 100 groups such pixel data pulses every row (m). In this manner, the voltage is sequentially applied to the column electrode Z _1-m . The driving device 100 generates a pixel data pulse of a high voltage when the pixel data bit is, for example, a logical level “1”, and a low voltage (0 volts) when the pixel data bit is a logical level “0”. Further, the driving device 100 generates the scan pulse SP as shown in FIG. 2 at the application timing of each of the pixel data pulse groups DP, and sequentially applies this to the row electrodes Y ₁ to Y _n . (Pixel data writing process Wc). At this time, a discharge (selective erasure discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied. The wall charges remaining in are selectively erased. As a result, the discharge cell initialized to the “light emitting cell” state in the simultaneous reset process Rc transitions to the “non-light emitting cell”. On the other hand, although the scan pulse SP is applied, the selective erasure discharge as described above does not occur in the discharge cells formed to intersect the “row” and “column” to which the low-voltage pixel data pulse is applied. The state initialized in the simultaneous reset process Rc, that is, the state of the “light emitting cell” is maintained.

Next, as shown in FIG. 2, the driving apparatus 100 repeatedly applies a positive sustain pulse IP _X to the row electrodes X _{1 to} X _n, and the sustain pulse IP _X is applied to the row electrodes X _{1 to} X _n . During the period in which no voltage is applied, a positive sustain pulse IP _Y as shown in FIG. 2 is repeatedly applied to the row electrodes Y _{1 to} Y _n (emission sustaining process Ic).

At this time, only the discharge cells in which the wall charges remain, that is, “light emitting cells” are discharged (sustain discharge) each time the sustain pulses IP _X and IP _Y are alternately applied. That is, only the discharge cell set as the “light emitting cell” in the pixel data writing process Wc repeats the light emission associated with the sustain discharge for the number of times corresponding to the weighting of the subfield, and maintains the light emission state. . The number of times these sustain pulses IP _X and IP _Y are applied is a number set in advance according to the weighting for each subfield.

Next, the driving device 100 applies an erasing pulse EP as shown in FIG. 2 to the row electrodes X _{1 to} X _n (erasing step E). As a result, all the discharge cells are simultaneously erased and discharged, and the wall charges remaining in the discharge cells are eliminated.

  By executing a series of operations as described above a plurality of times within one field, an intermediate luminance corresponding to the video signal can be obtained visually.

  However, when a pixel data pulse is applied to a column electrode of a display panel having a capacitive light emitting element such as a plasma display panel or an electroluminescence display panel, charging / discharging is caused by a parasitic capacitance existing between the column electrodes due to a potential difference generated between the column electrodes. Has occurred and reactive power is consumed. Further, when the number of column electrodes is increased for high-definition television image display, the number of pixel data pulses to be applied to the column electrodes is increased accordingly, so that power consumption is also increased.

  Therefore, there is a demand for a driving device that can apply pixel data pulses to a display panel while suppressing power consumption.

  An object of the present invention is to provide a display panel driving apparatus capable of reducing power consumption when pixel data pulses are generated.

The display panel driving apparatus according to claim 1 includes a display panel in which pixel cells corresponding to pixels are formed at intersections of a plurality of row electrodes and a plurality of column electrodes arranged to intersect the row electrodes. A display panel driving device for driving, based on an input video signal, and a power supply circuit that generates a line voltage on the power supply line that periodically changes the voltage by periodically repeating power supply, charge recovery, and discharge A pixel data pulse generating circuit for generating a pixel data pulse on the column electrode by connecting the power supply line and the column electrode for a predetermined period according to pixel data for each pixel, and the power supply circuit comprises: and the small variation width of the line voltage in comparison with the case of the intermittently applied in the case of the pixel data pulse is applied to one of the predetermined period said column electrodes sequentially for each Having a load recovery discharge characteristics.
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The power supply lines cyclically voltage is supplied the line voltage changes and column electrodes of the display panel, by connecting a predetermined period in accordance with a video signal, when applying the pixel data pulses on the column electrodes When the pixel data pulse is applied continuously, the change width of the line voltage is made smaller than when the pixel data pulse is applied discontinuously.

  FIG. 3 is a diagram showing a configuration of a display device provided with a driving device according to the present invention.

In FIG. 3, the PDP 10 as a plasma display panel includes row electrodes Y _{1 to} Y _n and X that form a pair of row electrodes corresponding to each row (first row to n-th row) of one screen with a pair of X and Y. _{1 to Xn} . Further, the PDP 10 includes column electrodes Z _{1 to} Z that are orthogonal to the row electrode pairs and correspond to each column (first column to m-th column) of one screen across a dielectric layer and a discharge space (not shown). _m is formed. Note that a discharge cell carrying one pixel is formed at an intersection between one pair of row electrodes (X, Y) and one column electrode Z.

As shown in FIG. 2, the drive control circuit 50 generates various timing signals for generating the reset pulses RP _X and RP _Y , the scan pulse SP, and the sustain pulses IP _X and IP _Y. This is supplied to each of the electrode drive circuits 30 and 40. The row electrode drive circuit 30 generates a reset pulse RP _X and a sustain pulse IP _X according to the timing signal, and applies them to the row electrodes X _{1 to} X _n of the PDP 10 at the timing as shown in FIG. . On the other hand, the row electrode drive circuit 40 generates each of the reset pulse RP _Y , the scan pulse SP, the sustain pulse IP _Y and the erase pulse EP according to various timing signals supplied from the drive control circuit 50, 2 is applied to the row electrodes Y _{1 to} Y _n of the PDP 10 at the timing as shown in FIG.

Further, the drive control circuit 50 converts the input video signal into, for example, 8-bit pixel data for each pixel, and divides this pixel data for each bit digit to correspond to each of the first to nth rows. What is extracted for each row (m) is supplied to the column electrode drive circuit 20 as pixel data bits DB _{1 to} DB _m . At this time, the drive control circuit 50 generates switching signals SW <b> 1 to SW <b> 4 for generating pixel data pulses corresponding to the pixel data bits DB, and supplies them to the column electrode drive circuit 20.

  FIG. 4 is a diagram showing an internal configuration of the column electrode drive circuit 20.

  As shown in FIG. 4, the column electrode drive circuit 20 includes a power supply circuit 21 and a pixel data pulse generation circuit 22.

  One end of the capacitor C1 in the power supply circuit 21 is grounded to a PDP ground potential Vs as a ground potential of the PDP 10. The switching element S1 is in an OFF state while the switching signal SW1 having the logic level “0” is supplied from the drive control circuit 50. On the other hand, when the logic level of the switching signal SW1 is “1”, the switching signal SW1 is turned on, and the potential generated at the other end of the capacitor C1 is applied to the power supply line 2 via the coil L1 and the diode D1. . As a result, the capacitor C1 starts discharging, and a potential generated by the discharging is applied to the power supply line 2. The switching element S2 is off while the switching signal SW2 having the logic level “0” is supplied from the drive control circuit 50, and is on when the logic level of the switching signal SW2 is “1”. In this state, the potential on the power supply line 2 is applied to the other end of the capacitor C1 through the coil L2 and the diode D2. At this time, the capacitor C1 is charged by the potential on the power supply line 2. The switching element S3 is off while the switching signal SW3 having the logic level “0” is supplied from the drive control circuit 50, and is on when the logic level of the switching signal SW3 is “1”. The power supply potential Va from the DC power supply B1 is applied to the power supply line 2 in the state. The negative terminal of the DC power supply B1 is grounded at the PDP ground potential Vs. The switching element S4 is off while the switching signal SW4 having the logic level “0” is supplied from the drive control circuit 50. On the other hand, the switching element S4 is on when the logic level of the switching signal SW4 is “1”. The power supply line 2 is grounded to the PDP ground potential Vs.

The pixel data pulse generation circuit 22, in response to each of the pixel data bits DB ₁ to DB _m of one line supplied from the drive control circuit 50 (m pieces), each independently switching the on-off control Elements SWZ _{1 to} SWZ _m and SWZ _{1O to} SWZ _mO are provided. Each of the switching elements SWZ _{1 to} SWZ _m is turned on only when the pixel data bit DB supplied to the switching elements SWZ _{1 to} SWZ _m is at the logic level “1”, and the potential generated on the power supply line 2 is set to the PDP 10. Applied to the column electrodes Z _{1 to} Z _m . Each of the switching elements SWZ _{1O to} SWZ _mO is turned on only when the pixel data bit DB is at the logic level “0”, and grounds the potential on the column electrode to the PDP ground potential Vs.

  FIG. 5 is a diagram showing internal operation waveforms of the column electrode drive circuit 20.

When a high-voltage pixel data pulse is continuously applied to the column electrode Z _i (i is 1 to m), as shown in FIG. 5B, the switching element SWZ _i (i is 1 to m). There the on-state, the switching element SWZ _io (i is 1 to m) is in the oFF state.

  On the other hand, the drive control circuit 50 supplies the switching signals SW2 to SW4 having the logic level “0” and the switching signal SW1 having the logic level “1” to the power supply circuit 21 (driving step G1).

Thereby, only switching element S1 is turned on among switching elements S1 to S4, and the electric charge stored in capacitor C1 is discharged. Therefore, a current flows to the column electrode Z _i through the coil L1, the diode D1, the switching element S1, and the switching element SWZ _i , and the load capacitance C ₀ is charged. At this time, the potential of the column electrode Z _i gradually rises as shown in FIG. 5B by a time constant determined by the coil L1 and the load capacitance C ₀ .

Next, when the half cycle of the resonance period due to the coil L1 and the load capacitance has elapsed, the drive control circuit 50 switches only the switching signal SW3 to the logic level “1” (drive process G2). As a result, the switching element S3 is turned on, the power supply potential Va from the DC power supply B1 is applied onto the power supply line 2, and the potential of the column electrode Z _i is fixed to the power supply potential Va.

Next, the drive control circuit 50 switches the switching signal SW1 to the logic level “0” (drive process G3). Thus, the switching element S1 is turned off, the resonance operation by the coil L1 and the load capacitance C ₀ is stopped.

Next, the drive control circuit 50 switches the switching signal SW2 to the logic level “1” and the switching signal SW3 to the logic level “0” (drive process G4). As a result, the electric charge stored in the load capacitor C ₀ is discharged. Therefore, a current flows to the capacitor C1 through the switching element SWZ _i , the coil L2, the diode D2, and the switching element S2, and the capacitor C1 is charged. At this time, the potential of the column electrode Z _i gradually decreases as shown in FIG. 5B by the time constant determined by the coil L2 and the load capacitance C ₀ .

  Next, when the half cycle of the resonance period due to the coil L1 and the load capacitance has elapsed, the drive control circuit 50 switches the short-pulse logic level “1” so that the switching element S4 is turned on for a predetermined short period. The signal SW4 is supplied to the power supply circuit 21 (driving step G5).

As a result, the power supply line 2 is grounded to the PDP ground potential Vs for the short period. At this time, a current flows into the switching element S4 from the PDP 10 via the switching element SWZ _i and the power supply line 2, but the current flowing into the switching element S4 is limited and the potential of the power supply line 2 decreases to 0 [V]. The on period of the switching element S4 is set short so as not to occur. At this time, as shown in FIG. 5B, the amplitude Vf of the potential waveform on the power supply line 2 is smaller than that when the high-voltage pixel data pulse is applied to the column electrode Z _i discontinuously. It has become.

Through a series of operations including the driving steps G1 to G5, the power supply circuit 21 generates a power supply potential having a potential fluctuation as shown in FIG. 5B, and this is applied to the power supply line 2 and the switching element SWZ _i . Then, it is continuously applied to the column electrode Z _i as a high-voltage pixel data pulse. As described above, by limiting the current flowing into the switching element S4 so that the potential of the power supply line 2 does not drop to 0 [V], the amplitude of the potential change generated on the power supply line 2 is reduced, thereby reducing the power consumption. Can be reduced.

On the other hand, when a high-voltage pixel data pulse is applied to the column electrode Z _i discontinuously, a power supply potential having a potential variation as shown in FIG. 5A is generated. In this case, when the pixel data bit DB is at the logic level “1”, the switching element SWZ _i of the pixel data pulse generation circuit 22 is turned on and the switching element SWZ _io is turned off, while the pixel data bit DB is at the logic level. In the case of “0”, the switching element SWZ _i of the pixel data pulse generation circuit 22 is turned off and the switching element SWZ _io is turned on.

Therefore, when the pixel data bit DB is switched from the logic level “1” to “0”, the switching element SWZ _i0 is turned on, the column electrode Z _i is grounded, and the potential of the column electrode Z _i is set to 0 [V]. Fixed.

When the pixel data bit DB is switched from the logic level “0” to “1”, the switching element SWZ _i is turned on and the switching element SWZ _i0 is turned off.

Simultaneously with the switching element SWZ _i being turned on, only the switching element S1 is turned on, and the charge stored in the capacitor C1 is discharged. Therefore, a current flows to the column electrode Z _i through the coil L1, the diode D1, the switching element S1, and the switching element SWZ _i , and the load capacitor C ₀ is charged. At this time, the potential of the column electrode Z _i gradually rises as shown in FIG. 5A by a time constant determined by the coil L1 and the load capacitance C ₀ .

Next, when the half cycle of the resonance period due to the coil L1 and the load capacitance has elapsed, the switching element S3 is turned on, the power supply potential Va from the DC power supply B1 is applied onto the power supply line 2, and the column electrode Z _i The potential is fixed at the power supply potential Va.

Next, the switching element S1 is turned off, the resonance operation by the coil L1 and the load capacitance C ₀ is stopped.

Next, the drive control circuit 50 turns on the switching element S2, switching element S3 is turned off, the charge stored in the load capacitor C ₀ is discharged. Therefore, a current flows to the capacitor C1 through the switching element SWZ _i , the coil L2, the diode D2, and the switching element S2, and the capacitor C1 is charged. At this time, the potential of the column electrode Z _i gradually decreases as shown in FIG. 5B by the time constant determined by the coil L2 and the load capacitance C ₀ .

Next, when the half cycle of the resonance period by the coil L1 and the load capacitance has elapsed, to turn on the switching element SWZ _io with the switching element S4 to a predetermined short duration ON state. Through the series of operations described above, discontinuous pixel data pulses are applied to the column electrode Z _i .

When the current becomes large as described above, the power supply circuit 21 first selectively discharges the electric charge accumulated in the capacitor C1 by the first switching current path including the coil L1, the diode D1, and the switching element S1, By supplying this to the power supply line 2 (driving step G1), the rising edge portion of the pixel data pulse is generated. Next, a pulse voltage (Va) of a pixel data pulse is generated by applying a power supply potential on the power supply line 2 through the second switching current path including the DC power supply B1 and the switching element S3 (driving step G3). . Next, the charge accumulated in the load capacitor C ₀ existing in the column electrode is selectively transferred to the capacitor C 1 via the power line 2 by the third switching current path including the coil L 2, the diode D 2, and the switching element S 2. By charging and collecting (driving step G4), the falling edge portion of the pixel data pulse is generated. Finally, the power supply line 2 is forcibly grounded for a predetermined short period by the switching element S4 as the fourth switching current path (driving step G5), thereby determining the lowest potential as the pixel data pulse. .

Above, in the present invention As described in detail, the column electrode of the power supply lines and the display panel cyclically voltage is supplied line voltage to change, by connecting a predetermined period in accordance with a video signal, In applying the pixel data pulse on the column electrode, when the pixel data pulse is applied continuously, the change width of the line voltage is made smaller than when the pixel data pulse is applied discontinuously.

  Therefore, according to the display panel driving apparatus of the present invention, the power consumption when the pixel data pulse is generated is reduced.

It is a figure which shows schematic structure of the plasma display apparatus using a plasma display panel as a flat display panel. It is a figure which shows the application timing of the various drive pulses applied to PDP10 in 1 subfield. It is a figure which shows the structure of the display apparatus carrying the drive device by this invention. 2 is a diagram showing an internal configuration of a column electrode drive circuit 20. FIG. 4 is a diagram for explaining the internal operation of the column electrode drive circuit 20. FIG.

Explanation of symbols

B1 DC power supply
C1 capacitor
D1, D2 diode
L1, L2 coil
S1-S4 switching element
10 PDP
20 row electrode drive circuit
50 Drive control circuit

Claims (4)

A display panel driving device for driving a display panel in which pixel cells corresponding to pixels are formed at intersections of a plurality of row electrodes and a plurality of column electrodes arranged to intersect the row electrodes,
A power supply circuit that generates a line voltage on the power supply line, the voltage of which periodically changes by periodically repeating power supply, charge recovery, and discharge ;
A pixel data pulse generation circuit for generating a pixel data pulse on the column electrode by connecting the power line and the column electrode for a predetermined period according to pixel data for each pixel based on an input video signal. ,
When the pixel data pulse is applied to one of the column electrodes continuously for each predetermined period , the power supply circuit makes the change width of the line voltage smaller than when the pixel data pulse is applied intermittently. A display panel driving device having charge recovery / discharge characteristics . The power circuit includes a capacitor, a first switching current path for selectively discharging the charge accumulated in the capacitor and supplying the capacitor to the power line, and a predetermined power supply potential selectively being applied to the power line. 2. A second switching current path to be applied, and a third switching current path for selectively charging the capacitor through the power supply line with a charge accumulated on the column electrode. The drive device of the display panel as described. When the pixel data pulse is continuously applied to the column electrode, the maximum potential of the pixel data pulse is the same as the power supply potential, and the minimum potential of the pixel data pulse is a positive polarity greater than 0 volt. 3. The display panel driving device according to claim 2, wherein the driving device is a potential. The power circuit includes a capacitor, a first switching current path that selectively discharges the electric charge accumulated in the capacitor and supplies the electric power to the power line, and a predetermined power supply potential is selectively applied to the power line. A second switching current path to be applied, and a third switching current path for selectively charging the capacitor through the power line with the charge accumulated on the column electrode,
2. The pixel data pulse generation circuit generates the pixel data pulse to be supplied to each of the plurality of column electrodes based on the line voltage generated by a single power supply circuit. Drive device for display panel.

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