JP2004280132A - Driving device of display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving device of a display panel that can reduce the power consumption in pixel data pulse generation. <P>SOLUTION: Pixel data pulses are applied to a row electrode of the display panel by connecting the column electrode of the display panel for a specified period to a power line to which a source voltage cyclically varying between 0 volt and a specified source potential is supplied according to pixel data by pixels based upon an input video signal. In this case, the source voltage is limited to a smaller amplitude when the pixel data pulses are continuously applied than when discontinuously applied. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a driving device for driving a display panel such as an AC-driven plasma display panel or an electroluminescent display panel.

  At present, a display device using a display panel in which capacitive light-emitting elements such as a plasma display panel or an electroluminescence display panel are arranged in a matrix as a wall-mounted TV has been commercialized.

  FIG. 1 is a diagram showing a schematic configuration of a display device using a plasma display panel as such a display panel.

In FIG. 1, a PDP 10 as a plasma display panel has row electrodes Y _{1 to} Y _n and X which form a row electrode pair corresponding to each row (first row to n-th row) of one screen with one pair of X and Y. _{1 to Xn} . Furthermore, the PDP 10 has column electrodes Z _{1 to} Z ₁ orthogonal to the row electrode pairs and corresponding to each column (first column to m-th column) of one screen across a dielectric layer and a discharge space (not shown). _m is formed. It should be noted that a discharge cell serving as one pixel is formed at the intersection of one row electrode pair (X, Y) and one column electrode Z.

  At this time, each discharge cell has only two states, "light emission" and "non-light emission", depending on whether or not a discharge occurs in the discharge cell. In other words, only two levels of luminance, that is, the lowest luminance (non-light emitting state) and the highest luminance (light emitting state) can be expressed.

  Therefore, in order to obtain a halftone luminance corresponding to the input video signal, the driving device 100 performs gradation driving using the subfield method for the PDP 10 having such a light emitting element.

  In the sub-field method, an input video signal is converted into N-bit pixel data corresponding to each pixel, and a display period of one field is divided into N sub-fields corresponding to each of the N-bit bits. To divide. Each subfield is assigned the number of times of discharge execution corresponding to the weight of the subfield, and the discharge is selectively generated only in the subfield corresponding to the video signal. At this time, the halftone luminance corresponding to the video signal can be obtained by the total number of discharges generated in each subfield (within one field display period).

  Note that a selective erase address method is known as a method of actually driving a PDP by using the subfield method.

  FIG. 2 is a diagram showing the application timings of various drive pulses applied to the column electrodes and the row electrodes of the PDP 10 by the drive device 100 in one subfield when performing the gradation drive based on the selective erase address method. is there.

First, the driving device 100 simultaneously applies a negative reset pulse RP _x row electrodes X ₁ to X _n, further a positive reset pulse RP _Y to the row electrodes Y ₁ to Y _n, respectively (simultaneous reset process Rc) .

Depending on the application of these reset pulses RP _x and RP _Y, all the discharge cells in the PDP10 is reset discharge, uniform predetermined amount of wall charge in each discharge cell is formed. As a result, all the discharge cells are initially set to "light emitting cells".

Next, the driving device 100 converts the input video signal into, for example, 8-bit pixel data for each pixel. The driving device 100 obtains pixel data bits by dividing the pixel data for each bit digit, and generates a pixel data pulse having a pulse voltage corresponding to the logic level of the pixel data bits. FIG. 2 shows the pixel data pulse groups DP _{1 to} DP _n corresponding to the first to n-th rows, respectively, in which the driving device 100 groups such pixel data pulses for each row (m). As described above, the voltage is sequentially applied to the column electrodes Z _{1 -m} . The driving device 100 generates a high-voltage pixel data pulse when the pixel data bit is, for example, a logical level “1”, and generates a low-voltage (0 volt) pixel data pulse when the pixel data bit is a logical level “0”. Furthermore, the driving device 100, at the pixel data pulse group DP each application timing, generates a scanning pulse SP such is shown in Figure 2, sequentially applies this to row electrodes Y ₁ to Y _n (Pixel data writing process Wc). At this time, a discharge (selective erase discharge) occurs only in the discharge cell at the intersection of the “row” to which the scan pulse SP is applied and the “column” to which the high-voltage pixel data pulse is applied, and the discharge cell Are selectively erased. As a result, the discharge cells initialized to the “light emitting cell” state in the simultaneous resetting process Rc change to “non-light emitting cells”. On the other hand, as described above, the selective erasing discharge is not generated in the discharge cells formed crossing the "rows" and "columns" to which the low-voltage pixel data pulse is applied although the scan pulse SP is applied. The state initialized in the simultaneous reset step Rc, that is, the state of the “light emitting cell” is maintained.

Next, the drive apparatus 100, as well as applied to repeatedly the row electrodes X ₁ to X _n. However, such positive polarity sustain pulse IP _X in shown in FIG. 2, the sustain pulse IP _X is the row electrodes X ₁ to X _n during the application that is not period and although such a positive polarity sustain pulse IP _Y of the repeatedly applied to the row electrodes Y ₁ to Y _n shown in FIG. 2 (light emission sustain process Ic).

At this time, the discharge cells in which the wall charges remain, i.e., only "light-emitting cell", discharge every time these sustain pulses IP _X and IP _Y are alternately applied (sustain discharge) to. That is, only the discharge cells set as "light emitting cells" in the pixel data writing process Wc repeat light emission accompanying the sustain discharge by the number of times corresponding to the weight of the subfield, and maintain the light emitting state. . Incidentally, the number of times that these sustain pulses IP _X and IP _Y are applied, a number set in advance in accordance with the weighting of each subfield.

Next, the drive apparatus 100 applies an erase pulse EP, such is shown in Figure 2 to the row electrodes X ₁ to X _n (erasing step E). As a result, all the discharge cells are simultaneously erase-discharged to eliminate the wall charges remaining in each discharge cell.

  By executing the above-described series of operations a plurality of times in one field, an intermediate luminance corresponding to a video signal can be obtained in a visual state.

  However, when a pixel data pulse is applied to a column electrode of a display panel having a capacitive light emitting element such as a plasma display panel or an electroluminescence display panel, charge and discharge are caused by a parasitic capacitance existing between the column electrodes due to a potential difference generated between the column electrodes. This causes a problem that reactive power is consumed. In addition, when the number of column electrodes is increased for displaying high-quality television images, the number of pixel data pulses to be applied to the column electrodes is correspondingly increased, so that power consumption is also increased.

  Therefore, a driving device that can apply a pixel data pulse to a display panel while suppressing power consumption is now desired.

  An object of the present invention is to provide a display panel driving device capable of reducing power consumption when a pixel data pulse is generated.

  2. The display panel driving device according to claim 1, wherein the display panel includes a plurality of row electrodes and a plurality of column electrodes arranged so as to intersect the row electrodes. A drive device for a display panel to be driven, comprising: a power supply circuit that generates a power supply voltage whose voltage fluctuates periodically and applies the power supply line to a power supply line; and a power supply according to pixel data for each pixel based on an input video signal. A pixel data pulse generating circuit that generates a pixel data pulse on the column electrode by connecting a line to the column electrode for a predetermined period, wherein the power supply circuit is configured to output the pixel data pulse to the column electrode continuously. In this case, the amplitude of the power supply voltage is made smaller than in the case of discontinuous application.

  By applying a pixel data pulse to a column electrode by connecting a power supply line to which a power supply voltage whose voltage fluctuates periodically and a column electrode of a display panel are connected for a predetermined period according to a video signal, When the pixel data pulse is applied continuously, the amplitude of the power supply voltage is made smaller than when the pixel data pulse is applied discontinuously.

  FIG. 3 is a diagram illustrating a configuration of a display device including the driving device according to the present invention.

In FIG. 3, a PDP 10 as a plasma display panel has row electrodes Y _{1 to} Y _n and X forming a row electrode pair corresponding to each row (first row to n-th row) of one screen with one pair of X and Y. _{1 to Xn} . Furthermore, the PDP 10 has column electrodes Z _{1 to} Z ₁ orthogonal to the row electrode pairs and corresponding to each column (first column to m-th column) of one screen across a dielectric layer and a discharge space (not shown). _m is formed. It should be noted that a discharge cell serving as one pixel is formed at the intersection of one row electrode pair (X, Y) and one column electrode Z.

Drive control circuit 50, such as is shown in FIG. 2, the reset pulses RP _X and RP _Y, the scan pulse SP, and sustaining pulses IP _X and IP _Y each generates various timing signals for generating, these lines It is supplied to each of the electrode drive circuits 30 and 40. The row electrode drive circuit 30, such timing signals depending on and generates a reset pulse RP _X and the sustain pulses IP _X, applies them to the PDP10 in the row electrode X ₁ to X _n at which it such timing shown in FIG. 2 . On the other hand, the row electrode drive circuit 40 generates each of a reset pulse RP _Y , a scan pulse SP, a sustain pulse IP _Y and an erase pulse EP in accordance with various timing signals supplied from the drive control circuit 50. 2 are applied to the row electrodes Y _{1 to} Y _n of the PDP 10 at the timing shown in FIG.

Further, the drive control circuit 50 converts the input video signal into, for example, 8-bit pixel data for each pixel, and divides this pixel data for each bit digit to correspond to each of the first to n-th rows. Those extracted for each row (m pieces) are supplied to the column electrode drive circuit 20 as pixel data bits DB _{1 to} DB _m . At this time, the drive control circuit 50 generates switching signals SW1 to SW4 for generating pixel data pulses corresponding to the pixel data bits DB, and supplies these to the column electrode drive circuit 20.

  FIG. 4 is a diagram showing an internal configuration of the column electrode drive circuit 20.

  As shown in FIG. 4, the column electrode drive circuit 20 includes a power supply circuit 21 and a pixel data pulse generation circuit 22.

  One end of the capacitor C1 in the power supply circuit 21 is grounded to the PDP ground potential Vs as the ground potential of the PDP 10. The switching element S1 is in the OFF state while the switching signal SW1 of the logic level “0” is supplied from the drive control circuit 50. On the other hand, when the logic level of the switching signal SW1 is "1", the switching signal SW1 is turned on, and the potential generated at the other end of the capacitor C1 is applied to the power supply line 2 via the coil L1 and the diode D1. . As a result, the capacitor C1 starts discharging, and the potential generated by the discharging is applied to the power supply line 2. The switching element S2 is off while the switching signal SW2 of the logic level “0” is supplied from the drive control circuit 50, and is on when the logic level of the switching signal SW2 is “1”. In this state, the potential on the power supply line 2 is applied to the other end of the capacitor C1 via the coil L2 and the diode D2. At this time, the capacitor C1 is charged by the potential on the power supply line 2. The switching element S3 is off while the switching signal SW3 of the logic level “0” is supplied from the drive control circuit 50, and is on when the logic level of the switching signal SW3 is “1”. In this state, the power supply potential Va from the DC power supply B1 is applied to the power supply line 2. The negative terminal of the DC power supply B1 is grounded at the PDP ground potential Vs. The switching element S4 is off while the switching signal SW4 of the logic level “0” is being supplied from the drive control circuit 50, and is on when the logic level of the switching signal SW4 is “1”. In this state, the power supply line 2 is grounded to the PDP ground potential Vs.

The pixel data pulse generation circuit 22, in response to each of the pixel data bits DB ₁ to DB _m of one line supplied from the drive control circuit 50 (m pieces), each independently switching the on-off control element SWZ ₁ ~SWZ _m, and SWZ _1O ~SWZ _mO provided. Each of the switching elements SWZ _{1 to} SWZ _m is turned on only when the pixel data bit DB supplied thereto is at the logical level “1”, and changes the potential generated on the power supply line 2 to the PDP 10. It applied to the column electrodes Z ₁ to Z _m. The switching element SWZ _1O ~SWZ _mO each, respectively, the pixel data bit DB is turned only turned on when a logic level "0", to ground the potential on the column electrode to the PDP ground potential Vs.

  FIG. 5 is a diagram showing an internal operation waveform of the column electrode drive circuit 20.

When a high-voltage pixel data pulse is continuously applied to the column electrode Z _i (i is 1 to m), as shown in FIG. 5B, the switching element SWZ _i (i is 1 to m) Are on, and the switching element SWZ _io (i is 1 to m) is off.

  On the other hand, the drive control circuit 50 supplies the switching signals SW2 to SW4 of the logic level “0” and the switching signal SW1 of the logic level “1” to the power supply circuit 21 (drive step G1).

As a result, only the switching element S1 of the switching elements S1 to S4 is turned on, and the charge stored in the capacitor C1 is discharged. Accordingly, the coil L1, the diode D1, current through the switching element S1 and switching element SWZ _i flows into the column electrode Z _i, the load capacitance C ₀ is charged. At this time, the potential of the column electrode Z _i by a time constant determined by the coil L1 and the load capacitance C ₀ is increased gradually as shown in Figure 5 (b).

Next, when a half cycle of the resonance cycle due to the coil L1 and the load capacitance has elapsed, the drive control circuit 50 switches only the switching signal SW3 to the logical level “1” (drive step G2). Thus, the switching element S3 is turned on, the power supply potential Va by the DC power source B1 is applied to the power supply line 2, the potential of the column electrode Z _i is fixed at the power supply potential Va.

Next, the drive control circuit 50 switches the switching signal SW1 to the logical level “0” (drive step G3). Thus, the switching element S1 is turned off, the resonance operation by the coil L1 and the load capacitance C ₀ is stopped.

Next, the drive control circuit 50 switches the switching signal SW2 to the logical level “1” and the switching signal SW3 to the logical level “0” (drive step G4). Thereby, the charge stored in the load capacitance C ₀ is discharged. Thus, current flows through the switching element SWZ _i , the coil L2, the diode D2, and the switching element S2 to the capacitor C1, and the capacitor C1 is charged. At this time, the potential of the column electrode Z _i by a time constant determined by the coil L2 and the load capacitance C ₀ decreases gradually as shown in Figure 5 (b).

  Next, when a half cycle of the resonance cycle due to the coil L1 and the load capacitance has elapsed, the drive control circuit 50 switches the short pulse logic level “1” to turn on the switching element S4 for a predetermined short period. The signal SW4 is supplied to the power supply circuit 21 (drive step G5).

Thereby, the power supply line 2 is grounded to the PDP ground potential Vs for the short period. At this time, a current flows from the PDP 10 into the switching element S4 via the switching element SWZ _i and the power supply line 2. However, the current flowing into the switching element S4 is limited to lower the potential of the power supply line 2 to 0 [V]. The on-period of the switching element S4 is set short so as not to cut off. At this time, as shown in FIG. 5 (b), the amplitude Vf of the power supply line 2 on the potential waveform is smaller than in the case where the pixel data pulse of high voltage is discontinuously applied to the column electrode Z _i Has become.

By a series of operations including the driving steps G1 to G5, the power supply circuit 21 generates a power supply potential having a potential variation as shown in FIG. 5B, and supplies the power supply potential to the power supply line 2 and the switching element SWZ _i . as a high-voltage pixel data pulse through, applied to the column electrode Z _i in succession. As described above, by limiting the current flowing into the switching element S4 so that the potential of the power supply line 2 does not drop to 0 [V], and thereby reducing the amplitude of the potential change occurring on the power supply line 2, power consumption is reduced. Can be reduced.

On the other hand, when the pixel data pulse of high voltage is discontinuously applied to the column electrode Z _i generates a power supply potential having Although such potential variation is shown in Figure 5 (a). In this case, when the pixel data bit DB is at the logic level “1”, the switching element SWZ _i of the pixel data pulse generation circuit 22 is turned on and the switching element SWZ _io is turned off. When it is “0”, the switching element SWZ _i of the pixel data pulse generation circuit 22 is turned off and the switching element SWZ _io is turned on.

Therefore, when the pixel data bit DB switches from the logical level “1” to “0”, the switching element SWZ _i0 is turned on, the column electrode Z _i is grounded, and the potential of the column electrode Z _i becomes 0 [V]. Fixed.

When the pixel data bit DB switches from the logical level “0” to “1”, the switching element SWZ _i is turned on and the switching element SWZ _i0 is turned off.

At the same time as the switching element SWZ _i is turned on, only the switching element S1 is turned on, and the electric charge stored in the capacitor C1 is discharged. Accordingly, the coil L1, the diode D1, current through the switching element S1 and switching element SWZ _i flows into the column electrode Z _i, the load capacitance C ₀ is charged. At this time, the potential of the column electrode Z _i by a time constant determined by the coil L1 and the load capacitance C ₀ is increased gradually as shown in Figure 5 (a).

Next, when a half cycle of the resonance cycle due to the coil L1 and the load capacitance has elapsed, the switching element S3 is turned on, the power supply potential Va from the DC power supply B1 is applied to the power supply line 2, and the column electrode Z _i The potential is fixed at the power supply potential Va.

Next, the switching element S1 is turned off, the resonance operation by the coil L1 and the load capacitance C ₀ is stopped.

Next, the drive control circuit 50 turns on the switching element S2, switching element S3 is turned off, the charge stored in the load capacitor C ₀ is discharged. Thus, current flows through the switching element SWZ _i , the coil L2, the diode D2, and the switching element S2 to the capacitor C1, and the capacitor C1 is charged. At this time, the potential of the column electrode Z _i by a time constant determined by the coil L2 and the load capacitance C ₀ decreases gradually as shown in Figure 5 (b).

Next, when the half cycle of the resonance period by the coil L1 and the load capacitance has elapsed, to turn on the switching element SWZ _io with the switching element S4 to a predetermined short duration ON state. The series of operations described above, discrete pixel data pulse is applied to the column electrode Z _i.

When the current is large as described above, the power supply circuit 21 first selectively discharges the charge accumulated in the capacitor C1 by the first switching current path including the coil L1, the diode D1, and the switching element S1, This is supplied to the power supply line 2 (driving process G1) to generate a rising edge portion of the pixel data pulse. Next, a pulse voltage (Va) of a pixel data pulse is generated by applying a power supply potential to the power supply line 2 through the second switching current path including the DC power supply B1 and the switching element S3 (drive step G3). . Next, the charge stored in the load capacitance C ₀ existing in the column electrode is selectively transferred to the capacitor C 1 via the power supply line 2 by the third switching current path including the coil L 2, the diode D 2, and the switching element S 2. By charging and collecting (driving process G4), a falling edge portion of the pixel data pulse is generated. Finally, the power supply line 2 is forcibly grounded for a predetermined short period by the switching element S4 as a fourth switching current path (drive step G5), thereby determining the lowest potential as a pixel data pulse. .

  As described in detail above, in the present invention, the power supply line to which the power supply voltage whose voltage fluctuates periodically is connected to the column electrode of the display panel for a predetermined period in accordance with the video signal, and thereby the column is connected. In applying the pixel data pulse to the electrode, the amplitude of the power supply voltage is smaller when the pixel data pulse is continuously applied than when the pixel data pulse is applied discontinuously.

  Therefore, according to the display panel driving device of the present invention, the power consumption when the pixel data pulse is generated is reduced.

FIG. 1 is a diagram illustrating a schematic configuration of a plasma display device using a plasma display panel as a flat display panel. FIG. 3 is a diagram showing application timings of various drive pulses applied to the PDP 10 within one subfield. FIG. 2 is a diagram showing a configuration of a display device equipped with a driving device according to the present invention. FIG. 3 is a diagram showing an internal configuration of a column electrode drive circuit 20. FIG. 3 is a diagram for explaining an internal operation of a column electrode drive circuit 20.

Explanation of reference numerals

B1 DC power supply
C1 capacitor
D1, D2 diode
L1, L2 coil
S1-S4 switching element
10 PDP
20 column electrode drive circuit
50 Drive control circuit

Claims (3)

A display panel driving device for driving a display panel in which pixel cells corresponding to pixels are formed at intersections of a plurality of row electrodes and a plurality of column electrodes arranged to intersect the row electrodes,
A power supply circuit that generates a power supply voltage whose voltage fluctuates periodically and applies the power supply voltage on a power supply line;
A pixel data pulse generation circuit that generates a pixel data pulse on the column electrode by connecting the power supply line and the column electrode for a predetermined period according to pixel data of each pixel based on an input video signal. ,
The display panel, wherein the power supply circuit reduces the amplitude of the power supply voltage when the pixel data pulse is continuously applied to the column electrode as compared with a case where the pixel data pulse is applied discontinuously. Drive.   The power supply circuit includes a capacitor, a first switching current path for selectively discharging electric charges stored in the capacitor and supplying the electric power to the power supply line, and selectively supplying a predetermined power supply potential to the power supply line. 2. The method according to claim 1, further comprising: a second switching current path to be applied; and a third switching current path for selectively charging the electric charge accumulated on the column electrode via the power supply line to the capacitor. The driving device of the display panel according to the above.   When the pixel data pulse is continuously applied to the column electrode, the maximum potential of the pixel data pulse is the same as the power supply potential, and the minimum potential of the pixel data pulse is a positive potential greater than 0 volt. The driving device for a display panel according to claim 2, wherein the driving device is a potential.

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