JP2008277598A - Field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor wherein a breakdown voltage is high, a threshold voltage is stable and a transition current for a gate electrode is small. <P>SOLUTION: The field effect transistor of this invention has a source, a first gate, a second gate and a drain provided with respective metal electrodes in the order on positions separated from each other along the surface of a semiconductor layer on the semiconductor layer. The first gate is an MIS type and the second gate is a Schottky type. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a field effect transistor, and more particularly to a power field effect transistor having a heterostructure.

Conventionally, an HFET (Heterostructure Field Effect Transistor) as shown in FIG. 4 is known as a field effect transistor (for example, Non-Patent Document 1 (Adivarahan et al., “ submicron gate _Si 3 _N 4 / AlGaN / GaN- metal - insulator - semiconductor heterostructure field effect transistor _{(submicron gate Si 3 N 4 /} AlGaN / GaN-metal-insulator-semiconductor heterostructure field-effect transistors) "eye (Refer to IEEE Electron Device Letters, Vol. 24, No. 9, pp. 541-543, 2003.) In this HFET, an AlN buffer is formed on a SiC substrate 2001. layer (thickness 500 Å) 2002, (1.5 [mu] m _thickness) channel layer composed of undoped GaN from _2003, Al _{0.25 Ga 0.75} N The Ti / Al / Au source ohmic electrode 2005 and the Ti / Al / Au drain ohmic electrode 2006 are formed separately from each other (a thickness of 250 mm) 2004. A Si ₃ N ₄ gate insulating film (thickness: 80 mm) 2008 is formed on a layer 2004 made of Al _0.25 Ga _0.75 N between 2005 and the drain ohmic electrode 2006, and a gate is formed on the gate insulating film 2008. An electrode 2010 is formed, and this device is an n-channel “normally on” type and has a threshold voltage of about −6.5 V. Note that normally on is directly below a zero-biased gate (metal electrode). Means that the carrier (in this example, the two-dimensional electron gas) can move across the channel region. Over the source electrode 2005 is grounded (ground), the drain electrode 2006 is connected to a load circuit (not shown). Then, the gate driving signal to the gate electrode 2010 is input, the output from the drain electrode 2006 to the load circuit is taken out.

FIG. 6 shows an “H-bridge” switching circuit configured by using four HFETs shown in FIG. 4 (represented by reference numerals 2101A, 2101B, 2101C, 2101D, respectively). This switching circuit includes a driver circuit 2100 that controls on and off of four HFETs 2101A, 2101B, 2101C, and 2101D at a predetermined timing, and a free circuit connected in antiparallel to these HFETs 2101A, 2101B, 2101C, and 2101D. Wheel diodes 2102A, 2102B, 2102C, and 2102D. These freewheeling diodes 2102A, 2102B, 2102C, and 2102D are used when the corresponding HFETs 2101A, 2101B, 2101C, and 2101D are turned on, and the drain voltage is switched to become a negative value with a large absolute value (in the case of an inductance load). Is provided to bypass the reverse drain current (charges swept away from within the transistor). Reference numeral 2103 denotes an inductance load. If these freewheeling diodes are simply omitted, the HFET gate may be forward biased and the HFET may be destroyed.
Adivarahan et al., “Submicron Gate Si3N4 / AlGaN / GaN-Metal-Insulator-Semiconductor Field-Effect Transistors” ”, IE Electron Device Letters, Vol.24, No.9, pp.541-543, 2003

  However, the HFET shown in FIG. 4 has the following problems.

  i) When the transistor (HFET) is off and a high drain-source voltage is applied and the drain-gate voltage is high, holes generated by impact ionization are avalanche multiplied. As a result, they gather under the gate insulating film 2008 immediately below the gate electrode 2010. For this reason, there is a problem that the transistor is turned on undesirably, that is, the breakdown voltage (withstand voltage) is low.

  ii) Holes generated by such impact ionization become hot holes that are injected into the gate insulating film 2008 immediately below the gate electrode 2010 and trapped. For this reason, there is a problem that the threshold voltage is not stable.

  iii) There is a problem that the transition current for the gate electrode is large. That is, during normal power switching operation, the source-drain voltage of the HFET oscillates periodically from a low voltage to a high voltage. Since most of the source-drain voltage is applied between the gate and drain (voltage drop), a large amount of charge is accumulated or released in the gate electrode in accordance with switching. This transitional charge flow, i.e., transition current, must be supplied by a driver circuit (e.g., driver circuit 2100 as shown in FIG. 6). When a high-speed switching operation is performed, this transition current becomes very large. As a result, the power consumption of the driver circuit that drives the HFET increases. Further, if the driver circuit cannot supply sufficient current, the power consumption of the HFET increases.

  Accordingly, an object of the present invention is to provide a field effect transistor having a high breakdown voltage, a stable threshold voltage, and a small transition current for the gate electrode.

In order to solve the above problems, the field effect transistor of the present invention is
A source having a metal electrode, a first gate, a second gate, and a drain are provided in this order at positions spaced apart from each other along the surface of the semiconductor layer on the semiconductor layer,
The first gate is a MIS type, and the second gate is a Schottky type.

  In the field effect transistor of the present invention, during a typical operation, a high frequency signal (including a switching drive signal and a high frequency input signal to be amplified) is applied to the first gate, and a DC bias is applied to the second gate. (Or ground).

  Here, when a high drain-source voltage is applied while the transistor is off and the drain-second gate voltage is high, a hole (hole) is formed in the channel region by impact ionization as in the conventional example. (And electrons paired with the hole) may occur. However, in this transistor, the generated holes are swept toward the Schottky second gate and absorbed. Therefore, the transistor is not turned on, and the breakdown voltage (withstand voltage) increases.

  Further, holes (hot holes) generated by impact ionization are swept up and absorbed toward the Schottky type second gate, so that they are injected and trapped in the gate insulating film forming the first gate. There is nothing to do. Therefore, the threshold voltage of this transistor is stabilized.

  Furthermore, since the source, the first gate, the second gate, and the drain are arranged in this order, most of the source-drain voltage is applied between the second gate and the drain (voltage drop). Therefore, the magnitude of the voltage applied to the first gate is limited, and the transition current for the first gate is relatively small. As a result, the power consumption of the driver circuit that drives the field effect transistor during the switching operation is reduced. Since the DC bias is applied (or grounded) to the second gate, the driver circuit is not burdened.

  In one embodiment, the first gate is normally off and the second gate is normally on.

  “Normally-on” means a configuration in which carriers can move across a channel region immediately below the gate (metal electrode) that is zero-biased. “Normally off” means a configuration in which carriers cannot move across a channel region immediately below the zero-biased gate (metal electrode).

  In the field effect transistor of this embodiment, since the first gate is normally off and the second gate is normally on, the entire field effect transistor is normally off. Therefore, this field effect transistor is suitable for constituting a switching element of a switching circuit.

  In one embodiment, the second gate is electrically connected to the source by a wiring.

  In the field effect transistor of this one embodiment, since the second gate is electrically connected to the source by wiring, the electrical resistance between the second gate and the source is lowered. Therefore, the high frequency characteristics are improved.

  Further, when the transistor transits from the off state to the on state during the switching operation, the drain voltage becomes a negative value. Here, in this transistor, if the drain voltage becomes a large negative value, the second gate is forward-biased. Therefore, the charge passes from the contact of the drain through the metal electrode constituting the second gate, and further through the wiring. Flows through the source. As a result, the magnitude of the forward bias voltage applied to the first gate is limited, and the current flowing through the first gate does not increase. This gives the advantage of eliminating the need for a freewheeling diode when this transistor is used as a switching element.

  The field effect transistor of one embodiment is characterized in that the second gate is connected to the source by an air bridge wiring.

  Here, the “air bridge wiring” refers to a wiring in which a central portion is floated in the air and only both end portions are supported.

  In the field effect transistor according to this embodiment, the electric resistance between the second gate and the source is negligibly low due to the air bridge wiring. At the same time, the capacitance related to the second gate (capacitance between the first gate and the second gate, etc.) is lower than when a wire such as a wire is provided. Therefore, the high frequency characteristics are improved. This configuration is equivalent to a cascode circuit.

In one embodiment of a field effect transistor,
A polyimide insulating film covering the first gate is provided between the source and the second gate,
The second gate is connected to the source by a wiring supported by the polyimide insulating film.

  In the field effect transistor according to this embodiment, the electrical resistance between the second gate and the source is negligibly low due to the wiring. At the same time, the capacitance related to the second gate (capacitance between the first gate and the second gate, etc.) is lower than when a wire such as a wire is provided. Therefore, the high frequency characteristics are improved. This configuration is equivalent to a cascode circuit. Further, since the wiring is supported by the polyimide insulating film, the structure is stable.

In one embodiment of a field effect transistor,
The source, the first gate, the second gate, and the drain each have a pattern extending in one direction on the semiconductor layer,
The air bridge wiring or wiring extends in a direction perpendicular to the one direction, and a plurality of the air bridge wirings or wirings are periodically provided in the one direction.

  In the field effect transistor of this embodiment, the source, the first gate, the second gate, and the drain each have a pattern elongated in one direction on the semiconductor layer, so that a large current can be switched or amplified. In addition, since the air bridge wiring or the wiring is elongated in a direction perpendicular to the one direction, and a plurality of the air bridge wirings or wirings are periodically provided with respect to the one direction, the capacitance (the first gate) And the like between the second gate and the second gate) do not increase so much.

  In one embodiment, a dielectric film having a dielectric constant higher than that of the semiconductor active layer is provided on the surface of the semiconductor layer between the second gate and the drain so as to be in contact with at least the second gate. It is characterized by being.

  As described above, in this field effect transistor, most of the source-drain voltage is applied between the second gate and the drain (voltage drop). For this reason, dielectric breakdown particularly in the vicinity of the second gate becomes a problem. Here, in the field effect transistor of this one embodiment, since the dielectric film is provided on the surface of the semiconductor layer between the second gate and the drain so as to be in contact with at least the second gate, The maximum electric field between the gate and the drain is lowered, and the dielectric breakdown particularly in the vicinity of the second gate is prevented. Further, since the concentration of the electric field does not occur even if the carrier concentration of the two-dimensional electron gas is high, the breakdown voltage can be increased despite the low channel resistance.

  The dielectric constant of the dielectric film is preferably higher than the dielectric constant of the semiconductor layer. In this case, the maximum electric field between the second gate and the drain can be effectively reduced.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

  FIG. 1A shows a cross-sectional structure of an HFET (Heterostructure Field Effect Transistor) of one embodiment, and FIG. 1B shows a planar layout when the one of FIG. 1A is viewed from above.

As shown in FIG. 1A, the HFET includes an undoped GaN layer 102 having a thickness of 3 μm and an Al _0.3 Ga _0.7 N layer 103 having a thickness of 25 nm on a sapphire substrate 101. These semiconductor layers 102 and 103 are patterned to form a mesa 112. A two-dimensional electron gas (2DEG) 104 having a carrier concentration of n _s = 8 × 10 ¹² cm ⁻² is generated along the interface between the GaN layer 102 and the Al _0.3 Ga _0.7 N layer 103. On the Al _0.3 Ga _0.7 N layer 103, metal electrodes are provided at positions separated from each other along the surface of the layer 103, and the source 105, the first gate 106, the second gate 107, and the drain 108 are provided. They are formed in this order.

The metal electrodes constituting the source 105 and the drain 108 are made of a Ti / Al / Au laminate, and are in ohmic contact with the Al _0.3 Ga _0.7 N layer 103 directly below.

The first gate 106 is provided with a gate insulating film 114 made of SiO ₂ having a thickness of 10 nm on the surface of the Al _0.3 Ga _0.7 N layer 103, and a Ni / Au layer on the surface of the gate insulating film 114. A laminated metal electrode 106M is provided to configure the MIS type. On the other hand, the second gate 107 is configured as a Schottky junction type by providing a metal electrode made of a WN / Au stack on the surface of the Al _0.3 Ga _0.7 N layer 103. The gate length of the first gate 106 is 0.5 μm, and the gate length of the second gate 107 is 1.0 μm. The distance between the second gate 107 and the drain 108 is 5 μm. The first gate 106 is a “normally on” type, and its pinch-off voltage (threshold voltage) is −10V. The second gate 107 is also a “normally on” type, and its pinch-off voltage is −5V.

  In this HFET, the second gate 107 is electrically connected to the source 105 by an air bridge wiring 109 made of a laminate of Ti / Pt / Au. A space 119 is provided immediately below the air bridge wiring 109.

Further, a portion of the surface of the Al _0.3 Ga _0.7 N layer 103 where the metal electrode is not provided, in particular, covers the entire area between the second gate 107 and the drain 108 so as to be in contact with the second gate 107. , A passivation film 115 made of SiN _x is provided.

  In this HFET, during a typical operation, a high voltage is applied between the source 105 and the drain 108, and a high-frequency signal (including a switching drive signal and a high-frequency input signal to be amplified) is applied to the first gate 106. And a DC bias is applied (or grounded) from the source 105 to the second gate 107 through the air bridge wiring 109.

  Here, when a high drain-source voltage is applied while the transistor is off and the drain-second gate voltage is high, a hole (hole) is formed in the channel region by impact ionization as in the conventional example. (And electrons paired with the hole) may occur. However, in this transistor, the generated holes are swept toward the Schottky second gate 107 and absorbed. Therefore, the transistor is not turned on, and the breakdown voltage (withstand voltage) increases.

  Further, holes (hot holes) generated by impact ionization are swept up and absorbed toward the Schottky second gate 107 as described above, so that they are injected into the gate insulating film 114 forming the first gate 106. Will not be trapped. Therefore, the threshold voltage of this transistor is stabilized.

  Furthermore, since the source 105, the first gate 106, the second gate 107, and the drain 108 are arranged in this order, most of the source-drain voltage is applied between the second gate 107 and the drain 108 (voltage drop). . Accordingly, the magnitude of the voltage applied to the first gate 106 is limited, and the transition current for the first gate 106 is relatively small. As a result, the power consumption of the driver circuit that drives the HFET during the switching operation is reduced. Since the DC bias is applied (or grounded) to the second gate 107, the driver circuit is not burdened.

  In this HFET, the electric resistance between the second gate 107 and the source 105 is reduced to a negligible level thanks to the air bridge wiring 109. At the same time, the capacitance related to the second gate 107 (capacitance between the first gate 106 and the second gate 107, etc.) is low enough to be ignored as compared with the case where wiring such as a wire is provided. Become. Therefore, the high frequency characteristics are improved. This configuration is equivalent to a cascode circuit.

  A polyimide insulating film (not shown) is provided in the space 119 immediately below the air bridge wiring 109 between the source 105 and the second gate 107 so as to cover the first gate 106, and the wiring 109 is formed with this polyimide insulating film. You may make it support. This stabilizes the structure.

  As shown in FIG. 1B, the source 105, the first gate 106, the second gate 107, and the drain 108 each have a pattern that extends in one direction (vertical direction in FIG. 1B) so that a large current can be switched or amplified. is doing. The air bridge wiring 109 has an elongated pattern with a width of 5 μm in a direction perpendicular to the one direction (left-right direction in FIG. 1B). A plurality of air bridge wires 109 are provided periodically in the vertical direction in FIG. 1B, specifically, at a pitch of 100 μm shown in FIG. 1B. In a typical example, the vertical pattern dimension (gate width) in FIG. 1B is 60 mm, and 600 structural units shown in FIG. 1B are included. As described above, since the air bridge wiring 109 is periodically provided in an elongated pattern, the capacitance related to the second gate 107 (capacitance between the first gate 106 and the second gate 107, etc.). Does not increase too much.

  Further, when the transistor transits from the off state to the on state during the switching operation, the drain voltage becomes a negative value. Here, in this transistor, if the drain voltage becomes a large negative value, the second gate 107 is forward-biased, so that the charge passes from the contact of the drain 108 through the metal electrode constituting the second gate 107 and further to the above. It flows to the source 105 through the air bridge wiring 109. As a result, the magnitude of the forward bias voltage applied to the first gate 106 is limited, and the current flowing through the first gate 106 does not increase. This gives the advantage of eliminating the need for a freewheeling diode when this transistor is used as a switching element.

  FIG. 2A shows a cross-sectional structure of an HFET according to another embodiment of the present invention, and FIG. 2B shows a planar layout when the one of FIG. 2A is viewed from above.

As shown in FIG. 2A, this HFET includes an undoped GaN layer 202 having a thickness of 3 μm and an Al _0.3 Ga _0.7 N layer 203 having a thickness of 25 nm on a SiC substrate 201. These semiconductor layers 202 and 203 are patterned to form a mesa 212. A two-dimensional electron gas (2DEG) 204 having a carrier concentration of n _s = 8 × 10 ¹² cm ⁻² is generated along the interface between the GaN layer 202 and the Al _0.3 Ga _0.7 N layer 203. On the Al _0.3 Ga _0.7 N layer 203, metal electrodes are provided at positions separated from each other along the surface of the layer 203, and the source 205, the first gate 206, the second gate 207, and the drain 208 are provided. They are formed in this order.

The metal electrodes constituting the source 205 and the drain 208 are made of a Ti / Al / Au laminate, and are in ohmic contact with the Al _0.3 Ga _0.7 N layer 203 immediately below.

The first gate 206 forms a recess groove 213 having a depth of 18 nm on the surface of the Al _0.3 Ga _0.7 N layer 203, covers the inner surface (bottom surface and side surface) of the recess groove 213, and A gate insulating film 214 made of Ta ₂ O ₅ having a thickness of 20 nm is provided so as to overlap the surfaces of the Al _0.3 Ga _0.7 N layers 203 on both sides, and WN / W is formed on the surface of the gate insulating film 214. A metal electrode 206M made of a laminate of Au is provided, and the MIS type is configured. On the other hand, the second gate 207 is configured as a Schottky junction type by providing a metal electrode made of a WN / Au laminate on the surface of the Al _0.3 Ga _0.7 N layer 203. The gate length of the first gate 206 is 0.5 μm, and the gate length of the second gate 207 is 1.0 μm. The distance between the second gate 207 and the drain 208 is 5 μm. The first gate 206 is of a “normally off” type thanks to the recess groove 213 and has a threshold voltage of + 0.3V. The second gate 207 is a “normally on” type, and its pinch-off voltage is −5V.

In this example, the gate insulating film 214 is made of Ta ₂ O ₅ . Ta ₂ O ₅ has a dielectric constant higher than that of general SiO ₂ and has a passivation effect. Therefore, it is particularly suitable as a material for a gate insulating film of a normally-off type element. However, other insulators such as SiO ₂ , SiN _x , HfO ₂ , TiO ₂ , and other metal oxide films may be used as the material of the gate insulating film.

  In this HFET, the second gate 207 is electrically connected to the source 205 by an air bridge wiring 209 made of a laminate of Ti / Pt / Au. A space 219 is immediately below the air bridge wiring 209.

In addition, the thickness of the dielectric film is such that the entire surface of the Al _0.3 Ga _0.7 N layer 203 occupies the entire area between the second gate 207 and the drain 208 and overlaps the second gate 207. A 4000 TiO ₂ film 215 is provided.

  In a typical operation, in this HFET, a high voltage is applied between the source 205 and the drain 208, and a high-frequency signal (including a switching drive signal and a high-frequency input signal to be amplified) is applied to the first gate 206. Is applied, and a DC bias is applied (or grounded) from the source 205 to the second gate 207 via the air bridge wiring 209.

  Here, as shown in FIG. 3B, when a high drain-source voltage is applied and the drain-second gate voltage is high when this transistor is in an off state, the channel is formed by impact ionization as in the conventional example. A hole (hole) 290 (and an electron 292 paired with the hole) may be generated in the region. However, in this transistor, the generated hole 290 is swept toward the Schottky-type second gate 207 and absorbed as indicated by an arrow 294. Therefore, the transistor is not turned on, and the breakdown voltage (withstand voltage) increases. Note that electrons 292 generated in the channel region by impact ionization are only swept toward the drain 208 and absorbed, as indicated by an arrow 293. On the other hand, in the HFET of the reference example shown in FIG. 3A (the HFET of FIG. 3B in which the second gate 207 and the air bridge wiring 209 are omitted), the generated hole 290 is multiplied by an avalanche (avalanche). As indicated by reference numeral 291, the films gather under the gate insulating film 214 immediately below the gate electrode 206M. For this reason, although not desired, the transistor is turned on, and the breakdown voltage (withstand voltage) is low.

  Further, the holes (hot holes) 290 generated by impact ionization are swept up and absorbed toward the Schottky second gate 207, so that they are injected into the gate insulating film 214 forming the first gate 206. Will not be trapped. Therefore, the threshold voltage of this transistor is stabilized.

  Furthermore, since the source 205, the first gate 206, the second gate 207, and the drain 208 are arranged in this order, most of the source-drain voltage is applied between the second gate 207 and the drain 208 (voltage drop). . Accordingly, the magnitude of the voltage applied to the first gate 206 is limited, and the transition current for the first gate 206 is relatively small. As a result, the power consumption of the driver circuit that drives the HFET during the switching operation is reduced. Since the DC bias is applied (or grounded) to the second gate 207, the driver circuit is not burdened.

  In this HFET, the electric resistance between the second gate 207 and the source 205 is negligibly low due to the air bridge wiring 209. At the same time, the capacitance related to the second gate 207 (capacitance between the first gate 206 and the second gate 207, etc.) is low enough to be ignored as compared with the case where a wiring such as a wire is provided. Become. Therefore, the high frequency characteristics are improved. This configuration is equivalent to a cascode circuit.

  A polyimide insulating film (not shown) is provided in the space 219 immediately below the air bridge wiring 209 between the source 205 and the second gate 207 so as to cover the first gate 206, and the wiring 209 is formed with this polyimide insulating film. You may make it support. This stabilizes the structure.

  As shown in FIG. 2B, each of the source 205, the first gate 206, the second gate 207, and the drain 208 has a pattern that is elongated in one direction (vertical direction in FIG. 2B) so that a large current can be switched or amplified. is doing. The air bridge wiring 209 has an elongated pattern with a width of 5 μm in a direction perpendicular to the one direction (left-right direction in FIG. 2B). A plurality of air bridge wirings 209 are provided periodically in the vertical direction in FIG. 2B, specifically, at a pitch of 200 μm shown in FIG. 2B. In a typical example, the vertical pattern dimension (gate width) in FIG. 2B is 60 mm, and 600 structural units shown in FIG. 2B are included. Thus, since the air bridge wiring 209 is periodically provided in an elongated pattern, the capacitance related to the second gate 207 (capacitance between the first gate 206 and the second gate 207, etc.) Does not increase too much.

As described above, in this example, the TiO ₂ film 215 as a dielectric film is provided so as to occupy the entire area between the second gate 207 and the drain 208 and overlap the second gate 207. Yes. TiO ₂ is preferable because it has a high dielectric constant and a high dielectric breakdown strength. Thanks to the dielectric film 215, the maximum electric field between the second gate 207 and the drain 208 is lowered, and the dielectric breakdown in the vicinity of the second gate 207 is prevented. Further, since the concentration of the electric field does not occur even when the carrier concentration of the two-dimensional electron gas 204 is high, the breakdown voltage can be increased although the channel resistance is low.

  The dielectric film 215 preferably has a dielectric constant higher than that of the GaN layer 202 or AlGaN layer 203. The dielectric film 215 is preferably thicker than 2000 mm. In this case, the maximum electric field between the second gate 207 and the drain 208 can be effectively reduced.

Specific examples of the material of the dielectric film 215 include HfO ₂ , TaOx, NbOx and the like in addition to TiO ₂ from the viewpoint of dielectric constant and dielectric breakdown strength.

  However, since the electrostatic capacity related to the second gate 207 increases due to the dielectric film 215, the transition current passing through the second gate 207 increases correspondingly during the switching operation. However, most of the source-drain voltage is applied between the second gate 207 and the drain 208 (voltage drop). Accordingly, the magnitude of the voltage applied to the first gate 206 is limited, and the transition current for the first gate 206 is relatively small. As a result, the power consumption of the driver circuit that drives the HFET during the switching operation is reduced.

Of course, instead of the dielectric film 215, a passivation film 115 made of SiN _x as shown in FIG. 1A may be provided.

  FIG. 5 shows an “H-bridge” switching circuit configured using four HFETs shown in FIG. 2A (indicated by reference numerals 401A, 401B, 401C, and 401D, respectively). This switching circuit includes a driver circuit 400 that controls on and off of four HFETs 401A, 401B, 401C, and 401D at a predetermined timing. Reference numeral 403 denotes an inductance load. When the drain voltage is switched and the absolute value becomes a large negative value (occurs in the case of an inductance load), the drain current in the reverse direction is changed from the metal electrode constituting the second gate 207 to the air bridge wiring as described above. 209 is bypassed and flows to source 205. As a result, the magnitude of the forward bias voltage applied to the first gate 206 is limited, and the current flowing through the first gate 206 does not increase. Therefore, the freewheeling diode required in the conventional switching circuit (see FIG. 6) is not necessary.

  In this embodiment, the GaN-based HFET has been described, but the present invention is not limited to this. The present invention is widely applied to a field effect transistor having a dual gate.

It is a figure which shows the cross-section of HFET of one Embodiment of this invention. It is a figure which shows the planar layout when the thing of FIG. 1A is seen from upper direction. It is a figure which shows the cross-section of HFET of another one Embodiment of this invention. It is a figure which shows the planar layout when the thing of FIG. 2A is seen from upper direction. 2B is a diagram for explaining the operation of a reference example corresponding to the second FET and the air bridge wiring omitted in the HFET of FIG. 2A. It is a figure explaining operation | movement of HFET of FIG. 2A. It is a figure which shows the cross-section of the conventional HFET. It is a figure which shows the structure of the switching circuit provided with HFET of FIG. 2A. It is a figure which shows the structure of the conventional H bridge switching circuit comprised using four HFETs of FIG.

Explanation of symbols

102, 202 Undoped GaN layer 103, 203 Al _0.3 Ga _0.7 N layer 104, 204 Two-dimensional electron gas 105, 205 Source 106, 206 First gate 107, 207 Second gate 108, 208 Drain 109, 209 Air Bridge wiring 213 Recess groove 215 TiO ₂ film

Claims (7)

A source having a metal electrode, a first gate, a second gate, and a drain are provided in this order at positions spaced apart from each other along the surface of the semiconductor layer on the semiconductor layer,
The field effect transistor according to claim 1, wherein the first gate is a MIS type and the second gate is a Schottky type. The field effect transistor according to claim 1.
The field effect transistor according to claim 1, wherein the first gate is normally off and the second gate is normally on. The field effect transistor according to claim 1 or 2,
The field effect transistor, wherein the second gate is electrically connected to the source by a wiring. The field effect transistor according to claim 3.
The field effect transistor according to claim 1, wherein the second gate is connected to the source by an air bridge wiring. The field effect transistor according to claim 3.
A polyimide insulating film covering the first gate is provided between the source and the second gate,
The field effect transistor according to claim 1, wherein the second gate is connected to the source by a wiring supported by the polyimide insulating film. The field effect transistor according to claim 4 or 5,
The source, the first gate, the second gate, and the drain each have a pattern extending in one direction on the semiconductor layer,
The field effect transistor according to claim 1, wherein a plurality of the air bridge wirings or wirings are elongated in a direction perpendicular to the one direction and are periodically provided in the one direction. In the field effect transistor as described in any one of Claim 1-6,
An electric field characterized in that a dielectric film having a dielectric constant higher than that of the semiconductor active layer is provided on the surface of the semiconductor layer between the second gate and the drain so as to be in contact with at least the second gate. Effect transistor.

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