JP5765978B2 - Semiconductor device and driving method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a driving method thereof.

  Power transistors that handle large amounts of power are widely used in various power supply circuits and automobiles. As the power transistor, a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is generally used.

  In recent years, GaN-HEMT (High Electron Mobility Transistor) having high breakdown field strength of GaN and high mobility of HEMT has attracted attention as a new power transistor.

  However, the breakdown voltage of the GaN-HEMT is not high for structural reasons related to the gate. Therefore, GaN-HEMT (hereinafter referred to as GaN-FP-HEMT) provided with a field plate (hereinafter referred to as FP) has been proposed. According to GaN-FP-HEMT, the gate and the source are not easily destroyed even when the drain potential is increased.

Wataru Saito, "Field-Plate Structure Dependence of Current Collapse Phenomena in Hight-Voltage GaN-HEMTs", IEEE Electron device. Vol.31, July, 2010, No.7, pp.559-661, July 2010.

  The power MOSFET has a parasitic diode in which an anode (anode) is connected to a source electrode and a cathode (cathode) is connected to a drain electrode. For this reason, when the source has a high potential with respect to the drain, a current flows from the source to the drain via the parasitic diode. Therefore, it is difficult to cut off the current flowing from the source to the drain with a single power MOSFET. Therefore, the current flow is controlled bi-directionally (ON / OFF control) using a switching circuit in which a pair of power MOSFETs in which the directions of the source and drain are reversed are connected in series. However, there is a problem that this circuit is formed by two power MOSFETs and cannot be formed by one power MOSFET.

  The GaN-FP-HEMT does not have a parasitic transistor. However, the GaN-FP-HEMT has a problem that the gate insulating layer is destroyed only when the source potential is higher than the drain potential by several tens of volts. Therefore, it is difficult to control the current flowing from the source to the drain even when the GaN-FP-HEMT is used.

  According to one aspect of the present device, a semiconductor heterojunction in which a channel layer and a barrier layer are stacked, a gate provided above the semiconductor heterojunction, and first and first electrodes provided on both sides of the gate. Two source / drain terminals, a first field plate provided between the first source / drain terminal and the gate, and a second field provided between the second source / drain terminal and the gate. A semiconductor device having a plate is provided.

  According to the semiconductor element and the driving method thereof of the present embodiment, the current flow can be controlled (ON / OFF control) in both directions without connecting other transistors.

2 is a cross-sectional view of the semiconductor element of First Embodiment. FIG. 3 is an equivalent circuit of the semiconductor element of the first embodiment. FIG. 3 is an example of a circuit diagram illustrating an operation of the semiconductor element of First Embodiment. 6 is a table showing an example of a state of a semiconductor element before and after a gate potential is changed from a first high level potential to a first low level potential in a first connection state. 10 is a table showing an example of a state of a semiconductor element before and after a gate potential changes from a first low level potential to a first high level potential in a first connection state. It is an example of sectional drawing of power MOSFET. FIG. 3 is a circuit diagram of a switching circuit that uses a power MOSFET to control a current flow in both directions. It is sectional drawing of GaN-FP-HEMT. It is an equivalent circuit of GaN-FP-HEMT. 5 is an equivalent circuit showing a modification of the semiconductor element of the first embodiment. 6 is an equivalent circuit of another modification of the first embodiment. 4 is an equivalent circuit of the semiconductor element of the second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof. In addition, the same code | symbol is attached | subjected to the corresponding part even if drawings differ, and the description is abbreviate | omitted.

(Embodiment 1)
(1) Structure FIG. 1 is a cross-sectional view of a semiconductor element 2 of the present embodiment. FIG. 2 is an equivalent circuit of the semiconductor element 2.

  The semiconductor element 2 of the present embodiment has a semiconductor heterojunction 6 provided on a substrate 4 as shown in FIG. The substrate 4 is, for example, a p-type Si substrate (semiconductor substrate). The semiconductor heterojunction 6 is a semiconductor heterojunction in which a channel layer 8 and a barrier layer 10 are stacked. The channel layer is, for example, an undoped GaN layer. The barrier layer 10 is, for example, an undoped or n-type AlGaN layer.

  Further, the semiconductor element 2 has a gate 12 provided above the semiconductor heterojunction 6 and first and second source / drain terminals 14 a and 14 b provided on both sides of the gate 12. In addition, the semiconductor element 2 includes a first feel plate 16a provided between the first source / drain terminal 14a and the gate 12, and a second feel plate 16a provided between the second source / drain terminal 14b and the gate 12. It has a field plate 16b.

A buffer layer 18 is provided between the semiconductor heterojunction 6 and the substrate 4. The buffer layer 18 is, for example, an AlN layer. A first insulating film 20 such as SiN is provided between the barrier layer 10 and the gate 12. The gate 12 is provided on the first insulating film 20. Further, a second insulating film 22 such as a SiO ₂ film is provided on the first insulating film 20. The first FP 16 a and the second FP 16 b are provided on the second insulating film 22. Note that the gate 12 may be provided directly on the barrier layer 10 without providing the first insulating film 20. The buffer layer 18 is for increasing the crystallinity of the channel layer 8 and can be omitted.

  Contact holes 24 a and 24 b reaching the barrier layer 10 are provided in the first insulating film 20 and the second insulating film 22. The first and second source / drain terminals 14 a and 4 b have a portion provided in the contact holes 24 a and 24 b and a portion provided on the surface of the second insulating film 22.

  As shown in FIG. 1, the first and second source / drain terminals 14a and 4b are connected to the barrier layer 10 exposed at the bottoms of the contact holes 24a and 24b. The first and second source / drain terminals 14a and 4b may be connected to the barrier layer 10 which is partially thinned at the bottoms of the contact holes 24a and 24b.

  The gate 12 and the nearby heterostructure 6 (including the first insulating film 20) function as a HEMT. The first FP 16a and the nearby heterostructure 6 (including the first and second insulating films 20 and 22) also function as a HEMT. Similarly, the second FP 16b and the nearby heterostructure 6 (including the first and second insulating films 20 and 22) also function as a HEMT.

  Accordingly, as shown in FIG. 2, the equivalent circuit of the semiconductor element 2 is a series circuit of a HEMT 26 corresponding to the gate 12, a HEMT 28a corresponding to the first FP 16a, and a HEMT 28b corresponding to the second FP 16b.

  Hereinafter, the HEMT 26 corresponding to the gate 12 is referred to as a gate transistor. The HEMT 28a corresponding to the first FP 16a is referred to as a first FP transistor. The transistor 28b corresponding to the second FP 16b is referred to as a second FP transistor.

  As shown in FIG. 2, the first feel plate 16 a is connected to the second source / drain terminal 14 b by a wiring (not shown) provided on the second insulating film 22. The second feel plate 16b is connected to the first source / drain terminal 14a by a wiring (not shown) provided on the second insulating film 22.

  On the other hand, the substrate 4 is not connected to any terminal (the first and second source / drain terminals 14a and 14b, the first and second FPs 16a and 16b, and the gate 12), and an external circuit (ground is connected). Is not connected). Therefore, no voltage is applied to the substrate 4 directly from the outside of the semiconductor element 2.

  Here, the threshold value of the first and second FP transistors 28a and 28b is a negative voltage (for example, about −40V). On the other hand, the threshold value of the gate transistor 26 is, for example, a positive voltage (for example, about 1 to 3 V).

  The threshold value of each transistor 26, 28a, 28b is the boundary value (or the first or second field plate voltage) of the gate voltage (or the first or second field plate voltage) at which the semiconductor element 2 changes from the non-conductive state to the conductive state when the other transistors are conductive. Threshold). The threshold value of the semiconductor element 2 is a boundary value (threshold value) of a gate voltage at which the semiconductor element 2 changes from a non-conductive state to a conductive state when the first and second FP transistors 28a and 28b are conductive. Note that the threshold value of the gate transistor 26 is also a threshold value of the semiconductor element 2 as described later.

  Here, the gate voltage is a voltage of the gate 12 with respect to the first or second source / drain terminal 14a, 14b on the low potential side. The first field plate voltage is a voltage of the first field plate 16a with respect to the first or second source / drain terminal 14a, 14b on the low potential side. Similarly, the second field plate voltage is a voltage of the second field plate 16b with respect to the first or second source / drain terminal 14a, 14b on the low potential side.

  The semiconductor heterojunction 6 is, for example, an AlGaN / GaN heterojunction. In the AlGaN / GaN heterojunction, piezoelectric polarization is generated due to lattice strain between the AlGaN barrier layer and the GaN channel layer. Due to this piezo polarization and spontaneous polarization, a two-dimensional electron gas is generated at the interface between the AlGaN barrier layer and GaN. Of course, the AlGaN barrier layer 24 may be doped with an n-type impurity.

  The breakdown voltage of the gate transistor 26 is, for example, about 100V. The withstand voltages of the first and second FP transistors 28a and 28b are sufficiently higher than the maximum value (for example, 380 V) of the voltage applied between the first and second source / drain terminals 14a and 14b.

  Here, the breakdown voltage of the gate transistor 26 is a breakdown voltage against a potential difference between both sides of the gate 12 (potential difference in the channel layer 10). Similarly, the breakdown voltage of the first FP transistor 28a is a breakdown voltage with respect to a potential difference on both sides of the first FP 16a. The same applies to the breakdown voltage of the second FP transistor 28b.

  The difference in characteristics (threshold, breakdown voltage, etc.) between the gate transistor 12 and the first and second FP transistors 16a and 16b is that the thickness of the insulating film 20 below the gate 12 and the first and second FPs 16a and 16b are different from each other. This is due to the difference in thickness of the insulating films 20 and 22 on the side. Under the first and second FP transistors 16a and 16b, insulating films 20 and 22 thicker than the insulating film 20 under the gate 12 are provided. For this reason, the breakdown voltage of the first and second FP transistors 16a and 16b is increased.

  The semiconductor element 2 can be manufactured by, for example, metal organic vapor phase epitaxy and silicon IC (Integrated Circuit) process technology. The buffer layer 18 and the semiconductor heterojunction 6 are grown on the silicon substrate by metal organic vapor phase epitaxy, and then the first and second insulating films 20 and 22 and the gate 12 are formed using a silicon IC (Integrated Circuit) process technology. Etc. are formed. Thereafter, a wiring or the like connecting the first FP 16a and the second source / drain terminal 14b is formed on the surface of the second insulating film 22, and the semiconductor element 2 is manufactured.

(2) Operation FIG. 3 is an example of a circuit diagram illustrating the operation of the semiconductor element 2. The semiconductor element 2 shown in FIG. 3 is an equivalent circuit. 3 shows an equivalent circuit 30a (hereinafter referred to as a first circuit) connected to the first source / drain terminal 14a and an equivalent circuit connected to the second source / drain terminal 14b. 30b (hereinafter referred to as a second circuit) is shown. The first circuit 30 a and the second circuit 30 b are simplified for explaining the operation of the semiconductor element 2.

  The first circuit 30a is, for example, a storage battery. The second circuit 30b is, for example, a parallel circuit of a DC (direct-current) -DC converter and a load circuit. FIG. 3 also shows a gate drive circuit 32 that drives the gate 12 of the semiconductor element 2.

  As shown in FIG. 3, the first circuit 30a includes a first load R1, a first constant voltage source E1, and a first switch SW1. The second circuit 30b includes a second load R2, a second constant voltage source E2, and a second switch SW2.

  The first switch SW1 and the second switch SW2 are switched in conjunction with each other. For example, the first switch SW1 connects the first constant voltage source E1 to the first source / drain terminal 14a for a certain period, and the second switch SW2 connects the second load R2 to the second source / drain terminal 14b. Connect. In addition, the first switch SW1 connects the first first load R1 to the first source / drain terminal 14a for another period, and the second switch SW2 connects the second source / drain terminal 14b to the second source / drain terminal 14b. Connect the constant voltage source E2. The voltage (> 0V) of the first and second constant voltage sources E1 and E2 is, for example, 380V.

  The semiconductor element 2 operates in the first operation mode and the second operation mode. In the first operation mode, when the potential of the first source / drain terminal 14a (which is higher than the potential of the second source / drain terminal 14b) is directed from the first source / drain terminal 14a to the second source / drain terminal 14b. This is an operation mode in which a flowing current is passed or cut off.

  In the example shown in FIG. 3, in the first operation mode, the first source / drain terminal 14a is connected to the first constant voltage source E1 (> 0V), and the second source / drain terminal 14b is connected to the second load R2. Is a mode in a state of being connected to (hereinafter referred to as a first connection state).

  The second operation mode flows from the second source / drain terminal 14b toward the first source / drain terminal 14a when the potential of the second source / drain terminal 14b is higher than the potential of the first source / drain terminal 14a. This is an operation mode in which current is passed or cut off.

  In the example shown in FIG. 3, in the second operation mode, the first source / drain terminal 14a is connected to the first load R1, and the second source / drain terminal 14b is the second constant voltage source E2 (> 0V). This is a mode in a state of being connected to (hereinafter referred to as a second connection state).

  The gate drive circuit 32 drives the semiconductor element 2 in the first drive mode and the second drive mode. The first drive mode is a drive mode corresponding to the first operation mode. For example, the gate drive circuit 32 monitors the potentials of the first and second source / drain terminals 14a and 14b, and when the potential of the first source / drain terminal 14a is higher than the potential of the second source / drain terminal 14b, The semiconductor element 2 is driven in the first drive mode.

  In the first drive mode, the gate drive circuit 32 drives the semiconductor element 2 based on a first threshold potential obtained by adding the threshold of the gate transistor 26 to the potential of the second source / drain terminal 14b.

  For example, the gate drive circuit 32 applies a potential higher than a first threshold potential (hereinafter referred to as a first high-bell potential) when the semiconductor element 2 is conductive to make the semiconductor element 2 conductive. The gate drive circuit 32 applies a potential lower than the first threshold potential when the semiconductor element 2 is non-conductive (hereinafter referred to as a first low-level potential) to the gate 12 to make the semiconductor element 2 non-conductive. Let me.

  In the example illustrated in FIG. 3, the first drive mode is a drive mode in the first connection state. As described above, the first connection state is a state in which the first source / drain terminal 14a is connected to the first constant voltage source E1 and the second source / drain terminal 14b is connected to the second load R2. It is.

  In the first connection state, the potential of the second source / drain terminal 14b when the semiconductor element 2 is conductive is substantially equal to the voltage of the first constant voltage source E1. Accordingly, the first threshold potential when the semiconductor element 2 is conductive is substantially equal to the potential obtained by adding the threshold (for example, 3 V) of the gate transistor 26 to the voltage (for example, 380 V) of the first constant voltage source E1. The gate drive circuit 32 applies a first high-level potential (for example, 400 V) higher than the first threshold potential (383 V) at the time of conduction to the gate 12 to make the semiconductor element 12 conductive.

  On the other hand, the potential of the second source / drain terminal 14 b when the semiconductor element 2 is not conducting is substantially equal to the potential of the ground G. Therefore, the first threshold potential when the semiconductor element 2 is non-conductive is approximately equal to the potential obtained by adding the threshold (for example, 3 V) of the gate transistor 26 to the potential (0 V) of the ground G. The gate drive circuit 32 applies a first low-level potential (for example, 0 V) lower than the first threshold potential (3 V) at the time of non-conduction to the gate 12 to make the semiconductor element 12 non-conductive.

  The second drive mode is a drive mode corresponding to the second operation mode. For example, the gate drive circuit 32 monitors the potentials of the first and second source / drain terminals 14a and 14b, and when the potential of the second source / drain terminal 14b is higher than the potential of the first source / drain terminal 14a, The transistor 2 is driven in the second drive mode.

  In the second drive mode, the gate drive circuit 32 drives the semiconductor element 2 based on a second threshold potential obtained by adding the threshold of the gate transistor 26 to the potential of the first source / drain terminal 14a.

  For example, the gate drive circuit 32 applies a potential higher than the second threshold potential when the semiconductor element 2 is conductive (hereinafter referred to as a second high bell potential) to the gate 12 to make the semiconductor element 2 conductive. The gate drive circuit 32 applies a potential lower than the second threshold potential when the semiconductor element 2 is non-conductive (hereinafter referred to as a second low level potential) to the gate 12 to make the semiconductor element 2 non-conductive. Let me.

  In the example illustrated in FIG. 3, the second drive mode is a drive mode in the second connection state. As described above, the second connection state is a state in which the first source / drain terminal 14a is connected to the first load R1 and the second source / drain terminal 14b is connected to the second constant voltage source E2. It is.

  In the second connection state, the potential of the first source / drain terminal 14a when the semiconductor element 2 is conductive is substantially equal to the voltage of the second constant voltage source E2. Therefore, the second threshold potential when the semiconductor element 2 is conductive is approximately equal to the potential obtained by adding the threshold (eg, 3V) of the gate transistor 26 to the voltage (eg, 380V) of the second constant voltage source E2. Therefore, the gate drive circuit 32 applies a second high level potential (for example, 400 V) higher than the second threshold potential (383 V) at the time of conduction to the gate 12 to make the semiconductor element 2 conductive.

  On the other hand, the potential of the first source / drain terminal 14b when the semiconductor element 2 is non-conductive is substantially equal to the potential of the ground G. Therefore, the second threshold potential when the semiconductor element 2 is non-conductive is substantially equal to the potential obtained by adding the threshold (eg, 3 V) of the gate transistor 26 to the potential (0 V) of the ground G. Therefore, the gate drive circuit 32 applies a second low level potential (for example, 0 V) lower than the second threshold potential (3 V) at the time of non-conduction to the gate 12 to make the semiconductor element 2 non-conductive. .

  In the above example, the voltages of the first and second constant voltage sources are equal. However, the voltages of the first and second constant voltage sources may be different. The first and second high level potentials may also be different. The same applies to the first and second low level potentials.

  FIG. 4 is a table showing an example of the state of the semiconductor element 2 before and after the gate potential changes from the first high level potential to the first low level potential (for example, 0 V) in the first connection state (hereinafter, Table 1). Called). The potentials shown in Table 1 are representative values shown in parentheses in the following description. The same applies to FIG. 5 below.

  In a state where a first high-level potential (for example, 400 V) is applied to the gate 12, the semiconductor element 2 becomes conductive, and current flows from the first source / drain terminal 14a toward the second source / drain terminal 14b. Yes. Therefore, the potential of the first source / drain terminal 14a is the voltage of the first constant voltage source (for example, 380V). The potentials of the first node N1 (the node between the first FP 16a and the gate 12) and the second node (the node between the second FP 16b and the gate 12) are also substantially equal to those of the first constant voltage source. It is a voltage (for example, 380V). The potential of the second source / drain terminal 14b is also substantially the voltage of the first constant voltage source (for example, 380V).

  When a first low level potential (for example, 0 V) is applied to the gate 12 in this state, the gate transistor 26 changes from the conductive state (ON) to the non-conductive state (OFF) as shown in the fourth column of Table 1. )become. As a result, the current flowing from the first source / drain terminal 14a toward the second source / drain terminal 14b is cut off.

  Then, as shown in the seventh column of Table 1, the potential of the second source / drain terminal 14b becomes substantially the ground potential (0 V). For this reason, the difference (for example, −380 V) between the potential (for example, 0 V) of the second source / drain terminal 14 b and the potential (for example, 380 V) of the first node N <b> 1 is the threshold (for example, for example). −40V). Accordingly, as shown in the second column of Table 1, the first FP transistor 16a is changed from the conductive state to the non-conductive state.

  When the gate transistor 12 and the first FP transistor 16a are turned off, the parasitic capacitance of the first node N1 is discharged and the potential of the first node N1 is lowered. As a result, the potential difference between the second source / drain terminal 14b and the first node N1 rises to the vicinity of the threshold value (for example, −40 V) of the first FP transistor 28a.

  Then, the leakage current of the first FP transistor 28a flowing into the node 1 and the discharge current of the parasitic capacitance become approximately the same, and the potential drop of the first node N1 is stopped. At this time, as shown in the third column of Table 1, the potential of the first node N1 is substantially equal to the absolute value (for example, 40 V) of the threshold value of the first FP transistor 16a.

  On the other hand, in the first connection state, the potential of the second FP 16b connected to the first source / drain terminal 14a on the high potential side is always higher than the potential of the second source / drain terminal 14b on the low potential side. Therefore, the second FP transistor 16b remains conductive as shown in the sixth column of Table 1. Therefore, when the gate transistor 26 becomes non-conductive, the stray capacitance of the second node N2 is gradually discharged through the second load resistor R2. As a result, as shown in the fifth column of Table 1, the potential of the second node N2 drops from the potential when the gate transistor 26 is conductive (for example, approximately 380V) to the approximate ground potential (0V). To do.

  Through the process as described above, the current from the first source / drain terminal 14a to the second source / drain terminal 14b is cut off. In the above description, the semiconductor element 2 has been described so as to sequentially transition to the state shown in each column of Table 1, but actually transitions in parallel.

  As described above, the potential of the first node N1 is substantially equal to the absolute value (for example, 40 V) of the threshold value of the first FP transistor 16a. On the other hand, the potential of the second node N2 is substantially the ground potential (for example, 0 V). Therefore, the potential difference between both ends of the gate 12 is approximately the same as the absolute value of the threshold value of the first FP transistor 16a. Therefore, the insulating layer (the first insulating film 20 and the barrier layer 10) immediately below the gate 12 is not destroyed.

  FIG. 5 is a table (hereinafter referred to as Table 2) showing an example of the state of the semiconductor element before and after the gate potential changes from the first low level potential to the first high level potential in the first connection state.

  When the gate potential changes from the first low level potential (for example, 0V) to the first high level (for example, 400V), as shown in the fourth column of Table 2, the gate transistor 26 is in a non-conductive state (OFF ) To a conductive state (ON). Then, since the second FP transistor 28b is conductive, the potential difference between the first node N1 and the second source / drain terminal 14b is substantially eliminated. For this reason, the potential difference (approximately 0 V) between the first FP 16a connected to the second source / drain terminal 14b and the first node N1 becomes higher than the threshold (for example, −40 V) of the first FP transistor 28a. For this reason, the first FP transistor 28a becomes conductive as shown in the second column of Table 2.

  As a result, all the transistors included in the semiconductor element 2 become conductive, and current flows from the first source / drain terminal 14a toward the second source / drain terminal 14b. Due to this current, a voltage is generated across the second load R2, and the potential of the second source / drain terminal 14b is equal to the potential of the first source / drain terminal 14a (for example, as shown in the seventh column of Table 2). 380V) to a slightly lower potential (for example, approximately 380V). The potential difference between the first source / drain terminal 14 a and the second source / drain terminal 14 b at this time is attributed to the on-resistance of the semiconductor element 2.

  At this time, the potentials of the first and second nodes N1 and N2 also rise to a slightly lower potential (for example, approximately 380 V) than the potential of the first source / drain terminal 14a. The second FP transistor 28b remains conductive as shown in the sixth column of Table 2. This is because the potential of the first source / drain terminal 14a to which the second FP 16b is connected is higher than the second source / drain terminal 14b or substantially the same potential as the second source / drain terminal 14b. Thus, in the first connection state, the second FP transistor 28b is always conductive.

  Through the process as described above, the semiconductor element 2 becomes conductive. That is, a current from the first source / drain terminal 14 a toward the second source / drain terminal 14 b passes through the semiconductor element 2. At this time, as shown in Table 2, since there is almost no potential difference between the first node N1 and the second node N2, the insulating layer (the first insulating film 20 and the barrier layer 10) immediately below the gate 12 is not destroyed. . The above process also proceeds in parallel as in the process shown in Table 1.

  The first drive mode by the gate drive circuit 32 has been described above with reference to FIGS. As shown in FIG. 1, the semiconductor element 2 has a symmetrical structure with the gate 12 as the center. Accordingly, in the second drive mode corresponding to the second operation mode, the operation of the first FP transistor 28a and the operation of the second FP transistor 28b are interchanged. Further, the potential of the first node N1 and the potential of the second node N2 are interchanged. Similarly, the potential of the first source / drain terminal 14a and the potential of the second source / drain potential 14b are interchanged.

  Therefore, when a second low-level potential (for example, 0 V) is applied to the gate 12, the current flowing from the second source / drain terminal 14b toward the first source / drain terminal 14a is blocked by the semiconductor element 2. The On the other hand, when a second high-level potential (for example, 400 V) is applied to the gate 12, a current from the second source / drain terminal 14 b toward the first source / drain terminal 14 a passes through the semiconductor element 2.

  As described above, according to the semiconductor element 2 of the present embodiment, the direction from the first source / drain terminal 14a toward the second source / drain terminal 14b and the opposite direction without connecting another transistor. The current flow can be controlled (ON / OFF control).

  The potentials of the first and second source / drain terminals 14a and 14b are preferably 0V or positive potential. However, the potentials of the first and second source / drain terminals 14a and 14b do not necessarily have to be 0V or a positive potential. For example, the potential of the source / drain terminal on the low potential side may be lower than 0V.

  In order to operate the gate transistor 12 in the non-saturated region, a potential higher than the potential obtained by adding the threshold value of the gate transistor 12 to the potential of the source / drain terminal on the high potential side when the semiconductor element 2 is conductive is applied to the gate 12. It is preferable.

―Power MOSFET―
FIG. 6 is an example of a cross-sectional view of the power MOSFET 34. FIG. 7 is a circuit diagram of a switching circuit using the power MOSFET 34 to control the current flow in both directions.

  The power MOSFET 34 has a p-type region 38 provided on the n-type Si substrate 36 and an n-type region 40 surrounded by the p-type region 38. The n-type Si substrate 36 functions as a drain. The p-type region 38 functions as a channel layer. The n-type region 40 functions as a source.

  The power MOSFET 34 further includes an oxide film 42 provided on the n-type region 40 and a gate 44 embedded in the oxide film 42. The power MOSFET 34 includes a source electrode 45 connected to the n-type region (source) 40 and a drain electrode 46 connected to the n-type Si substrate (drain) 36. FIG. 6 also shows a path 48 of drain current flowing from the drain to the source.

  As shown in FIG. 6, in the power MOSFET, the source electrode 45 is connected not only to the n-type region (source) but also to the p-type region (channel layer) 38. Therefore, the pn junction between the n-type substrate 36 and the p-type region 38 operates as a parasitic diode 50 in which the anode (anode) is connected to the source electrode 45 and the cathode (cathode) is connected to the drain electrode 46. The reason for connecting the source electrode 45 to the p-type region (channel layer) 38 is to make the channel layer (p-type region 38) the same potential as the source (n-type region 40).

  When the source electrode 45 is at a higher potential than the drain electrode 46, current flows from the source electrode 45 to the drain electrode 46 because the current flows through the parasitic diode 50 even if the gate potential is lower than the threshold value. .

  Therefore, in order to control the current flow in both directions, a series circuit of a pair of power MOSFETs 34a and 34b in which the directions of the source S and the drain D are reversed as shown in FIG. 7 is used. The same potential is applied to the gate G1 of the first power MOSFET 34a and the gate G2 of the second power MOSFET 34b, and the first and second power MOSFETs 34a and 34 are simultaneously turned on or off.

  The forward direction of the parasitic diode 50a of the first power MOSFET 34a faces the reverse direction of the parasitic diode 50b of the second power MOSFET 34b. Therefore, when the first power MOSFET 34a and the second power MOSFET 34b are in a non-conductive state, no current flows through the first parasitic diode 50a and the second parasitic diode 50b.

  Therefore, if the circuit shown in FIG. 7 is used, the current flow can be controlled (ON / OFF control) in both directions. However, the circuit of FIG. 7 cannot be formed by one power MOSFET, but is formed by using two power MOSFETs.

-GaN-FP-HEMT-
FIG. 8 is a cross-sectional view of the GaN-FP-HEMT 52. FIG. 9 is an equivalent circuit of the GaN-FP-HEMT 52.

  The structure of the GaN-FP-HEMT 52 is similar to the semiconductor element 2 of the present embodiment. However, no field plate is provided between the gate 12 and the first source / drain terminal 14a (source).

  When the potential of the first source / drain terminal 14a (source) is higher than the potential of the second source / drain terminal 14b (drain), the first source / drain terminal 14a to which the second FP 16 is connected is the second source / drain. The potential becomes higher than that of the terminal 14b. For this reason, the second FP transistor 28b is always conductive. Therefore, the potential difference between the first source / drain terminal 14a and the second source / drain terminal 14b is applied to both ends of the gate 12 almost as it is.

  When the gate transistor 26 becomes non-conductive in such a state, a high voltage (for example, 380 V) is applied between the gate 12 and its insulating layer (the first insulating film 20 and the barrier layer 10), and the insulating layer is destroyed. Is done. For this reason, the current flow cannot be controlled by only the single GaN-FP-HEMT 52.

  On the other hand, in the semiconductor element 2 of the present embodiment, since the first FP 16a is provided between the gate 12 and the first source / drain terminal 14a, the current flow can be controlled by both.

  Incidentally, the GaN-FP-HEMT 52 is used in a state where the substrate 4 is connected to the first source / drain terminal 14a. In this state, the substrate potential is asymmetric with respect to the first and second source / drain terminals 14a and 14b. In this respect, the GaN-FP-HEMT 52 is not suitable for current control in both directions.

(3) Modified Example FIG. 10 is an equivalent circuit showing a modified example of the semiconductor element 2. The sectional view of Modification 2a is substantially the same as the sectional view of the semiconductor element 2 shown in FIG. Therefore, description of portions common to the semiconductor element 2 is omitted.

  In Modification 2a, the substrate 4 (see FIG. 1) is connected to the gate 12 as shown in FIG. The substrate 4 and the gate 12 are connected by, for example, wiring provided outside the substrate 4. Alternatively, the gate 12 and the substrate 4 are connected using a through hole provided in the semiconductor heterojunction 6.

  In Modification 2a, since the substrate 4 is connected to the gate 12, the potential of the channel layer 8 immediately below the gate is controlled not only from the gate side but also from the substrate side. For this reason, the semiconductor element 2a is easily conductive and non-conductive. That is, the conduction control of the semiconductor element 2a is facilitated.

  FIG. 11 is an equivalent circuit of another modification 2b of the present embodiment. The sectional view of Modification 2b is substantially the same as the sectional view of the semiconductor element 2 shown in FIG. Therefore, description of portions common to the semiconductor element 2 is omitted.

  As shown in FIG. 11, the substrate 4 of the modified example 2b has a potential lower than the potential applied to the first and second source / drain terminals 14a and 14b at least during the non-conducting period of the semiconductor element 2b. Applied. The potential applied to the substrate 4 is supplied by, for example, an external power source 56 connected to the substrate terminal 54.

  For example, as in FIG. 3, when circuits 30a and 30b having constant voltage sources E1 and E2 and loads R1 and R2 are connected to both ends of the modified example 2b, the connection to the first and second source / drain terminals 14a and 14b is performed. The applied voltage is 0V or an electromotive force (> 0V) of the constant voltage sources E1 and E2. Therefore, a potential lower than 0 V (for example, about −1 to −10 V) is applied to the substrate 4 at least during the period in which the semiconductor element 2 b is non-conductive.

  As described above, the potential of the channel layer 8 immediately below the gate is controlled not only from the gate side but also from the substrate side. Accordingly, if the substrate 4 is in a floating state and the potential is not controlled, the substrate potential may rise and the semiconductor element 2b may be conducted.

  However, according to the present embodiment, a potential lower than that of the first and second source / drain terminals 14a and 14b is applied to the substrate 4. As a result, the threshold value of the gate transistor 26 is increased, and the operation of the semiconductor element 2b is stabilized.

  In the above example, the threshold value of the gate transistor 26 is a positive voltage. However, the threshold value of the gate transistor 26 may be 0 V or less. In the above example, a voltage of 380 V is applied between the first source / drain terminal 14a and the second source / drain terminal 14b. However, another voltage (for example, 600 V) may be applied between the first source / drain terminal 14a and the second source / drain terminal 14b.

(Embodiment 2)
FIG. 12 is an equivalent circuit of the semiconductor element 2c of the present embodiment. The cross-sectional view of the semiconductor element 2c is substantially the same as the cross-sectional view of the semiconductor element 2 of the first embodiment shown in FIG. Therefore, description of portions common to the semiconductor element 2 of the first embodiment is omitted.

  As shown in FIG. 12, the first and second FPs 16 a and 16 b of the semiconductor element 2 c are connected to the gate 12. The first and second FPs 16a and 16b are connected to the gate 12 by, for example, wiring (not shown) provided on the second insulating film 22 (see FIG. 1). The threshold value of the gate transistor 26 is, for example, 0 V or a positive voltage (for example, 1 to 3 V). The threshold values of the first and second FP transistors 28a and 28b are negative voltages (for example, −40V). Thus, the threshold value of the gate transistor 26 is higher than the threshold values of the first and second FPs 28a and 28b.

  The semiconductor element 2c is driven by the driving method described in the first embodiment. For example, the high level potential and the low level potential described in Embodiment 1 are applied to the gate 12.

  The potential applied to the gate 12 is also applied to the first and second FPs 16a and 16b. Incidentally, the threshold value of the gate transistor 26 is higher than that of the first and second FP transistors 28a and 28b as described above. Therefore, when a high level potential is applied to the gate 12, the first and second FP transistors 28 a and 28 b are turned on together with the gate transistor 12. At this time, the semiconductor element 2c can pass a current in both directions.

  On the other hand, when a low level potential (for example, about 0 V) is applied to the gate 12, the gate transistor 26 becomes non-conductive. Immediately thereafter, the potential of the node (for example, the node N1) between the high potential side FP transistor (for example, the first FP transistor 28a) and the gate transistor 12 is substantially equal to the potential of the high potential side source / drain terminal due to the parasitic capacitance. It is kept in. For this reason, the difference between the low level potential (for example, 0 V) applied to the gate 12 and the node potential (for example, 380 V) becomes lower than the threshold value (for example, −40 V) of the FP transistor on the high potential side. Accordingly, the FP transistor on the high potential side becomes non-conductive.

  When the gate transistor 12 and the FP transistor on the high potential side are turned off, the parasitic capacitance of the node is discharged, and the potential of the node is lowered. When the potential of the node is lowered to the vicinity of the potential (for example, about 40 V) obtained by adding the absolute value of the threshold value (for example, about −40 V) of the high potential side FP transistor to the low level potential, the high potential side FP transistor The leakage current increases. For this reason, the potential drop at the node stops.

  The potential of the node at this time is about a potential (for example, about 40 V) obtained by adding an absolute value of a threshold value (for example, about −40 V) of the FP transistor on the high potential side to a low level potential (for example, 0 V). Therefore, no high voltage is generated at both ends of the gate 12, and the first gate insulating film 20 and the barrier layer 10 are not destroyed.

  In this way, the semiconductor element 2c can cut off the current regardless of which of the first and second source / drain terminals 14a and 14b is at a high potential. In other words, the semiconductor element 2c can cut off current in both directions.

  As described above, the semiconductor element 2 passes or blocks current in both directions. That is, the semiconductor element 2c has the first and second operation modes described in the first embodiment.

  In the above example, the threshold value of the gate transistor 26 is 0 V or a positive voltage. However, the threshold value of the gate transistor 26 may be a negative voltage. The substrate 4 of the semiconductor element 2c may be connected to the gate 12 as in the modification of the first embodiment. Further, as in another modification of the first embodiment, the potential applied to the first and second source / drain terminals 14a and 14b during the period when the semiconductor element 2c is at least non-conductive is applied to the substrate 4. A lower potential may be applied.

  The semiconductor heterojunction 6 of the first and second embodiments is a GaN / AlGaN heterojunction. However, the semiconductor heterojunction 6 may be another semiconductor heterojunction. For example, the semiconductor heterojunction 6 may be a GaAs / AlGaAs heterojunction.

  Regarding the above first and second embodiments, the following additional notes are disclosed.

(Appendix 1)
A semiconductor heterojunction in which a channel layer and a barrier layer are stacked;
A gate provided above the semiconductor heterojunction;
First and second source / drain terminals provided on both sides of the gate;
A first feel plate provided between the first source / drain terminal and the gate;
A semiconductor element, comprising: a second field plate provided between the second source / drain terminal and the gate.

(Appendix 2)
In the semiconductor element according to attachment 1,
The first field plate is connected to the second source / drain terminal;
The semiconductor element, wherein the second field plate is connected to the first source / drain terminal.

(Appendix 3)
In the semiconductor element according to appendix 1 or 2,
Having a substrate provided with the semiconductor heterojunction;
The semiconductor element, wherein the substrate is connected to the gate.

(Appendix 4)
In the semiconductor element according to any one of appendices 1 to 3,
Having a substrate provided with the semiconductor heterojunction;
A potential lower than a potential applied to the first and second source / drain terminals is applied to the substrate during at least the period when the semiconductor element is non-conductive.

(Appendix 5)
In the semiconductor element according to any one of appendices 1 to 4,
When the potential of the first source / drain terminal is higher than the potential of the second source / drain terminal, the current flowing from the first source / drain terminal toward the second source / drain terminal is allowed to pass or cut off. A first operating mode;
When the potential of the second source / drain terminal is higher than the potential of the first source / drain terminal, the current flowing from the second source / drain terminal toward the first source / drain terminal is allowed to pass or cut off. A semiconductor element having a second operation mode.

(Appendix 6)
In the semiconductor element according to any one of appendices 1 to 5,
The threshold value of the transistor corresponding to the first field plate and the threshold value of the transistor corresponding to the second field plate are negative voltages.

(Appendix 7)
In the semiconductor device according to any one of appendices 1 to 6,
The channel layer is an AlGaN layer;
The barrier element is a GaN semiconductor element.

(Appendix 8)
A gate provided above a semiconductor heterojunction; first and second source / drain terminals provided on both sides of the gate; and a first provided between the first source / drain terminal and the gate. A semiconductor device having a field plate, a second field plate provided between the second source / drain terminal and the gate,
When the potential of the first source / drain terminal is higher than the potential of the second source / drain terminal, it is based on the first threshold potential obtained by adding the threshold of the semiconductor element to the potential of the second source / drain terminal. A first drive mode for driving the semiconductor element;
When the potential of the second source / drain terminal is higher than the potential of the first source / drain terminal, it is based on a second threshold potential obtained by adding the threshold of the semiconductor element to the potential of the first source / drain terminal. And a second driving mode for driving the semiconductor element.

(Appendix 9)
In the semiconductor element driving method according to attachment 8,
In the first drive mode, a potential higher than the first threshold potential when the semiconductor element is conductive is applied to the gate to cause the semiconductor element to conduct, and the first element when the semiconductor element is non-conductive is used. Applying a potential lower than a threshold potential to the gate to make the semiconductor element non-conductive;
In the second drive mode, a potential higher than the second threshold potential when the semiconductor element is conductive is applied to the gate to make the semiconductor element conductive, and the second element when the semiconductor element is non-conductive is used. A driving method of a semiconductor element, wherein a potential lower than a threshold potential is applied to the gate to make the semiconductor element non-conductive.

(Appendix 10)
In the semiconductor element according to attachment 1,
The first field plate is connected to the gate;
The second field plate is connected to the gate;
A featured semiconductor element.

(Appendix 11)
In the semiconductor element according to attachment 10,
Having a substrate provided with the semiconductor heterojunction;
The semiconductor element, wherein the substrate is connected to the gate.

(Appendix 12)
In the semiconductor element according to attachment 10 or 11,
Having a substrate provided with the semiconductor heterojunction;
A potential lower than a potential applied to the first and second source / drain terminals is applied to the substrate during at least the period when the semiconductor element is non-conductive.

(Appendix 13)
In the semiconductor element according to any one of appendices 10 to 12,
When the potential of the first source / drain terminal is higher than the potential of the second source / drain terminal, the current flowing from the first source / drain terminal toward the second source / drain terminal is allowed to pass or cut off. A first operating mode;
When the potential of the second source / drain terminal is higher than the potential of the first source / drain terminal, the current flowing from the second source / drain terminal toward the first source / drain terminal is allowed to pass or cut off. A semiconductor element having a second operation mode.

(Appendix 14)
The semiconductor element according to any one of appendices 10 to 13,
The threshold value of the transistor corresponding to the first field plate and the threshold value of the transistor corresponding to the second field plate are negative voltages.

(Appendix 15)
The semiconductor element according to any one of appendices 10 to 13,
The channel layer is an AlGaN layer;
The barrier element is a GaN semiconductor element.

2, 2a, 2b, 2c ... semiconductor element 4 ... substrate 6 ... semiconductor heterojunction 8 ... channel layer 10 ... barrier layer 12 ... gate 14a ... first source Drain terminal 14b ... Second source / drain terminal 16a ... First feel plate 16b ... Second feel plate

Claims (6)

A semiconductor heterojunction in which a channel layer and a barrier layer are stacked;
A gate provided above the semiconductor heterojunction;
First and second source / drain terminals provided on both sides of the gate;
A first field plate provided above the semiconductor heterojunction and provided between the first source / drain terminal and the gate;
The semiconductor to be provided above the heterojunction, and have a second field plate disposed between the second source drain terminal and the gate,
The first field plate is connected to the second source / drain terminal;
The semiconductor element, wherein the second field plate is connected to the first source / drain terminal . The semiconductor device according to claim 1 ,
Having a substrate provided with the semiconductor heterojunction;
The semiconductor device, wherein the substrate is connected to the gate. The semiconductor device according to claim 1 or 2 ,
Having a substrate provided with the semiconductor heterojunction;
The semiconductor element, wherein a potential lower than a potential applied to the first and second source / drain terminals is applied to the substrate during a period when the semiconductor element is at least non-conductive. The semiconductor device according to any one of claims 1 to 3 ,
When the potential of the first source / drain terminal is higher than the potential of the second source / drain terminal, the current flowing from the first source / drain terminal toward the second source / drain terminal is allowed to pass or cut off. A first operating mode;
When the potential of the second source / drain terminal is higher than the potential of the first source / drain terminal, the current flowing from the second source / drain terminal toward the first source / drain terminal is allowed to pass or cut off. A semiconductor element having a second operation mode. A semiconductor heterojunction in which a channel layer and a barrier layer are stacked;
A gate provided above the semiconductor heterojunction;
First and second source / drain terminals provided on both sides of the gate;
A first field plate provided above the semiconductor heterojunction and provided between the first source / drain terminal and the gate;
The semiconductor to be provided above the heterojunction, and have a second field plate disposed between the second source drain terminal and the gate,
The first field plate is connected to the gate;
The second field plate is connected to the gate ;
Having a substrate provided with the semiconductor heterojunction;
That the substrate is connected to the gate;

A featured semiconductor element. The semiconductor device according to claim 5 ,
Having a substrate provided with the semiconductor heterojunction;
The semiconductor element, wherein a potential lower than a potential applied to the first and second source / drain terminals is applied to the substrate during a period when the semiconductor element is at least non-conductive.

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