JP2007073815A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device improved in a distortion characteristic in terms of semiconductor devices to be used in high frequency switching circuits. <P>SOLUTION: In the high frequency switching circuit, a high frequency signal via either a source electrode 102 or a drain electrode 103 in a multi-gate FET 100 is inputted and outputted via the other electrode, and controls high frequency signal passing or blocking is controlled by the electric potentials of control terminals connected to multiple gate electrodes 107, 108 and 109. The length of a source side roof in a first gate 107 nearest to the source electrode 102 and that of a drain side pent roof in a third gate 109 nearest to the drain electrode 103 are longer than that of the other pent roof in the gate electrode and they determine an additional capacity. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device used in a high frequency switch circuit.

  Along with the reduction in power consumption of mobile communication devices that transmit and receive radio frequency (RF) signals, the insertion loss of the radio frequency switch circuit provided between the antenna and the transmission circuit or between the antenna and the reception circuit is reduced, and the radio frequency switch circuit There is a need to reduce the power consumption of itself. For this reason, it is desired that the switching element has a small insertion loss and does not require a DC bias current unlike a diode. For example, a high-performance FET (Field Effect Transistor) is used as such a switching element. This is because the high-frequency switch circuit composed of FETs consumes almost no power.

  However, in mobile communication, especially in high-speed data communication such as cellular phones and wireless LANs, signals such as CDMA (Code Division Multi-Access) and OFDM (Orthogonal Frequency Division Multiplexing) are used. In addition to this, low distortion is required more than ever. Therefore, in order to improve the distortion characteristics, in order to obtain the maximum allowable power in the low voltage operation, the gate electrode is configured in a plurality of stages, and between the first stage gate electrode and the source electrode as viewed from the source electrode, It has been proposed to install an additional capacitor (Cadd) between the gate electrode and the drain electrode (see, for example, Patent Document 1).

However, in the FET constituting the high-frequency switch circuit, as described above, in order to directly install the additional capacitance between the first-stage gate electrode and the source electrode and between the final-stage gate electrode and the drain electrode, Therefore, it is necessary to increase the width of the power supply point of the drain electrode, which increases the element area and further increases the manufacturing cost.
Japanese Patent Laid-Open No. 11-136111

  An object of the present invention is to provide a semiconductor device having improved distortion characteristics.

  In the semiconductor device according to one embodiment of the present invention, a high-frequency signal is input from one of a source electrode and a drain electrode of a plurality of field effect transistors connected in series and output from the other, and the plurality of field effects In a semiconductor device for a high-frequency switch circuit that controls the passage and shielding of the high-frequency signal by the potential of a control terminal connected to the gate electrode of the transistor through a resistor, the gate electrode and the ohmic electrode of the first stage field effect transistor And the parasitic capacitance density between the gate electrode and the ohmic electrode of the field effect transistor in the final stage is larger than the parasitic capacitance density between the other gate electrode and the ohmic electrode.

  A semiconductor device according to another aspect of the present invention includes a high-frequency signal that is input from one of a source electrode and a drain electrode of a field effect transistor and output from the other, and is provided between the source electrode and the drain electrode. In a semiconductor device for a high-frequency switch circuit that controls passage and shielding of the high-frequency signal by a potential of a control terminal connected to each of a plurality of gate electrodes via a resistor, the gate electrode closest to the ohmic electrode and the ohmic electrode The parasitic capacitance density between the first and second gate electrodes is larger than the parasitic capacitance density between the other gate electrode and the node between the gate electrodes.

  According to the semiconductor device of one embodiment of the present invention, distortion characteristics can be improved.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In addition, although embodiment of this invention is described based on drawing below, those drawings are provided for illustration and this invention is not limited to those drawings.

  FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of the semiconductor device shown in FIG. The semiconductor device shown in these drawings includes an FET 100 having a triple-gate structure. The FET 100 may be either a HEMT (High Electron Mobility Transistor) or a MESFET (Metal Semiconductor Field Effect Transistor). The FET 100 includes a source electrode 102 and a drain electrode 103 that are provided on a semiconductor substrate 101 such as a GaAs substrate at a predetermined distance (first recess region).

  The source electrode 102 and the drain electrode 103 are formed on the semiconductor substrate 101 via the first and second ohmic contact layers 104 and 105, respectively, and constitute an ohmic electrode. Between the source electrode 102 and the drain electrode 103, a first insulating film 106 is provided on the semiconductor substrate 101 via ohmic contact layers 104 and 105. The first insulating film 106 includes a plurality of first insulating films 106. The gate formation region (second recess region) is formed through. A plurality of gate electrodes, that is, first, second, and third gate electrodes 107 are interposed between the source electrode 102 and the drain electrode 103 through the gate formation region formed in the first insulating film 106. 108 and 109 are provided.

  Each of the gate electrodes 107, 108, and 109 described above has a T-shaped cross section (T gate) including an eaves portion disposed on the first insulating film 106. That is, each gate electrode 106, 107, 108 is a first portion (corresponding to a T-shaped vertical bar) filled in a gate formation region (penetrating portion) formed so as to penetrate the first insulating film 106. And a second portion (a portion corresponding to a T-shaped horizontal bar) formed continuously on the first portion, and the second portion is on the first insulating film 106. The eaves part is provided. Note that the second gate electrode 108 may be a straight gate.

  The eaves portion of each of the gate electrodes 107, 108, 109, particularly the eaves portion of the first and third gate electrodes 107, 109, is connected to the ohmic contact layers 104, 105 connected to the source electrode 102 or the gate electrode 103 and the first The insulating film 106 is opposed to each other. Such an eaves portion forms a capacitance according to its length (the length of the portion disposed on the first insulating film 106) or the like. A second insulating film 110 is formed on the first, second and third gate electrodes 107, 108 and 109. Furthermore, a wiring metal 111 is formed on the source electrode 102 and the gate electrode 103, respectively.

  Each of these components constitutes a FET 100 for a high-frequency switch circuit, that is, a triple-gate FET 100 used for switching of the high-frequency circuit. Although the triple gate structure FET 100 is shown here, the number of gates is not limited to this, and for example, a dual gate, a quadruple gate, a quintuple gate. It is possible to use FETs having a multi-gate structure such as.

  Of the above-described gate electrodes 107, 108, and 109, the length (wsg1) of the first gate electrode 107 eaves portion closest to the source electrode 102 and the third gate electrode closest to the drain electrode 103 109, the length (wdg3) of the drain electrode 103 side eaves portion is the length (w) of the other eaves portion, that is, the length (w) of the elongate portion of the first gate electrode 107 on the drain electrode 103 side, The length (w) of each eaves portion of the gate electrode 108 is longer than the length (w) of the eaves portion on the source electrode 102 side of the third gate electrode 109.

  The capacitance (Cgs1) between the source electrode 102 and the first gate electrode 107 is between the first gate electrode 107 and the first node 112 depending on the shape of the source side eaves portion of the first gate electrode 107. The capacitance (Cgd1), the capacitance (Cgs2) between the first node 112 and the second gate electrode 108, the capacitance (Cgd2) between the second gate electrode 108 and the second node 113, the second node 113 and the second node 113 3 is larger than the capacity (Cgs3) between the three gate electrodes 109.

  Similarly, the capacitance (Cgd3) between the drain electrode 102 and the third gate electrode 109 is between the first gate electrode 107 and the first node 112 depending on the shape of the drain side eaves portion of the third gate electrode 109. The capacitance (Cgd1), the capacitance (Cgs2) between the first node 112 and the second gate electrode 108, the capacitance (Cgd2) between the second gate electrode 108 and the second node 113, the second node 113 and the second node 113 3 is larger than the capacity (Cgs3) between the three gate electrodes 109.

Calculate for each of the capacities mentioned above. A parallel plate model is assumed for the capacitance between the eaves of the gate electrodes 107, 108, 109 and the ohmic contact layers (104, 105). The first insulating film 106 is made of SiO ₂ , and εr = 4 and thickness = 0.15 μm. In the case of a normal T gate (w = 0.1 μm), Cgd1 = Cgs2 = Cgd2 = Cgs3 = 0.024 pF / mm, whereas in the case of wsg1 = wdg3 = 1.0 μm, Cgs1 = Cgd3 = 0.236 pF / mm.

  FIG. 3 shows a through-type high-frequency SPDT switch circuit using the FET 100. In this circuit, the RF signal input to P2 or P3 is transmitted through P1 or P2 through the RF signal of either P2 or P3 according to the potentials of Vc1 and Vc2, and the other signal is cut off. Specifically, FETs 100 having a pinch-off voltage Vp of about -1 V are prepared as T1 and T2, and control terminals Vc1 and Vc2 are connected to the gate electrodes of the FETs 100 (T1 and T2) via gate additional resistors Rgg.

  When the potential of the control terminal Vc1 is set to 0 V or higher with respect to the potentials of P1, P2, and P3, the FET 100 as T1 is turned on, and when it is set to −3 V, the FET 100 is turned off. The same applies to T2. The FET 100 shown in FIG. 2 can be represented by an on-resistance (Ron) in the on state (transmission state), and is represented by a cutoff capacitance (Coff) and a capacitance due to the eaves portion of the gate electrode in the off state (cut-off state). be able to. FIG. 4 shows an equivalent circuit diagram when T1 is turned on and T2 is turned off.

  In the circuit diagram of FIG. 3, power characteristics were evaluated at a frequency of 6 GHz. The input power (Pin) in which the second harmonic (2fo) and third harmonic (3fo), which are distortion indicators, exceed -75dBc, was 29.2dBm when using a normal FET. In this embodiment, it was 30.8 dBm. Thus, the source side eaves part length (wsg1) of the first gate electrode 107 closest to the source electrode 102 and the drain side eaves part length (wdg3) of the third gate electrode 109 closest to the drain electrode 103 are set. By making the capacity longer than the other eaves part length (w), it becomes possible to improve the distortion characteristics of the high-frequency switch circuit without causing an increase in device area or an increase in manufacturing cost based thereon. .

  Next, the length of the eaves portion of the gate electrode having a T shape will be described. The eaves length of a general gate electrode is usually 0 to 0.3 μm, although it depends on the alignment accuracy of the stepper. In the case of a straight gate, the eaves length is 0 μm. Cgd1 = Cgs2 = Cgd2 = Cgs3 = 0.072 pF / mm when the eaves part length w is 0.3 μm, whereas Cgs1 = Cgd3 = 0.118 pF / mm when wsg1 and wdg3 are 0.5 μm. In the power evaluation result in this case, the input power (Pin) in which the second harmonic (2fo) and the third harmonic (3fo), which are distortion indices, exceed −75 dBc was 29.6 dBm. From this, it can be seen that it is effective to set the length of the eaves portion close to the source electrode and the drain electrode (ohmic electrode) to 0.5 μm or more. This eaves portion length can be increased by increasing the source-gate distance, but in this case, Ron increases and insertion loss deteriorates.

  In addition, when only the length of one eaves part of the gate electrode closest to the source electrode and the drain electrode is made longer, the third harmonic (3fo) is deteriorated and distorted compared to when the eaves part is all equal. The input power (Pin) at which the second harmonic (2fo) and the third harmonic (3fo), which are indicators of the above, exceed -75 dBc was 28.5 dBm. From this, it can be seen that it is necessary to increase both the lengths of the eaves of the gate electrode closest to the source electrode and the drain electrode (ohmic electrode).

  In this embodiment, the triple-gate FET 100 is shown. However, even in an FET having a multi-gate structure such as a dual-gate, quadruple-gate, and quintuple-gate. Similar effects can be obtained. In a FET having a dual gate structure, the length of the eaves on the side of the source and drain electrodes of each gate electrode may be made longer than the length of the other eaves. Further, it goes without saying that a shunt type switch circuit, a resonance type switch circuit, and a multi-port switch circuit (SPnT) have the same effect. Moreover, although HEMT was used in this embodiment, it cannot be overemphasized that even if it uses MESFET, there exists the same effect.

  Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 5 is a sectional view showing the configuration of the semiconductor device according to the second embodiment, and FIG. 6 is an equivalent circuit diagram of the semiconductor device shown in FIG. The semiconductor device shown in these drawings includes an FET 100 having a triple-gate structure, as in the first embodiment. The FET 100 may be either HEMT or MESFET, but here it is assumed to be HEMT. The same parts as those in the first embodiment are denoted by the same reference numerals, and a part of the description is omitted.

  The FET 100 according to the second embodiment includes an eaves length (wsg1) of the first gate electrode 107 closest to the source electrode 102 on the source electrode 102 side and a drain of the third gate electrode 109 closest to the drain electrode 103. In addition to the eaves part length (wdg3) on the electrode 103 side being longer than the other eaves part lengths (w), the source electrode 102 or the drain electrode 103 is provided on the first and third gate electrodes 107 and 109. The wiring metal 111 connected to each other is disposed via the second insulating film 110.

  Accordingly, the capacitance (Cgs1) between the source electrode 102 and the first gate electrode 107 is the capacitance (Cgd1) between the first gate electrode 107 and the first node 112, and the first node 112 and the second gate electrode. A capacitance between the second gate electrode 108 and the second node 113 (Cgd2), a capacitance between the second node 113 and the third gate electrode 109 (Cgs3), and The capacitance (Cgs1a) between one gate electrode 107 and the wiring metal 111 is also connected in parallel. It should be noted that specific conditions such as the source side eaves part length (wsg1) of the first gate electrode 107 are preferably the same as those in the first embodiment.

  Similarly, the capacitance (Cgd3) between the drain electrode 102 and the third gate electrode 109 is the capacitance (Cgd1) between the first gate electrode 107 and the first node 112, and the first node 112 and the second gate. Larger than the capacitance (Cgs2) between the electrodes 108, the capacitance (Cgd2) between the second gate electrode 108 and the second node 113, and the capacitance (Cgs3) between the second node 113 and the third gate electrode 109; A capacitance (Cgd3a) between the third gate electrode 109 and the wiring metal 111 is also connected in parallel. Note that specific conditions such as the drain side eaves portion length (wdg3) of the third gate electrode 109 are preferably the same as those in the first embodiment.

Calculate for each of the capacities mentioned above. A parallel plate model is assumed for the capacitance between the eaves of the gate electrodes 107, 108 and 109 and the ohmic contact layer (not shown in FIG. 5) and the capacitance between the gate electrodes 107 and 109 and the wiring metal 111. To do. The gate length is 0.5 μm, the first insulating film 106 is SiO ₂ , εr = 4, thickness = 0.15 μm, the second insulating film 110 is a SiN film, εr = 7, and thickness = 0.20 μm. In a normal T gate (w = 0.1 μm), Cgd1 = Cgs2 = Cgd2 = Cgs3 = 0.024 pF / mm. On the other hand, when wsg1 = wdg3 = 1.0 μm, Cgs1 = Cgd3 = 0.236 pF / mm. Further, since the gate head length (Lh1) of the first and third gate electrodes 107 and 109 is Lh1 = 1.0 + 0.5 + 0.1 = 1.6 μm, Cgs1a = Cgd3a = 0.774 pF / mm.

  The FET of this embodiment is applied to the through-type high-frequency SPDT switch circuit shown in FIG. The configuration and operation of the switch circuit are as described above. Further, the FET shown in FIG. 6 can be represented by an on-resistance (Ron) in the on state (transmission state), and the cutoff capacitance (Coff) and the gate electrode length in the off state (cut-off state), as in FIG. It can be expressed by the capacitance between the portion and the capacitance between the wiring metal on the gate electrode. FIG. 7 shows an equivalent circuit when T1 is turned on and T2 is turned off.

  In the circuit diagram of FIG. 3, power characteristics were evaluated at a frequency of 6 GHz. The input power (Pin) in which the second harmonic (2fo) and third harmonic (3fo), which are distortion indicators, exceed -75dBc, was 29.2dBm when using a normal FET. In this embodiment, it was 31.5 dBm. Thus, the source side eaves part length (wsg1) of the first gate electrode 107 closest to the source electrode 102 and the drain side eaves part length (wdg3) of the third gate electrode 109 closest to the drain electrode 103 are set. In addition to increasing the length, by adding capacitance between the gate electrodes 107 and 109 and the wiring metal 111, it is possible to further improve the distortion characteristics of the high-frequency switch circuit. Moreover, although HEMT was used in this embodiment, it cannot be overemphasized that even if it uses MESFET, there exists the same effect.

  Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 8 and 9 are cross-sectional views respectively showing the configuration of the FET used in the semiconductor device according to the third embodiment, FIGS. 10 and 11 are equivalent circuit diagrams thereof, and FIG. 12 is an FET shown in FIGS. FIG. 14 is a circuit diagram showing a switch circuit configured by connecting a plurality of FETs shown in FIG. 13 in series. A multi-FET switch circuit is configured by stacking FETs (single-gate FETs). In this embodiment, a switch circuit having a three-stage stack structure will be described. The FET used here may be either HEMT or MESFET, but here it is assumed to be HEMT.

  8 and 10 show the first FET 201 arranged on the source electrode side, and FIGS. 9 and 11 show the second FET 202 arranged on the drain electrode side. FIG. 13 shows a third FET 203 arranged between the first and second FETs 201 and 202. The basic structure of the first, second, and third FETs 201, 202, and 203 is the same as that of the FET 100 of the first embodiment except that the first, second, and third FETs 201, 202, and 203 are single gates. 102 and the gate electrode 103, and the gate electrodes 211, 221, and 231 formed in a T shape by the first insulating film 106 formed through the ohmic contact layers 104 and 105 therebetween.

  In the first FET 201 shown in FIG. 8, the eaves part length (wsg1) on the source electrode 102 side of the gate electrode 211 is longer than the eaves part length (w) on the drain electrode 103 side. Accordingly, the capacitance (Cgs1) between the source electrode 102 and the gate electrode 211 is larger than the capacitance (Cgd1) between the gate electrode 211 and the drain electrode 103. The second FET 202 shown in FIG. 9 is symmetric with respect to FIG. 8, and the eaves part length (wdg1) on the drain electrode 103 side of the gate electrode 221 is longer than the eaves part length (w) on the source electrode 102 side. Yes. Therefore, the capacitance (Cgd2) between the drain electrode 103 and the gate electrode 221 is larger than the capacitance (Cgs2) between the gate electrode 221 and the source electrode 102. Note that the third FET 203 shown in FIG. 13 has a normal T gate 231 (the length of the eaves portion is w).

Calculate for each of the capacities mentioned above. In FIG. 11, since Cgd2 = Cgs1 and Cgs2 = Cgd1, the respective capacitors in FIG. 10 are shown here, and FIG. 11 is omitted. A parallel plate model is assumed for the capacitance between the eaves portion of the gate electrode 211 and the ohmic contact layers (104, 105). The first insulating film 106 is made of SiO ₂ , and εr = 4 and thickness = 0.15 μm. In contrast to Cgd1 (= Cgs2) = 0.024 pF / mm in the case of a normal T gate (w = 0.1 μm), Cgs1 (= Cgd2) = 0.236 pF / mm in the case of wsg1 (= wdg1) = 1.0 μm.

  FIG. 12 shows a through FET SPDT switch circuit having a multi-FET structure in which the first FET 201 shown in FIG. 8, the second FET 202 shown in FIG. 9, and the third FET 203 shown in FIG. 13 are stacked in three stages. In FIG. 12, the first FET 201 shown in FIG. 8 is used for the first stage Tr1 and Tr4, and the second stage shown in FIG. 9 is used for the final stage Tr3 and Tr6. The third FET 203 shown in FIG. 13 is used as the intermediate Tr2 and Tr5.

  In the through SPDT switch circuit shown in FIG. 12, Tr1, Tr2 and Tr3 are connected in series, and each of these gate electrodes is connected to the control terminal Vc1 via a gate additional resistor Rgg. The same applies to Tr4, Tr5 and Tr6, which are connected in series, and each gate electrode is connected to the control terminal Vc2 via a gate additional resistor Rgg. Rd is used to make the drain and source potentials of the FETs the same, and is a resistance of about 10 kΩ.

  The through SPDT switch circuit shown in FIG. 12 is a circuit that transmits the RF signal input to P2 or P3 to the P1 through the RF signal of either P2 or P3 by the potential of Vc1 or Vc2, and cuts off the other signal. It is. Specifically, when a FET having a pinch-off voltage Vp of about -1V is prepared as Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, and the potential of Vc1 is set to 0 V or more with respect to the potentials of P1, P2, P3. Tr1, Tr2, and Tr3 are in the on state, and Tr4, Tr5, and Tr6 are in the off state when set to -3V. In FIG. 12, each transistor Tr can be represented by an on-resistance (Ron) in the on state (transmission state), and is represented by a cutoff capacitance (Coff) and a capacitance due to the eaves portion of the gate electrode in the off state (cut-off state). be able to. FIG. 14 shows an equivalent circuit when Tr1 to Tr3 are turned on and Tr4 to Tr6 are turned off.

  In the circuit diagram of FIG. 12, power characteristics were evaluated at a frequency of 6 GHz. The input power (Pin) in which the second harmonic (2fo) and third harmonic (3fo), which are distortion indicators, exceed -75dBc, was 30.3dBm when using a normal FET. On the other hand, it was 31.2 dBm in this embodiment. In this way, the source side eaves part length (wsg1) of the gate electrode 211 of the first stage FET 201 and the drain side eaves part length (wdg1) of the gate electrode 221 of the final stage FET 202 in the multi-transistor structure are set to the other eaves part length (w). The distortion characteristics of the high-frequency switch circuit can be improved by increasing the capacity by increasing the length.

  Next, the length of the eaves portion of the T gate will be described. The length of the eaves portion of a normal T gate is 0 to 0.3 μm as described above. Cgd1 = Cgd2 = 0.118 pF / mm when wsg1 = wdg2 = 0.5 μm, whereas Cgd1 = Cgs3 = Cgd3 = Cgs2 = 0.072 pF / mm when w = 0.3 μm. In the power evaluation result in this case, the input power (Pin) at which the second harmonic (2fo) and the third harmonic (3fo), which are distortion indicators, exceed −75 dBc was 30.8 dBm. From this, it can be seen that it is effective to set the length of the eaves portion near the source electrode or drain electrode (ohmic electrode) of the gate electrodes 211 and 221 of the first-stage and final-stage FETs 201 and 202 to 0.5 μm or more. This eaves portion length can be increased by increasing the source-gate distance, but in this case, Ron increases and insertion loss deteriorates.

  Further, when only one of the source side eaves part length of the gate electrode 211 of the first stage FET 201 and the drain side eaves part length of the gate electrode 221 of the final stage FET 202 is lengthened, it is three times as long as the eaves part is all equal. The harmonic wave (3fo) deteriorated, and the input power (Pin) at which the second harmonic wave (2fo) and third harmonic wave (3fo), which are indicators of distortion, exceeded -75 dBc was 29.5 dBm. From this, it can be seen that it is necessary to increase both the length of the source side eaves portion and the length of the drain side eaves portion of the gate electrodes 211 and 221 of the FETs 201 and 202 in the first stage and the final stage.

  In this embodiment, an example in which three stages of single-gate FETs are stacked has been shown. However, when two or more FETs are stacked, the source side eaves portion of the gate electrodes of the first and last stage FETs through which high frequency is transmitted. The same effect can be obtained by lengthening the length and drain side eaves part length. Further, it goes without saying that a shunt type switch circuit, a resonance type switch circuit, and a multi-port switch circuit (SPnT) have the same effect. Moreover, although HEMT was used in this embodiment, it cannot be overemphasized that even if it uses MESFET, there exists the same effect.

  Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 15 and 17 show the first FET 201 arranged on the source electrode side, and FIGS. 16 and 18 show the second FET 202 arranged on the drain electrode side. FIG. 19 shows a third FET 203 disposed between the first and second FETs 201 and 202. The FET used here may be either HEMT or MESFET, but here it is assumed to be HEMT. Note that the same parts as those in the third embodiment are denoted by the same reference numerals, and the description thereof is partially omitted.

  The first FET 201 shown in FIG. 15 is connected to the source electrode 102 on the gate electrode 211 in addition to the source side eaves part length (wsg1) of the gate electrode 211 being longer than the drain side eaves part length (w). A wiring metal 111 is disposed via the second insulating film 110. Therefore, the capacitance (Cgs1) between the source electrode 102 and the gate electrode 211 is larger than the capacitance (Cgd1) between the gate electrode 211 and the drain electrode 103, and the capacitance (Cgs1a) between the gate electrode 211 and the wiring metal 111 is also parallel. It is connected.

  The second FET 202 shown in FIG. 16 is symmetric with the first FET 201 shown in FIG. 15, and the drain side eaves part length (wdg1) of the gate electrode 221 is longer than the source side eaves part length (w). A wiring metal 111 connected to the drain electrode 103 is disposed on the gate electrode 221 with the second insulating film 110 interposed therebetween. Therefore, the capacity (Cgd2) between the drain electrode 103 and the gate electrode 221 is larger than the capacity (Cgs2) between the gate electrode 221 and the source electrode 102, and the capacity (Cgd2a) between the gate electrode 221 and the wiring metal 111 is also parallel. It is connected.

Calculate for each of the capacities mentioned above. In FIG. 18, Cgd2 = Cgs1, Cgs2 = Cgd1, and Cgd2a = Cgd1a. Therefore, here, the respective capacities of FIG. 17 are shown, and FIG. 18 is omitted. A parallel plate model is assumed for the capacitance between the eaves portion of the gate electrode 211 and the ohmic contact layers (104, 105). The gate length is 0.5 μm, the first insulating film 106 is SiO ₂ , εr = 4, thickness = 0.15 μm, the second insulating film 110 is a SiN film, εr = 7, and thickness = 0.20 μm. Cgs1 (= Cgd2) = 0.236 pF / mm when wsg1 (= wdg1) = 1.0 μm, whereas Cgd1 (= Cgs2) = 0.024 pF / mm in the case of a normal T gate (w = 0.1 μm) Become. Since the gate head length (Lh1) of the gate electrode 221 is Lh1 = 1.0 + 0.5 + 0.1 = 1.6 μm, Cgs1a (= Cgd2a) = 0.774 pF / mm.

  The FETs according to this embodiment (the first FET 201 shown in FIG. 15 and the second FET 202 shown in FIG. 16) were applied to the through-type SPDT switch circuit having the three-stage stack structure shown in FIG. 12, Tr1 and Tr4 have the first FET 201 shown in FIG. 15, Tr3 and Tr6 have the second FET 202 shown in FIG. 16, and Tr2 and Tr5 have the third FET 203 shown in FIG. Using. The configuration and operation of the switch circuit are as described above. FIG. 20 shows an equivalent circuit when Tr1 to Tr3 are turned on and Tr4 to Tr6 are turned off. Note that the source side eaves part length (wsg1) of the gate electrode 211, the drain side eaves part length (wdg1) of the gate electrode 221 and the like are preferably the same as those in the third embodiment described above.

  In the circuit diagram of FIG. 12, power characteristics were evaluated at a frequency of 6 GHz. The input power (Pin) in which the second harmonic (2fo) and third harmonic (3fo), which are distortion indicators, exceed -75dBc was 30.3dBm when using a normal FET. In this embodiment, it was 32.5 dBm. In this way, the source side eaves part length (wsg1) of the gate electrode 211 of the first stage FET 201 and the drain side eaves part length (wdg1) of the gate electrode 221 of the final stage FET 202 in the multi-transistor structure are compared with other eaves part lengths (w). In addition to increasing the length, by adding capacitance between the gate electrodes 211 and 221 and the wiring metal 111, it becomes possible to further improve the distortion characteristics of the high-frequency switch circuit. Moreover, although HEMT was used in this embodiment, it cannot be overemphasized that even if it uses MESFET, there exists the same effect.

  Next, a semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 21 and 22 are cross-sectional views showing the structure of the FET used in the semiconductor device according to the fifth embodiment. FIG. 23 shows a plurality of FETs shown in FIG. 21 and FIG. 22 (further shown in FIG. 24) connected in series. It is a circuit diagram which shows the comprised switch circuit. Here, a MOSFET is used as the FET. A multi-FET switch circuit is configured by stacking FETs (single-gate FETs). In this embodiment, a switch circuit having a three-stage stack structure will be described.

  FIG. 21 shows the first FET 204 arranged on the source electrode side, and FIG. 22 shows the second FET 205 arranged on the drain electrode side. Note that FIG. 24 shows a third FET 206 disposed between the first and second FETs 204 and 205. The first, second, and third FETs 204, 205, and 206 have a source electrode 302 and a drain electrode 303 that are provided on a semiconductor substrate 301 such as a Si substrate at a certain distance.

  A gate electrode 304 is formed on the semiconductor substrate 301 with a gate insulating film 305 interposed between the source electrode 302 and the drain electrode 303. Further, an interlayer insulating film 306 and a wiring metal 308 are disposed on the source electrode 302 and the drain electrode 303, and a contact hole for connecting the source electrode 302, the drain electrode 303 and the wiring metal 308 to the interlayer insulating film 306. 307 is formed. The first FET 204 has a configuration in which a wiring metal 308 connected to the source electrode 302 extends to the gate electrode 304. The second FET 205 has a configuration in which a wiring metal 308 connected to the drain electrode 303 extends to the gate electrode 304.

The capacity when the wiring metal 308 described above extends to the gate electrode 304 is calculated. For the MOSFET shown in FIG. 24, the gate-source capacitance (Cgs0) and the gate-drain capacitance (Cgd0) are both equal in the off state (when Vth = + 0.8V, for example, Vds = 0V, Vgs = 0V). When the gate insulating film 305 is made of SiO ₂ , thickness 6 nm, and gate length (Lg) 0.25 μm, approximately Cgs = Cds = 0.18 pH / mm is obtained. On the other hand, the capacitance (Cgsa, Cgda) with respect to the wiring metal 308 on the gate electrode 304 in FIGS. 21 and 22 is Cgsa = Cgda = when the interlayer insulating film is a TEOS film (εr = 4) and the thickness is 0.05 μm. 0.177pF / mm. That is, the source-gate capacitance (Cgs204) of the FET 204 is Cgs204 = Cgs0 + Cgsa = 0.357 pH / mm. Similarly, the drain-gate capacitance (Cgd205) of the FET 205 is Cgd205 = Cgd0 + Cgda = 0.357 pF / mm.

  FIG. 23 shows a through FET SPDT switch circuit having a multi-FET structure in which the first FET 204 shown in FIG. 21, the second FET 205 shown in FIG. 22, and the third FET 206 shown in FIG. 24 are stacked in three stages. 23, the first FET 204 shown in FIG. 21 is used for the first stage Tr1 and Tr4, and the second FET 205 shown in FIG. 22 is used for the final stage Tr3 and Tr6. However, the third FET 206 shown in FIG. 24 is used for the intermediate Tr2 and Tr5.

  In the through SPDT switch circuit shown in FIG. 23, Tr1, Tr2 and Tr3 are connected in series, and each of these gate electrodes is connected to the control terminal Vc1 via a gate additional resistor Rgg. The same applies to Tr4, Tr5 and Tr6, which are connected in series, and each gate electrode is connected to the control terminal Vc2 via a gate additional resistor Rgg. Rd is used to make the drain and source potentials of the FETs the same, and may be a resistance of about 10 kΩ.

  The through SPDT switch circuit shown in FIG. 23 is a circuit that transmits the RF signal of either P2 or P3 to P1 and cuts off the other signal depending on the potential of Vc1 or Vc2 of the RF signal input to P2 or P3. It is. Specifically, FETs having a threshold value Vth of about 0.8 V were prepared as Tr1, Tr2, Tr3, Tr4, Tr5, Tr6, and the potential of Vc1 was set to 2 V or more with respect to the potentials of P1, P2, and P3. In this case, Tr1, Tr2, and Tr3 are turned on, and Tr4, Tr5, and Tr6 are turned off when the voltage is set to 0V.

  In the circuit diagram of FIG. 23, power characteristics were evaluated at a frequency of 6 GHz. The input power (Pin) in which the second harmonic (2fo) and third harmonic (3fo), which are distortion indicators, exceed -75dBc was 15.5dBm when using a normal FET. On the other hand, in this embodiment, it was 16.5 dBm. As described above, the wiring metal 308 connected to the source electrode 302 via the interlayer insulating film 306 is disposed on the gate electrode 304 of the first stage FET 204 in the multi-transistor structure, and the interlayer insulating film 306 is disposed on the gate electrode 304 of the final stage FET 205. By applying a structure in which the wiring metal 308 that is connected to the drain electrode 302 is applied, the distortion characteristics of the high-frequency switch circuit can be improved.

  Also, when FET 206 is used as the first stage and intermediate FET and FET 205 is used as the final stage FET, the third harmonic (3fo) is deteriorated compared to the case where FET 205 is used, and the second harmonic that is an index of distortion. The input power (Pin) at which the harmonic (2fo) and the third harmonic (3fo) exceed -75 dBc was 14.2 dBm. Even when the FET 204 is used as the first stage FET and the FET 206 is used as the intermediate stage and the final stage FET, the third harmonic (3fo) is deteriorated as compared with the case where the FET 205 is used, and the second harmonic is used as an index of distortion. The input power (Pin) at which the wave (2fo) and the third harmonic (3fo) exceed -75 dBc was 14.2 dBm. From this, it can be seen that it is necessary to use both the first-stage and final-stage FETs 204 and 205 together.

  In this embodiment, an example of stacking three stages of FETs having a single gate structure is shown. However, when two or more stages of FETs are stacked, ohmic electrodes are formed on the gate electrodes of the first and last stage FETs through which high-frequency waves are transmitted. The same effect can be obtained by extending the connected wiring metal. Further, it goes without saying that a shunt type switch circuit, a resonance type switch circuit, and a multi-port switch circuit (SPnT) have the same effect. In addition, although it demonstrated using MOSFET as FET here, it cannot be overemphasized that it is the same effect even if it is MESFET and HEMT.

  Next, a switch circuit according to a sixth embodiment of the present invention will be described with reference to FIG. FIG. 25 is a circuit diagram of an SP4T switch that handles high power and high frequency such as GSM. P1 is an antenna, P2 is passed through a matching circuit to the output terminal of a GSM800MHz band power amplifier (PA), P3 is passed through a matching circuit to a GSM800MHz low-noise amplifier (LNA), and P4 is passed through a matching circuit to output the DCS1800 PA. The terminal P5 is connected to the LNA of the DCS 1800 through a matching circuit. Rsd serves to make the bias between the source and drain of the FETs (T1 to T10) substantially the same, and is usually about 10 kΩ. The FET may be any of HEMT, MESFET, and MOSFET, but here it is assumed to be HEMT.

  The FET 203 shown in FIG. 13 is used for T2 to T4, T6 to T10, T12 to T14, and T16 to T20, the FET 201 shown in FIG. 8 is used for T1 and T11, and the FET 202 shown in FIG. 9 is used for T5 and T15. Using. In each of the T1, T5, T11, and T15 FETs, the eaves portion of the gate electrode closer to the RF terminal (P1, P2, P4) is longer than the other or the eaves portion of the FET shown in FIG. Thereby, the gate-source capacitance density Cgs1 of the FETs (T1, T11) close to the RF terminals (P2, P4) is larger than the gate-source capacitance density Cgs2 of the other FETs. Further, the gate-drain capacitance Cgd5 of the FETs (T5, T15) close to the RF terminal (P1) is larger than the gate-drain capacitance density Cgd2 of the other FETs.

Next, it is specifically shown how much the above-mentioned Cgs1 is larger than Cgs2 of other FETs. The first ohmic contact layer 105 is an N-GaAs layer having a thickness of 100 nm and a concentration of 5 × 10 ¹⁸ cm ⁻³ , and the second ohmic contact layer 104 is an n-GaAs layer having a thickness of 30 nm and a concentration of 3 × 10 ¹⁸ cm ^−3. The first insulating film 106 is SiO ₂ , the relative permittivity is 4, the thickness is 0.15 μm, the normal eaves part length (w) is 0.1 μm, the eaves part length of the FET having a long eaves part is 1.0 μm, and the gate A parallel plate model is assumed for the capacitance between the electrode eaves and the ohmic contact layers (105, 106). In the case of a normal T gate, Cgs2 = 0.024 pF / mm, whereas when wsg1 = 1.0 μm, Cgs1 = 0.24 pF / mm. In other words, it can be seen that the capacitance density increases as the length of the eaves portion of the gate is increased.

  Next, a method for setting the gate width from the viewpoint of design will be described. The terminal used for the output of the PA is required to have low distortion with respect to the high-power RF signal input from the PA. Here, since the third harmonic is generally higher than the second harmonic when the single FET is turned on with the gate width as a parameter in FIG. 26, the third harmonic (3f0) is −75 dBc. The pin exceeding P is plotted on the vertical axis. From this figure, it is understood that the gate width must be 3 mm or more in order to satisfy the high linearity (3f0 <−75 dBc) even at Pin = 35 dBm. On the other hand, since no large power is inserted on the receiving side, it is required to be shielded in Tx mode (transmission mode), that is, to have high isolation. Since it is sufficient to satisfy the insertion loss, for example, Wg = 0.8 mm.

  The effectiveness of the present embodiment will be described using the above parameters. FIG. 27 is a diagram in which high-order distortion generated with a high frequency reflected by the off-FET when the FET is off is plotted against Wg of the conventional FET and the FET adopting the structure of the present invention. This is the vertical axis of Pin where the third harmonic (3f0) exceeds -75 dBc. From these figures, the higher-order distortion increases with Wg, and when limited by the standard of -75 dBc, it should be 2.0 mm or less with the conventional structure alone, but with the structure of the present invention, it should be 6.0 mm or less. I understand. That is, in the case of the conventional structure, the standard of −75 dBc is not satisfied, but it can be seen that Wg = 3.0 mm may be used in the structure of the present invention. When the gate width Wg used on the receiving side is 0.8 mm, the two are combined to 1.6 mm, and the generated distortion clears -75 dBc.

Next, it will be shown that this embodiment is more effective than the prior art. When using the method described in Japanese Patent Application Laid-Open No. 11-136111, a capacitor of Cadd = 0.24 pF / mm × 3.0 mm = 0.72 pF is required when Wg = 3.0 mm. When this capacitor is formed of MIM, if the interlayer insulating film is SiN (εr = 7) and the thickness is 200 nm, an area of about 2300 μm ² is required. That is, an area of 30 μm width × 100 μm length is required. However, when the structure of the present invention is used, the strain characteristics can be improved without causing an increase in the chip area.

  In the present embodiment, an SP4T switch having two transmission ports and two reception ports has been described as an example. However, it can be realized by adjusting the Wg on the reception side even with two or more transmission ports or two or more reception ports. In the present embodiment, a switch having only a through FET has been described as an example. However, since a distortion can be further reduced by using a shunt switch, the present invention is also effective for a shunt switch circuit. Moreover, although HEMT was used in this embodiment, it cannot be overemphasized that even if it uses MESFET, there exists the same effect.

  Next, a switch circuit according to a seventh embodiment of the present invention will be described. Similarly to the sixth embodiment, the seventh embodiment is also shown in the circuit diagram shown in FIG. FIG. 25 is a circuit diagram of an SP4T switch that handles high power and high frequency such as GSM. P1 is an antenna, P2 is passed through a matching circuit to the output terminal of a GSM800MHz band power amplifier (PA), P3 is passed through a matching circuit to a GSM800MHz low-noise amplifier (LNA), and P4 is passed through a matching circuit to output the DCS1800 PA. The terminal P5 is connected to the LNA of the DCS 1800 through a matching circuit. Rsd serves to make the bias between the source and drain of the FETs (T1 to T10) substantially the same, and is usually about 10 kΩ. The FET may be any of HEMT, MESFET, and MOSFET, but here it is assumed to be HEMT.

  T2 to T4, T6 to T10, T12 to T14, and T16 to T20 are the FETs 203 shown in FIG. 13, T1 and T11 are the FETs 201 shown in FIG. 15, and T5 and T15 are the FETs 202 shown in FIG. Using. In each of the T1, T5, T11, and T15 FETs, the eaves of the gate electrode closer to the RF terminal (P1, P2, P4) are longer than the other and the eaves of the FET of FIG. The connected wiring metal 111 is disposed on the gate electrodes 211 and 221 via the second insulating film 110. As a result, the gate-source capacitance density Cgs1 of the FETs (T1, T11) close to the RF terminals (P2, P4) is larger than the gate-source capacitance density Cgs2 of the other FETs. Further, the gate-drain capacitance Cgd5 of the FETs (T5, T15) close to the RF terminal P1 is larger than the gate-drain capacitance density Cgd2 of the other FETs.

Next, it is specifically shown how much the above-mentioned Cgs1 is larger than Cgs2 of other FETs. The first ohmic contact layer 105 is an N-GaAs layer having a thickness of 100 nm and a concentration of 5 × 10 ¹⁸ cm ⁻³ , and the second ohmic contact layer 104 is an n-GaAs layer having a thickness of 30 nm and a concentration of 3 × 10 ¹⁸ cm ^−3. The first insulating film 106 is SiO ₂ , the relative permittivity is 4, the thickness is 0.15 μm, the normal eaves part length (w) is 0.1 μm, the eaves part length of the FET with the longer eaves part is 1.0 μm, the second The insulating film 110 is made of SiN, has a dielectric constant of 7 and a thickness of 0.20 μm, and has a capacitance between the eaves of the gate electrode and the ohmic contact layers (104, 105) and between the gate electrodes 211, 221 and the wiring metal 111. A parallel plate model is assumed for the capacity. In the case of a normal T-gate, Cgs2 = 0.024pF / mm, whereas when wsg1 = 1.0μm, the capacitance density between the eaves of the gate electrode and the ohmic contact layer is 0.24pF / mm, the gate length is 0.5μm, and the other The capacitance density between the gate electrode and the wiring metal when the eaves portion of the gate electrode is 0.1 μm is 0.50 pF / mm, and thus Cgs1 = 0.74 pF / mm. That is, it can be seen that the capacity density increases as the eaves portion length of the gate is increased.

  Next, a method for setting the gate width from the viewpoint of design will be described. The terminal used for the output of the PA is required to have low distortion with respect to the high-power RF signal input from the PA. Here, since the third harmonic is generally higher than the second harmonic when the single FET is turned on with the gate width as a parameter in FIG. 26, the third harmonic (3f0) is −75 dBc. The pin exceeding P is plotted on the vertical axis. From this figure, it is understood that the gate width must be 3 mm or more in order to satisfy the high linearity (3f0 <−75 dBc) even at Pin = 35 dBm. On the other hand, since no large power is inserted on the receiving side, it is required to be shielded in Tx mode (transmission mode), that is, to have high isolation. Since it is sufficient to satisfy the insertion loss, for example, Wg = 0.8 mm.

  The effectiveness of the present embodiment will be described using the above parameters. FIG. 27 is a diagram in which high-order distortion generated along with the high frequency reflected by the Off-FET when the FET is off is plotted against Wg of the FET adopting the conventional FET and the FET structure of the present invention. This is the vertical axis of Pin where the third harmonic (3f0) exceeds -75 dBc. From these figures, the higher-order distortion increases with Wg, and when limited by the standard of -75 dBc, it should be 2.0 mm or less with the conventional structure alone, but with the structure of the present invention, it should be 6.0 mm or less. I understand. That is, in the case of the conventional structure, the standard of −75 dBc is not satisfied, but it can be seen that Wg = 3.0 mm may be used in the structure of the present invention. When the gate width Wg used on the receiving side is 0.8 mm, the two are combined to 1.6 mm, and the generated distortion clears -75 dBc.

Next, it will be shown that this embodiment is more effective than the prior art. When using the method described in JP-A-11-136111, a capacitor of Cadd = 0.74 pF / mm × 3.0 mm = 2.22 pF is required at least when Wg = 3.0 mm. When this capacitor is formed of MIM, if the interlayer insulating film is SiN (εr = 7) and the thickness is 200 nm, an area of about 7100 μm ² is required. That is, an area of 71 μm width × 100 μm length is required. However, when the structure of the present invention is used, the strain characteristics can be improved without causing an increase in the chip area.

  In the present embodiment, an SP4T switch having two transmission ports and two reception ports has been described as an example. However, it can be realized by adjusting the Wg on the reception side even with two or more transmission ports or two or more reception ports. In the present embodiment, a switch having only a through FET is taken as an example. However, since a distortion can be further reduced by using a shunt switch, it is also effective for a shunt switch circuit. Needless to say. Moreover, although HEMT was used in this embodiment, it cannot be overemphasized that even if it uses MESFET, there exists the same effect.

  The present invention is not limited to the above-described embodiment, and is applied to a high-frequency switch circuit semiconductor device using various multi-gate FETs or various multi-FET semiconductor device for high-frequency switch circuits. be able to. Such a semiconductor device is also included in the present invention. The embodiments of the present invention can be expanded or modified within the scope of the technical idea of the present invention, and the expanded and modified embodiments are also included in the technical scope of the present invention.

It is sectional drawing which shows the structure of the semiconductor device for high frequency switch circuits which comprises the multigate FET by the 1st Embodiment of this invention. FIG. 2 is an equivalent circuit diagram of the multi-gate FET shown in FIG. 1. It is a circuit diagram which shows the high frequency switch circuit to which the multigate FET shown in FIG. 1 is applied. FIG. 4 is an equivalent circuit diagram when T1 of the high-frequency switch circuit shown in FIG. 3 is turned on and T2 is turned off. It is sectional drawing which shows the structure of the semiconductor device for high frequency switch circuits which comprises the multigate FET by the 2nd Embodiment of this invention. FIG. 6 is an equivalent circuit diagram of the multi-gate FET shown in FIG. 5. FIG. 6 is an equivalent circuit diagram when the multi-gate FET shown in FIG. 5 is applied to the high-frequency switch circuit shown in FIG. 3. It is sectional drawing which shows the structure of first stage FET in the semiconductor device for high frequency switch circuits of the multitransistor structure by the 3rd Embodiment of this invention. It is sectional drawing which shows the structure of the last stage FET in the semiconductor device for high frequency switch circuits of the multitransistor structure by the 3rd Embodiment of this invention. FIG. 9 is an equivalent circuit diagram of the first stage FET shown in FIG. 8. FIG. 10 is an equivalent circuit diagram of the final stage FET shown in FIG. 9. FIG. 10 is a circuit diagram showing a high-frequency switch circuit having a multitransistor structure to which the FET shown in FIGS. 8 and 9 is applied. It is sectional drawing which shows the structure of intermediate FET in the semiconductor device for high frequency switch circuits of a multitransistor structure. FIG. 13 is an equivalent circuit diagram when the first stage FET shown in FIG. 8 and the last stage FET shown in FIG. 9 are applied to the multi-transistor structure high-frequency switch circuit shown in FIG. It is sectional drawing which shows the structure of first stage FET in the semiconductor device for high frequency switch circuits of the multitransistor structure by the 4th Embodiment of this invention. It is sectional drawing which shows the structure of final stage FET in the semiconductor device for high frequency switch circuits of the multitransistor structure by the 4th Embodiment of this invention. FIG. 16 is an equivalent circuit diagram of the first stage FET shown in FIG. 15. FIG. 17 is an equivalent circuit diagram of the final stage FET shown in FIG. 16. It is sectional drawing which shows the structure of intermediate FET in the semiconductor device for high frequency switch circuits of a multitransistor structure. FIG. 17 is an equivalent circuit diagram in the case where the first stage FET shown in FIG. 15 and the last stage FET shown in FIG. 16 are applied to the multi-transistor structure high-frequency switch circuit shown in FIG. It is sectional drawing which shows the structure of first stage FET in the semiconductor device for high frequency switch circuits of the multi-transistor structure by the 5th Embodiment of this invention. It is sectional drawing which shows the structure of the last stage FET in the semiconductor device for high frequency switch circuits of the multi-transistor structure by the 5th Embodiment of this invention. It is a circuit diagram which shows the high frequency switch circuit of the multi-transistor structure to which FET shown in FIG. 21 and FIG. 22 is applied. It is sectional drawing which shows the structure of intermediate FET in the semiconductor device for high frequency switch circuits of a multitransistor structure. It is a circuit diagram which shows the high frequency switch circuit of the multi-transistor structure by the 6th and 7th embodiment of this invention. It is a figure which shows the gate width dependence of the distortion of the ON state of single FET. It is a figure which shows the gate width dependence of the distortion of the OFF state of single FET.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Multi-gate FET, 102, 302 ... Source electrode, 103, 303 ... Drain electrode, 107 ... First gate electrode, 108 ... Second gate electrode, 109 ... Third gate electrode, 201, 204 ... First stage FET 202, 205... Final stage FET, 211, 221, 304... Gate electrode.

Claims (5)

A high-frequency signal is input from one of the source and drain electrodes of a plurality of field effect transistors connected in series and output from the other, and is connected to the gate electrodes of the plurality of field effect transistors through resistors, respectively. In a semiconductor device for a high-frequency switch circuit that controls the passage and shielding of the high-frequency signal by the potential of the control terminal,
The parasitic capacitance density between the gate electrode and the ohmic electrode of the first stage field effect transistor and the parasitic capacitance density between the gate electrode and the ohmic electrode of the last stage field effect transistor are A semiconductor device characterized in that it is larger than the parasitic capacitance density. A high-frequency signal is input from one of the source electrode and the drain electrode of the field effect transistor and output from the other, and a plurality of gate electrodes provided between the source electrode and the drain electrode are respectively connected via resistors. In a semiconductor device for a high-frequency switch circuit that controls passage and shielding of the high-frequency signal by a potential of a connected control terminal,
A semiconductor device, wherein a parasitic capacitance density between a gate electrode closest to the ohmic electrode and the ohmic electrode is larger than a parasitic capacitance density between another gate electrode and a node between the gate electrodes.   The wiring metal is formed on the gate electrode having a large parasitic capacitance density through an insulating film, and the wiring metal is connected to the ohmic electrode having the large parasitic capacitance density. 2. The semiconductor device according to 2.   4. The semiconductor device according to claim 1, wherein the gate electrode having a high parasitic capacitance density has a T-shaped cross section including an eaves portion. 5. In a semiconductor device comprising a multi-port switch circuit having at least two transmission terminals and at least one reception terminal,
5. The semiconductor device according to claim 1, wherein the semiconductor device according to claim 1 is disposed between the transmission terminal and the antenna terminal.

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