JP5348239B2 - High frequency switch circuit - Google Patents

Abstract

The switch circuit comprises semiconductor switch blocks (210, 220) that switch between connecting and disconnecting high-frequency signals between high-frequency terminals. The proportion of parasitic capacities present in field effect transistors (FET) (31-36) that configure the semiconductor switch blocks (210, 220) are reduced through the addition of capacitative elements (51-62). The addition of these capacitative elements (51-62) makes it possible, when the switch blocks (210, 220) are off and the high-frequency signals change over time to positive and negative centered on the direct-current potential, to produce symmetric changes centered on the direct-current potential in the impedance seen from any of the high-frequency terminals, and thereby to reduce distortion.

Description

  The present invention relates to a high-frequency switch circuit for switching between passing and blocking of a high-frequency signal and a semiconductor device for realizing the same.

  Conventionally, a high-frequency switch circuit for switching between passing and blocking of a high-frequency signal is known. As a configuration of the high-frequency switch circuit, one using a diode or one using a field effect transistor (FET) is known.

  FIG. 13 is a diagram showing an example of a conventional high-frequency switch circuit 20 using FETs. The high frequency switch circuit 20 is a SPDT (single pole double through) type high frequency switch circuit. The high frequency switch circuit 20 includes a first switch block 21 and a second switch block 22. The first switch block 21 and the second switch block 22 have a SPST (single pole single through) type structure that switches between passing and blocking high-frequency signals.

  The first switch block 21 includes three FETs 31 to 33 connected in series by sharing a drain and a source with adjacent FETs. One end of the FET 31-33 units connected in series is connected to the first high-frequency terminal 1 and the other end is connected to the second high-frequency terminal 2. The gate terminal of each FET 31-33 is connected to the control terminal 11 via resistance elements 41-43.

  Similarly, the second switch block 22 includes three FETs 34 to 36 connected in series by sharing a drain and a source with adjacent FETs. One end of the units of the FETs 34-36 connected in series is connected to the first high frequency terminal 1, and the other end is connected to the third high frequency terminal 3. That is, the first switch block 21 and the second switch block 22 share the first high frequency terminal 1. The gate terminal of each FET 34-36 is connected to the control terminal 12 via the resistance elements 44-46.

The operation of the conventional high-frequency switch circuit 20 having such a configuration will be described.
In the high-frequency switch circuit 20 of FIG. 13, a high-level or low-level control signal is input to the control terminal 11 of the first switch block 21 and the control terminal 12 of the second switch block 22. Thereby, on / off of the first switch block 21 and the second switch block 22 is controlled.
Here, a binary control signal of high level and low level is complementarily input to the control terminal 11 and the control terminal 12. Then, the high frequency signal input from the first high frequency terminal 1 can be output from the second high frequency terminal 2 or the third high frequency terminal 3.
Alternatively, one of the high-frequency signals input from the second high-frequency terminal 2 and the third high-frequency terminal 3 can be output from the first high-frequency terminal 1.

FIG. 14 is a diagram showing an example of the layout of the switching FET used in the high-frequency switching circuit 20. The switching FET corresponds to the FETs 31-36.
As shown in FIG. 14, the FET has a configuration in which a drain electrode 143, a source electrode 144, and a gate electrode 142 are formed on a conductive channel 141. A resistor 145 is connected to the gate electrode 142 through a through hole 146. The resistor 145 corresponds to the resistor elements 41-46.

  Here, in the switching FET, it is necessary to increase the gate width. On the other hand, the parasitic capacitance increases as the gate width increases, and the switching characteristics deteriorate. Therefore, in general, a switching FET is often formed using a meander-shaped gate so that the gate electrode 142, the drain 143, and the source electrode 144 do not intersect with each other in order to avoid deterioration of characteristics due to parasitic capacitance. That is, as shown in FIG. 14, the source electrode 144 and the drain electrode 143 are each formed in a comb-like shape, and are further arranged so that the electrodes are opposed to each other. The gate electrode 142 is wired in a meander shape between the source electrode 144 and the drain electrode 143.

As characteristics required for a high-frequency switch circuit, it is important that non-linear distortion is small in addition to loss when a high-frequency signal passes and isolation between high-frequency terminals.
The non-linear distortion in the high frequency switch circuit 20 as shown in FIG. 13 is determined by the non-linearity of various elements constituting the switch circuit 20.
In a multi-port switch such as a 1-input n-output SPnT type or an n-input m-output nPmT type, the number of off-state paths increases compared to the on-state path.
Therefore, in this case, the off-state path is a source of large nonlinear distortion. This non-linear distortion occurs when the parasitic capacitance of the FET in the off state varies greatly depending on the potential of the high-frequency signal applied to the FET.

Among nonlinear distortions, even-order nonlinear distortions such as second-order harmonic distortion (2f ₀ distortion) and second-order intermodulation distortion (IMD2 distortion) constitute a switch when a positive / negative bias due to RF operation is applied. This occurs when the impedance value of the semiconductor element to be operated exhibits an asymmetric behavior with respect to the bias change. That is, when the impedance when a positive potential is applied to an off-state FET and the impedance when a negative potential is applied change asymmetrically, even-order nonlinear distortion occurs.

FIG. 15 is a diagram illustrating an example of the bias dependence of the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd) in the off-state FET.
When the bias is oscillated positively or negatively around the DC potential, the gate-source capacitance Cgs and the gate-drain capacitance Cgd change. That is, when the high-frequency signal input from the high-frequency terminal changes in the positive and negative directions with reference to the DC potential, the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd) also change.
Here, in the manufacture of FETs, there are factors causing product variations and errors such as misalignment of exposure. If there are variations or errors in the product, the gate-source capacitance Cgs and the gate-drain capacitance Cgd may exhibit characteristics that do not intersect at a DC potential.
In such a case, the capacitance characteristics of the entire FET have asymmetry with respect to the bias change, and even-order distortion will occur.

Here, the switching FET generally has a large gate width in general, and the resistance connected to the gate generally has a high resistance value of several kΩ to several hundred kΩ.
As shown in FIG. 14, the parasitic capacitance is reduced by adopting a meander type field effect transistor, but such a large gate width and a large resistance value are the area occupied by these elements in the layout. And increase parasitic elements caused by these elements, particularly an increase in ground capacitance.
Such parasitic capacitance (referred to as ground parasitic capacitance) between the FET and the back surface of the substrate greatly affects the characteristics.

FIG. 16 is a circuit diagram in which the first switch block 21 is taken out and the parasitic capacitances 81 to 83 are clearly shown in the conventional high-frequency switch circuit 20 of FIG.
Furthermore, here, a capacitive element 91 that allows high frequency to pass through and cuts off the DC potential, and a terminal load resistor 92 are additionally shown.
Each FET (31 to 33) has parasitic capacitances 81 to 83 connected to the gate terminals.
Actually, there are parasitic capacitances connected to the drain terminal and the source terminal, but the influence on the characteristics is very limited, and the description is omitted here.

FIG. 17 is a diagram showing an equivalent circuit when the switch circuit of FIG. 16 is in an OFF state.
In this equivalent circuit, the FET 31 is replaced with a gate-drain capacitance (Cgd) 101, a gate-source capacitance (Cgs) 102, and a drain-source capacitance (Cds) 111. The FET 32 is replaced with a gate-drain capacitance (Cgd) 103, a gate-source capacitance (Cgs) 104, and a drain-source capacitance (Cds) 112. The FET 33 is replaced with a gate-drain capacitance (Cgd) 105, a gate-source capacitance (Cgs) 106, and a drain-source capacitance (Cds) 113.

Here, the capacitances 81, 82, and 83, which are ground parasitic capacitances, are connected between the gate terminals and GND, but are sufficiently smaller than the capacitances existing in the path between each gate terminal and GND.
For example, there are capacitors 102, 103, 104, 105, 106, 112, 113, 91, etc. in the path from the gate terminal to which the capacitor 81 is connected to GND, but these are sufficient compared to the capacitor 81. It has a large capacity. Therefore, the capacitor 81 can be considered to be approximately parallel to the capacitor 102. The same applies to the parasitic capacitances 82 and 83. An equivalent circuit based on this approximation is shown in FIG.

When considering even-order distortion in the conventional switch circuit 20, the even-order distortion is greatly influenced by the symmetry of impedance with respect to positive and negative biases in one cycle of the input signal.
In particular, the capacitance between the gate and drain (Cgd) and the capacitance between the gate and source (Cgs) 101 to 106 have bias dependence, and their values change nonlinearly.
In addition, the presence of the parasitic capacitors 81 to 83 deteriorates the impedance symmetry and the distortion.

  Here, as means for reducing even-order distortion, methods disclosed in Patent Document 1 to Patent Document 12 are known.

JP 2005-341595 JP JP 2006-042138 JP JP 2005-323030 JP JP 2000-223902 A JP2005-065060 JP2005-072993 JP 2005-086420 JP JP 2006-211265 Gazette JP2007-073815 JP 2006-237450 JP JP 2007-27563 JP JP 2008-011320 JP JP 2002-118123 A

Patent Document 1 discloses a method of performing cancellation by reversing the phase of a distortion component using parallel paths.
However, this method is not practical in terms of controllability and area, such as adding a large circuit and not being able to use it to remove a distortion signal having a frequency close to that of the input signal.

Patent Document 2 discloses a technique that utilizes the weakening of only a signal of a specific frequency by a reflected signal.
This method is effective for attenuating a specific frequency, but cannot be applied to a plurality of frequencies.
Since distortion occurs at a plurality of frequencies, the method of Patent Document 2 is not effective for countermeasures against distortion.
Furthermore, the method of Patent Document 2 is not practical due to the area overhead because it is necessary to create a plurality of transmission lines (wirings).

Patent Document 3 discloses a circuit that reduces distortion by stabilizing the potential.
It is true that the operation of the switch is stabilized by stabilizing the potential.
However, the method of Patent Document 3 does not improve the capacity asymmetry.
Therefore, practically no effect is obtained in terms of improving even-order distortion.

According to the configurations disclosed in Patent Document 4 to Patent Document 9, it is possible to suppress deterioration of distortion at high power by improving handling power.
However, with these configurations, the effect of improving the distortion level in the normal operation region cannot be obtained.
In these configurations, since an asymmetric element is added, distortion is rather deteriorated with respect to impedance.

  Further, Patent Document 1 to Patent Document 9 do not describe ground parasitic capacitance, and it is not possible to prevent characteristic deterioration due to the influence of ground parasitic capacitance.

On the other hand, Patent Document 10 to Patent Document 12 refer to measures against ground parasitic capacitance.
Patent Document 10 discloses reducing the capacity to the back surface by disposing an insulator on the back surface. According to this method, by separating the distance between the front surface and the back surface, the capacity between them can be reduced. Therefore, it is the simplest method. However, the size of the FET arranged on the front surface is usually extremely small, such as about several tens of μm square to about 100 μm square compared to the size of the back surface (for example, Patent Document 13 illustrates the size of the FET). Therefore, the electric lines of force are concentrated on the surface side, and the capacitance value is almost determined at the surface portion. In considering the capacity between the front surface and the back surface, the parallel plate approximation is not established, and the capacity reduction by increasing the substrate thickness is limited.

Patent Document 11 discloses a method of applying a positive bias to the back surface and the side gate terminal in order to prevent electric lines of force from concentrating on the surface.
Although this method has an effect of reducing the ground parasitic capacitance, there is a problem that an additional electrode or power source, that is, a power source circuit needs to be changed.

Patent Document 12 discloses means for increasing the gate width Wg of a part of the FET array.
However, there are two problems with this method.
One problem is that an increase in the gate width Wg also causes an increase in ground parasitic capacitance, and as a result, distortion is not improved.
Another problem is that increasing the capacitance of some FETs causes an increase in input amplitude to the FET that does not increase the capacitance, and the distortion of the entire circuit may not change or may deteriorate. There is a point.

  An object of the present invention is to provide a high-frequency switch circuit capable of improving nonlinear distortion by using a means different from the conventional technique. In particular, an object of the present invention is to provide a high-frequency switch circuit that can reduce even-order distortion from an off-state switch block.

In the present invention, in order to solve the above problem, the ratio of the parasitic capacitance that causes the distortion is reduced.
Specifically, the parasitic capacitance itself is not reduced as in other means, but the proportion of the parasitic capacitance in the total capacitance is reduced.
That is, the switch circuit of the present invention includes a semiconductor switch block having a function of turning on / off a high-frequency signal passing path connecting the first high-frequency terminal and the second high-frequency terminal in accordance with an applied control signal, When the potential of the high-frequency signal input from the high-frequency terminal or the second high-frequency terminal changes positively or negatively with respect to the DC potential, the semiconductor switch block viewed from any of the high-frequency terminals at the positive-negative potential. An additional capacitor for increasing the capacitance in the semiconductor switch block is added so that the impedance of the semiconductor switch has a symmetric change around the DC potential, and the ratio of the parasitic capacitance of the semiconductor switch block is reduced.
Since the amount of distortion is determined by the ratio of parasitic capacitance to the total capacitance, the same effect can be obtained not only by reducing the parasitic capacitance but also by increasing the total capacitance.
As an actual measure, a capacitance element is added between the gate and drain of the FET and between the gate and source.
As a method for adding such capacitance, a structure was adopted in which gate-drain capacitance Cgd and gate-source capacitance Cgs were increased by adding MIM (metal-insulating film-metal) capacitance or changing the gate shape. There is capacity usage.
It should be noted that when the total capacitance is increased, the ground parasitic capacitance that is the cause of asymmetry is not increased, or even if it is caused, the ratio of the parasitic capacitance to the whole must be reduced.

  According to the present invention, the parasitic capacitance existing in the gate electrode of the FET, which is the cause of asymmetry, can be increased by adding the capacitance, and the ratio of the parasitic capacitance can be reduced. Can be reduced.

1 is a circuit diagram showing a first embodiment of a high-frequency switch circuit according to the present invention. FIG. 3 is an equivalent circuit diagram in which the first switch block of the high-frequency switch circuit according to the first embodiment is taken out and the parasitic capacitance in the off state is clearly shown. FIG. 3 is a diagram illustrating an example of bias dependence of a gate-source capacitance (Cgs) and a gate-drain capacitance (Cgd) when the FET is off in the first embodiment. FIG. 10 is an equivalent circuit diagram in which the first switch block of the high-frequency switch circuit is taken out and the ground parasitic capacitance is clearly shown in the second embodiment. The figure which shows the circuit example at the time of trying to reduce the even-order distortion only by the addition of the capacitance difference which compensates the parasitic capacitance of a gate electrode as a comparative example. The figure which shows the experimental result for demonstrating the effect of 1st Embodiment and 2nd Embodiment of this invention. FIG. 10 is a layout diagram in the case where an FET having an additional capacitor is actually realized in the third embodiment. FIG. 10 is a layout diagram in the case where an FET having an additional capacitance is actually realized in the fourth embodiment. FIG. 10 is a layout diagram in the case where an FET having an additional capacitance is actually realized in the fifth embodiment. FIG. 10 is an enlarged view of a gate electrode 152 of an additional FET 151, and is an enlarged view of a portion indicated by reference numeral 153 in FIG. The figure which shows the modification for enlarging the gate-drain capacity | capacitance Cgd and the gate-source capacity | capacitance Cgs. FIG. 9 is a diagram showing a switch circuit in which the first embodiment is applied to a first switch block and a second switch block is applied with a conventional configuration in Modification 1. The figure which shows the conventional high frequency switch circuit using FET in description of background art. The figure which shows an example of the conventional layout of FET for a switch used for a high frequency switch circuit. The figure which shows an example of the bias dependence of the capacity | capacitance between gate-sources (Cgs) and the capacity | capacitance between gate-drains (Cgd) when FET is an OFF state in background art. FIG. 14 is a circuit diagram in which the first switch block is taken out and the parasitic capacitance is clearly shown in the conventional high-frequency switch circuit of FIG. FIG. 17 is an equivalent circuit diagram when the switch circuit of FIG. 16 is in an OFF state. FIG. 18 is a diagram showing an equivalent circuit when the capacitor 81 in FIG. 17 is approximately regarded as being in parallel with the capacitor 102;

Embodiments of the present invention will be described with reference to the drawings.
In the FET used for the switch, the drain terminal and the source terminal often have the same structure, and in many cases do not distinguish between the two terminals, but in describing the configuration of the following embodiment, In order to clarify the connection relationship, the drain terminal and the source terminal will be described separately for convenience.
In the case of an SPDT (single pole double throw) switch, the shared terminal on the first high frequency terminal 1 side is the drain terminal, and the second high frequency terminal 2 or the third high frequency terminal 3 side terminal is the source terminal. To do.
Similarly, in the case of SPST (single pole single throw), a terminal on the first high frequency terminal 1 side is defined as a drain terminal, and a terminal on the second high frequency terminal 2 side is defined as a source terminal.
The switches of other structures will be described in the respective items.

(First embodiment)
FIG. 1 is a circuit diagram showing a first embodiment of a high-frequency switch circuit according to the present invention.
In the following description, the same elements as those shown in the background art are denoted by the same reference numerals, and the description thereof is omitted as appropriate.
The first embodiment is an example in which the present invention is applied to an SPDT type high-frequency switch circuit.
As shown in FIG. 1, the high-frequency switch circuit 200 according to the first embodiment includes a first switch block 210 that switches between passing and blocking a high-frequency signal between the high-frequency terminal 1 and the high-frequency terminal 2, and the high-frequency terminal 1 and the high-frequency terminal. And a second switch block 220 that passes or blocks a high-frequency signal between the terminal 3 and the terminal 3.
The first switch block 210 and the second switch block 220 share the first high-frequency terminal 1.

  The first switch block 210 includes FETs 31, 32, 33 connected in series, resistance elements 41, 42, 43 provided between the gate terminal of the FET 31-33 and the control terminal 11, and FETs 31-33, respectively. Additional capacitors 51, 52, 53, 54, 55, 56 provided between the gate and drain terminals and between the gate and source terminals, respectively.

  The second switch block 220 includes FETs 34, 35, and 36 connected in series, resistance elements 44, 45, and 46 provided between the gate terminals of the FETs 34, 35, and 36, and the control terminal 12, respectively, and FETs. And additional capacitors 57, 58, 59, 60, 61 and 62 provided between the gate and drain terminals of 34, 35 and 36 and between the gate and source terminals, respectively.

Here, in the additional capacitors 51 to 62, those connected to the same gate have the same capacitance value.
For example, the additional capacitor 51 is provided between the gate and drain of the FET 31, and the additional capacitor 52 is provided between the gate and source of the FET 31, so that the additional capacitor 51 and the additional capacitor 52 are connected to the gate of the same FET 31. Will be connected. Therefore, the additional capacitor 51 and the additional capacitor 52 need to have the same capacitance value. Similarly, since the additional capacitor 53 and the additional capacitor 54 are connected to the gate of the same FET 32, it is necessary to have the same capacitance value.
The same applies to the other additional capacitors 55 to 62.
On the other hand, for example, additional capacitors that are not connected to the gate of the same FET, such as the additional capacitor 51 and the additional capacitor 53, do not necessarily have the same capacitance value.

  However, in order to obtain the maximum effect of the present invention, it is desirable that the additional capacitances not connected to the gates of the same FET (for example, the relationship between the additional capacitance 51 and the additional capacitance 53) have the same capacitance value.

Next, the function and effect of the high frequency switch circuit 200 of the first embodiment will be described.
FIG. 2 is an equivalent circuit diagram in which the first switch block 210 of the high-frequency switch circuit according to the first embodiment is taken out and the parasitic capacitance in the off state is clearly shown.
In the present embodiment, when the additional capacitors 51 to 56 are added, these additional capacitors 51 to 56 are the gate-source capacitors 101, 103, and 105 and the gate-drain capacitors 102, 104 of the FETs 31 to 33 , respectively. 106 is provided in parallel with 106. When the additional capacitors 51 to 56 and the parasitic capacitors 101 to 106 of the FETs 31 to 33 are combined, it can be considered as if the gate-source capacitance and the gate-drain capacitance of the FETs 31 to 33 are increased.

As described above, the gate-source capacitance and the gate-drain capacitance of the FETs 31 to 33 are increased, so that the relative ratio of the parasitic capacitances 81 to 83 is decreased.
Thereby, the influence by the parasitic capacitances 81-83 becomes small, the asymmetry resulting from the parasitic capacitances 81-83 can be improved, and even-order distortion can be reduced.

Further, by adding the additional capacitors 51 to 56 having the same capacitance value between the gate and drain terminals and between the gate and source terminals for each of the FETs 31 to 33 , the gate-source capacitance Cgs and the gate The ratio of deviation from the drain-to-drain capacitance Cgd can be reduced.
As a result, the ratio at which the gate-source capacitance Cgs and the gate-drain capacitance Cgd of the FETs 31 to 33 fluctuate nonlinearly depending on the bias can also be reduced.
This relationship is shown in FIG.
As a result, not only even-order distortion but also odd-time distortion can be reduced.

(Second embodiment)
Next, a second embodiment of the present invention will be described.
The basic configuration of the second embodiment is the same as that of the first embodiment, but the second embodiment is characterized by the setting of the capacitance value of the additional capacitor.
In the second embodiment, the capacitance value of the additional capacitor disposed on the first high-frequency terminal side is made larger than the additional capacitor disposed on the second high-frequency terminal side by the amount of parasitic capacitance existing in the FET gate electrode.

This will be specifically described.
FIG. 4 is an equivalent circuit in which the first switch block 310 of the high-frequency switch circuit is extracted and the ground parasitic capacitance is clearly shown in the second embodiment.
In the second embodiment, additional capacitors 71, 72, 73, 74, 75, and 76 are provided between the gate and drain terminals and between the gate and source terminals of the FET 31-33, respectively.
Here, the capacitance values of the additional capacitors 71 and 72 provided between the gate and drain terminals and between the gate and source terminals of the FET 31 are represented by Cadd_gd and Cadd_gs, respectively. That is, the capacitance value of the additional capacitor 71 arranged on the first high frequency terminal side as viewed from the FET 31 is Cadd_gd. Also, the capacitance value of the additional capacitor 72 disposed on the second high frequency terminal side as viewed from the FET 31 is Cadd_gs.

Further, the capacitance value of the parasitic capacitance (capacitance 81) existing in the gate electrode of the FET 31 is Cp.
At this time, the capacitance value Cadd_gd of the additional capacitance 71 between the gate and drain terminals is equivalent to the capacitance value Cp of the parasitic capacitance (capacitance 81) existing in the gate electrode, rather than the capacitance value Cadd_gs of the additional capacitance 72 between the gate and source terminals. Enlarge.
That is, the following relationship is established.

  Cadd_gd = Cadd_gs + Cp

That is, the additional capacitor 71 has a capacitance value larger than the additional capacitor 72 by the capacitance value (Cp) of the parasitic capacitor 81.
The additional capacitor 73 has a capacitance value larger than the additional capacitor 74 by the capacitance value (Cp) of the parasitic capacitor 82.
The additional capacitance 75 has a capacitance value larger than the additional capacitance 76 by the capacitance value (Cp) of the parasitic capacitance 83.

There are no design restrictions on the capacitance values of the additional capacitors having the same relationship, for example, the additional capacitor 71 and the additional capacitor 73.
However, it is desirable that the additional capacitors having the same relationship have the same capacitance value in order to obtain the maximum effect of the present invention.
For example, the additional capacity 71, the additional capacity 73, and the additional capacity 75 are preferably set to the same capacity value.
Further, it is preferable that the additional capacity 72, the additional capacity 74, and the additional capacity 76 have the same capacity value.

Next, functions and effects of the second embodiment will be described.
Each FET 31-33 has asymmetry corresponding to the ground parasitic capacitances 81, 82, 83, and this is compensated by the capacitance difference of the additional capacitances 71-76.
That is, regarding FET 31, the combined capacitance between the gate and the source (the sum of the capacitance 101 and the additional capacitance 71) is the combined capacitance between the gate and the drain (the sum of the capacitance 102, the additional capacitance 72, and the parasitic capacitance 81). Design equal to
With such a design, impedance asymmetry can be improved and even-numbered distortion can be reduced.

Here, simply considering, it seems that even-order distortion can be reduced only by adding a capacitance difference that compensates for the parasitic capacitances 81 to 83 of the gate electrode.
In this case, the circuit example shown in FIG. 5 is obtained.
In FIG. 5, capacitors 301 to 306 added between the first high-frequency terminal and the gate electrode are designed in balance with the parasitic capacitance of the gate electrode.
However, an actual device has a problem that it is difficult to control a minute capacity. That is, there is a lower limit of a level at which capacity control is possible. Therefore, it is difficult to compensate for the parasitic capacitances 81 to 83 and sufficiently reduce even-order distortion only by adding a capacitance difference as shown in FIG.

In the second embodiment, not only the compensation of the parasitic capacitances 81 to 83 is added, but additional capacitances (71 to 76) are added between the gate and the source and between the gate and the drain, and these additional capacitances (71 to 76) are added. The capacitance value design in (76) is intended to further reduce even-order distortion.
As a result, in addition to reducing the ratio of the parasitic capacitances 81 to 83, we also designed a capacitance that compensates for the parasitic capacitances 81 to 83 with additional capacitors (71 to 76) that are sufficiently controllable even in actual devices. ing.
Thereby, there is an epoch-making effect that a realistic and highly precise distortion reduction can be realized.

(Experiment 1)
FIG. 6 shows the experimental results for demonstrating the effects of the first and second embodiments of the present invention.
FIG. 6 is a diagram showing results of actually measuring even-order distortion in each circuit of the prior art (the circuit configuration shown in FIG. 13), the first embodiment, FIG. 5, and the second embodiment. .
From the case of no measures (prior art), it was shown that there was an improvement of 15 dB in the first embodiment and further an improvement of 30 dB in the second embodiment.

As shown in the first embodiment and the second embodiment, in the present invention, when the switch block is composed of series-connected FETs, the additional capacitance is added to all of the series-connected FET arrays. It is necessary to provide.
Here, we present a method for increasing the capacitance value between the most between end increases the width Wg of the gate electrode of the FET of the gate and source of the FET and the gate and drain of the FET column Patent Document 12.
However, such a method is not effective.

For example, assume a FET string composed of three FETs.
Further, it is assumed that the gate electrode width Wg of the first FET, which is one of the FET arrays, can be doubled without increasing the ground parasitic capacitance.
In the conventional configuration, the input amplitude is uniformly (1/3) applied to all FETs.
On the other hand, due to the change in impedance due to the increase in the gate electrode width Wg, the input amplitude takes 1/5 for the first FET and 2/5 for the second and third FETs.
Here, it is further assumed that the generated even-order distortion is proportional to the amplitude applied to the FET. Then, the even-order distortion from the first FET becomes 0.3 times that of the prior art. However, the even-order distortion from the second and third FETs is 1.2 times. Then, as a whole, even-order distortion that is 0.9 times that of the conventional configuration is generated.

However, an ideal state that is impossible in the first place is considered, and in practice, the distortion generated from the FET increases nonlinearly with an increase in amplitude.
Furthermore, it is fundamentally impossible to make the increase in ground parasitic capacitance zero when the width Wg of the gate electrode is increased.

On the other hand, in the embodiment of the present invention, assuming that the capacitance of all FETs is doubled, the overall impedance changes, but the amplitude distribution between the FETs remains the same, and the even-order distortion is ideal as a total. Is 0.5 times that of the prior art.
Actually, there is an influence of non-linearity, etc., which is about 0.6 times that of the prior art, but it can be seen that even-order distortion can be improved effectively.

(Third embodiment)
Next, as a third embodiment, a specific layout for realizing the switch circuit of the present invention will be described.
In the configuration of the switch circuit, since the drain terminal and the source terminal are substantially symmetrical, in the description of the layout diagram, for the sake of convenience, the left side of the figure is the source terminal and the right side is the drain terminal.

FIG. 7 is a layout diagram in the case of actually realizing FETs 31 to 36 having additional capacitors (51 to 62 or 71 to 76).
In FIG. 7, a meander-type field effect transistor is configured, that is, a drain electrode 143, a source electrode 144, and a gate electrode 142 are formed on a conductive channel 141.
A resistor 145 is connected to the gate electrode 142 through a through hole 146. The resistor 145 corresponds to the resistors 41 to 46 in FIG.
Here, the gate electrode 142 is connected to a capacitor element 148 serving as an additional capacitor through a through hole 147.
This capacitive element 148 is configured to add capacitance between the gate electrode 142 and the source electrode 144 and between the gate electrode 142 and the drain electrode 143. That is, the additional capacitor 148 includes a metal plate 400 connected to the gate electrode, a metal plate 401 connected to the source electrode 144, and a metal plate 402 connected to the drain electrode 143. In addition, the metal plate 401 and the metal plate 402 are disposed to face the metal plate 400 with an insulating layer interposed between the metal plate 400 and the metal plate 400. With such a configuration, FETs 31 to 36 having additional capacitors (51 to 62 or 71 to 76) can be realized.

Although FIG. 7 shows an example in which the additional capacitor is arranged at the end of the gate terminal, the arrangement location of the additional capacitor is a design matter and can be appropriately selected.
For example, an additional capacitor may be arranged in the vicinity of the through hole 146 close to the resistor 145, or the additional capacitor may be arranged in the middle by dividing the FET.

(Fourth embodiment)
Next, a fourth embodiment will be described.
FIG. 8 is a layout diagram in the case of actually realizing FETs 31 to 36 having additional capacitors (51 to 62 or 71 to 76).
In the fourth embodiment, the gate electrode 142 is connected to the capacitor element 149 as an additional capacitor through the through hole 147.
The capacitive element 149 is configured to add capacitance between the gate electrode 142 and the source electrode 144 and between the gate electrode 142 and the drain electrode 143.
The capacitive element 149 is formed using a wiring metal or another metal, and is generally called an interdigital capacitor.
Although FIG. 8 shows a simplified case where each metal is one, a large number of metal lines may be alternately arranged like an actual generally used interdigital capacitor.
In this figure, the capacitive element is arranged at the end of the gate terminal, but it is a design item with respect to the arrangement location, so it may be arranged near the through hole 146 close to the resistor 145, and the FET is divided into the middle. You may arrange in.

(Fifth embodiment)
Next, a fifth embodiment will be described.
FIG. 9 is a layout diagram in the case of actually realizing FETs 31 to 36 having additional capacitors (51 to 62 or 71 to 76).
The fifth embodiment is characterized in that the additional capacitor is configured by an additional FET.

That is, the FET portion as a switch is a meander type field effect transistor.
One of the gate electrodes is connected to the resistor 145 through the through hole 146.
Here, in FIG. 9, in addition to the configuration of the switching FET 150, there is an additional FET 151 for adding capacitance.
The additional FET 151 has a meander-type field effect transistor structure similar to the switching FET 150 and is provided continuously with the switching FET 150. That is, the gate electrode 142 of the switching FET 150 is continuous with the gate terminal 152 of the additional FET 151. The drain electrode 143 and the source electrode 144 of the switching FET 151 are extended, and are continuous as the drain electrode and the source electrode of the additional FET 151.

  However, the gate electrode 152 of the additional FET 151 has a structure in which the gate-drain capacitance Cgd and the gate-source capacitance Cgs are larger than those of the switching FET 150.

FIG. 10 is an enlarged view of the gate electrode 152 of the additional FET 151, and corresponds to an enlarged view of a portion indicated by reference numeral 153 in FIG.
As shown in FIG. 10, the gate electrode 152 of the additional FET 151 has a plurality of protrusions toward the drain electrode 143 and the source terminal 144. As a result, the peripheral length of the gate electrode 152 becomes longer. Then, the gate-drain capacitance Cgd and the gate-source capacitance Cgs can be increased.
At this time, the parasitic capacitance to the ground also increases, but since the area of the gate electrode 152 facing the source electrode 144 and the drain electrode 143 increases more greatly by providing the gate electrode 152, the gate-drain capacitance Cgd The increase in the capacitance Cgs between the gate and the source is larger than the increase in the ground parasitic capacitance.

FIG. 11 shows a modification for increasing the gate-drain capacitance Cgd and the gate-source capacitance Cgs. In FIG. 11, the gate electrode 152 of the additional FET 151 is meandered between the opposing source electrode 144 and drain electrode 143.
Thereby, the area of the gate electrode 152 facing the source electrode 144 and the drain electrode 143 is greatly increased.

  With such a configuration, FETs 31 to 36 having additional capacitors (51 to 62 or 71 to 76) can be realized.

In the present invention, as a method of adding the additional capacitors 51 to 62, it is not possible to use the increase in capacitance by simply increasing the gate width Wg from the principle of the present invention.
As described above, the ground parasitic capacitance that causes asymmetry increases in proportion to the surface area of the FET.
Therefore, the increase in the gate width Wg increases the additional capacitances 51 to 62, and at the same time increases the ground parasitic capacitances 81 to 83.
Therefore, a simple increase in the gate width Wg cannot realize the configuration of the present invention in which the ratio of the parasitic capacitances (81 to 83) is reduced or the difference in parasitic capacitance is compensated.
In this regard, according to the third to fifth embodiments, the additional capacitance can be provided without increasing the ground parasitic capacitance 81 to 83.

(Modification 1)
In a switch circuit having two or more switch blocks, if there are different specifications / requirements for each switch block, it is not always necessary to configure all the switch blocks in the same configuration. Of course, the present invention may be applied.
For example, the configuration of the first embodiment or the second embodiment may be applied to a first switch block, and the second switch block may be a switch circuit to which a conventional configuration is applied.

FIG. 12 is a switch circuit in which the first embodiment is applied to the first switch block 210, and the second switch block 22 is a conventional circuit.
For example, assume that the configuration shown in FIG. 12 is used as a changeover switch circuit for simple transmission and reception. Then, it is assumed that the transmitter circuit is connected to the third high frequency terminal 3, the receiver circuit is connected to the second high frequency terminal 2, and the antenna is connected to the first high frequency terminal 1 for use. In this case, at the time of transmission in which distortion is a problem, the first switch block 210 is turned off and the second switch block 22 is turned on, but the first high frequency terminal 1 and the second high frequency terminal 2 have a low impedance. Become. In this state, the first switch block 210 in the off state has an effect of reducing even-order distortion as described in the first embodiment.

On the other hand, at the time of reception, the second switch block is turned off and the first switch block is turned on.
At this time, there is no effect of reducing the distortion of the switch circuit 500 itself, but the distortion is not a problem because the power is originally low at the time of reception.

  As described above, in the present invention, even-order distortion generated from an off-state switch block can be reduced, so that a high-power signal such as an antenna terminal passes when a high-frequency signal changes over time with a DC potential as a center. The first embodiment or the second embodiment is applied so that the impedance viewed from the high-frequency terminal changes symmetrically about the DC potential.

  Of course, the first embodiment and the second embodiment may be used in combination.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.
In the first and second embodiments, the SPDT is used as an example. However, the configuration of the present invention is not limited to the SPDT, and can also be used in an nPmT switch that switches input / output between an n port and an m port. is there.
Further, as an example, the case where the number of FETs connected in series is three is shown, but the present invention is not limited to this, and the present invention can be used even when the number of FETs is two or less or four or more.
In addition, other elements may be added to the first embodiment or the second embodiment as long as the effects of the present invention are not hindered. For example, the methods described in Patent Documents 10 and 11 may be used in combination. Is also possible.

The configuration in which the additional capacitor is added to the FET is not limited to the above-described embodiment, and it is of course possible to obtain the same effect with a configuration other than the example.
Further, an additional capacitor may be added to the FET in the switch circuit by using the methods of the third embodiment, the fourth embodiment, and the fifth embodiment in combination.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2009-041903 for which it applied on February 25, 2009, and takes in those the indications of all here.

  1, 2, 3 ... high frequency terminals, 11, 12 ... control terminals, 21, 22, 210, 220 ... SPST switch blocks, 31, 32, 33, 34, 35, 36 ... field effect transistors, 41, 42, 43, 44, 45, 46 ... resistive elements, 51-62, 71-76 ... capacitive elements, 81, 82, 83 ... ground parasitic capacitances, 91 ... DC blocking capacitive elements, 92 ... termination resistors, 101, 102, 103, 104 105, 106: gate-source capacitance, gate-drain capacitance (Cgd, Cgs), 111, 112, 113 ... drain-source capacitance (Cds), 141: channel portion, 142: gate metal, 143, 144 ... drain electrode or source electrode, 145 ... resistance element, 146, 147 ... through hole, etc. 148, 149 ... capacitive element, 151 ... field effect transistor for adding capacitance, 152 ... gate electrode, 200 ... high frequency switch circuit.

Claims (7)

A semiconductor switch block having a function of turning on and off a high-frequency signal passing path connecting the first high-frequency terminal and the second high-frequency terminal in accordance with an applied control signal;
Before Symbol semiconductor switch block, it becomes the drain terminal and the source terminal of a field effect transistor of each other to n connected in series (n ≧ 2),
A drain terminal of the first field effect transistor is connected to the first high frequency terminal, and a source terminal of the nth field effect transistor is connected to the second high frequency terminal;
Between each gate terminal of the field effect transistor and the control signal terminal, a resistor element, an inductor element, or a circuit by parallel connection or series connection of the resistor element and the inductor element is connected ,
When the potential of the high-frequency signal input from the first high-frequency terminal or the second high-frequency terminal changes in time positively or negatively around a DC potential, the semiconductor viewed from any of the high-frequency terminals at the positive-negative potential. In order to reduce the ratio of the parasitic capacitance existing at the gate terminal of the field effect transistor that constitutes the semiconductor switch block so that the impedance of the switch block causes a symmetric change around the DC potential , Additional capacity is added to increase capacity,
The switch circuit is characterized in that the additional capacitor is added so as to increase both the capacitance between the gate and drain terminals and the capacitance between the gate and source terminals . The switch circuit according to claim 1 ,
The sum of the capacitance value of the capacitance between the gate and drain terminals of the field effect transistor and the capacitance value of the additional capacitance connected between the terminals is Cgd,
When the sum of the capacitance value of the capacitance between the gate and source terminals of the field effect transistor and the capacitance value of the additional capacitance connected between the terminals is Cgs,
A switch circuit characterized in that Cgd and Cgs are equal. The switch circuit according to claim 2 ,
Cgd and Cgs are equal values for all field effect transistors constituting one semiconductor switch block. The switch circuit according to claim 1 ,
The sum of the capacitance value of the capacitance between the gate and drain terminals of the field effect transistor and the capacitance value of the additional capacitance connected between the terminals is Cgd,
When the sum of the capacitance value of the capacitance between the gate and source terminals of the field effect transistor and the capacitance value of the additional capacitance connected between the terminals is Cgs,
Cgd is equal to a value obtained by adding a capacitance value of a ground parasitic capacitance of a field effect transistor to Cgs. A semiconductor device constituting the switch circuit according to any one of claims 1 to 4 ,
The semiconductor device, wherein the additional capacitor for increasing the capacitance in the semiconductor switch block is created by using a capacitance between two or more metal wirings. A semiconductor device constituting the switch circuit according to any one of claims 1 to 4 ,
The additional capacitance that increases the capacitance in the semiconductor switch block is due to the addition of the gate electrode, and the ratio of the increase in parasitic capacitance is small compared to the increase in the normal gate width of the same length. apparatus. The semiconductor device according to claim 6 .
By changing the shape of the gate end of the semiconductor device, the perimeter length per unit gate width is increased, and the increase in capacitance existing in the semiconductor device is increased compared to the increase in the normal gate width of the same length. In addition, a semiconductor device characterized in that the rate of increase in parasitic capacitance is reduced.

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