JP2008271471A - Charge pump circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump circuit which is capable of generating a plus potential and a minus potential and reduces the number of flying capacitors and the number of switches. <P>SOLUTION: A charge pump circuit of the present invention comprises nine switches SW1-SW9, first and second flying capacitors C1 and C2, and first and second output capacitors Cout1 and Cout2. The first flying capacitor C1 on a first stage is connected to a node N1 that is a connecting node of SW1 and SW4, and a node N2 that is a connecting node of SW1 and SW2. Furthermore, the second flying capacitor C2 on a next stage (final stage) is connected to a node N3 that is a connecting node of SW4 and SW5, and a node N4 that is a connecting node of SW8 and SW9. From a first output terminal P1, 3VDD that is a plus potential is outputted and from a second output terminal P2, -2VDD that is a minus potential is outputted, wherein VDD is a power supply potential. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit that generates a negative potential and a positive potential.

  In general, a charge pump circuit is a circuit that generates a boosted potential by forming a plurality of pumping packets and boosting an input potential. In particular, charge pump circuits that generate a negative potential and a positive potential with respect to the ground potential (0 V) are widely used in power supply circuits and the like.

  FIG. 5 is a circuit diagram showing this type of charge pump circuit. This circuit includes eleven switches SW11 to SW21, three flying capacitors C11, C12, and C13, and two output capacitors Cout11 and Cout12.

  The flying capacitor C11 is connected to a node N11 that is a connection node between SW13 and SW14, and a node N12 that is a connection node between SW11 and SW12. The flying capacitor C12 is connected to a node N13 that is a connection node between SW14 and SW15, and a node N14 that is a connection node between SW16 and SW17.

  The flying capacitor C13 is connected to a node N16 that is a connection node between SW18 and SW19 and a node N17 that is a connection node between SW20 and SW21. The on / off switching of the switches SW11 to SW21 is controlled by a control circuit (not shown).

  Then, 3VDD which is a positive potential is output from the first output terminal P11, and −2VDD which is a negative potential is output from the second output terminal P12. VDD is a power supply potential.

  The steady state operation of the charge pump circuit will be described with reference to FIG. This charge pump circuit operates in two cycles of the first phase and the second phase, and first performs a positive boost to generate 3VDD, then performs a negative boost using 3VDD as a power source, and −2VDD Generate.

  First, plus boosting will be described. In the first phase, SW12, SW13, SW15, and SW16 are turned on, and SW11, SW14, and SW17 are turned off.

  Then, the potential of the node N11 becomes VDD and the potential of the node N12 becomes VSS (ground potential = 0V), so that the flying capacitor C11 is connected between VDD and VSS and charged. The potential of the node N14 changes from VSS to VDD, and the potential of the node N13 changes from 2VDD to 3VDD due to the capacitive coupling of the flying capacitor C12. The charge accumulated in the flying capacitor C12 is discharged through SW15, and the potential of the first output terminal P11 becomes 3VDD.

  In the second phase, SW12, SW13, SW15, and SW16 are turned off, and SW11, SW14, and SW17 are turned on. Then, the node N12 changes from VSS to VDD, and the node N11 changes from VDD to 2VDD due to the capacitive coupling of the flying capacitor C11. The electric charge accumulated in the flying capacitor C11 is discharged through SW14, and the potential of the node N13 becomes 2VDD. By alternately repeating the operations of the first phase and the second phase, 3VDD can be obtained from the first output terminal P11.

  Next, minus boosting will be described. In the first phase, SW18 and SW20 are turned on, and SW19 and SW21 are turned off. Then, the potential of the node N16 becomes VDD and the potential of the node N17 becomes 3VDD, so that the flying capacitor C13 is connected between VDD and 3VDD and charged. In the second phase, SW18 and SW20 are turned off, and SW19 and SW21 are turned on. Then, the node N17 changes from 3VDD to VSS, and the potential of the node N16 changes from VDD to -2VDD due to the capacitive coupling of the flying capacitor C13. The electric charge accumulated in the flying capacitor C13 is discharged through SW19, and the potential of the second output terminal P12 becomes −2VDD.

The charge pump circuit is described in Patent Documents 1 and 2.
JP 2001-231249 A JP 2001-286125 A

  However, in the charge pump circuit, in order to obtain a plus potential and a minus potential, plus boosting is once performed, and minus boosting is performed by using the output potential of the plus boosting as a power source. Therefore, the flying capacitors C11 and C12 of the plus boosting unit and the flying capacitor C13 of the minus boosting unit are separately required, and there is a problem that the number of switches SW11 to SW21 for controlling the connection relation of these flying capacitors is large. .

  Further, since the minus boosted output potential -2VDD is generated based on the plus boosted output potential 3VDD, if the load is suddenly applied to the minus boosted output terminal P12, the plus boosted output potential 3VDD also decreases. There was also a problem.

  The charge pump circuit of the present invention includes a first flying capacitor having a first terminal and a second terminal, a second flying capacitor having a third terminal and a fourth terminal, and a switching circuit. In the first phase, the switching circuit applies a power supply potential to the second terminal, applies a ground potential to the fourth terminal, and short-circuits the first terminal and the third terminal to perform the second flying The capacitor is charged, and in the second phase, a power supply potential is applied to the first terminal, a ground potential is applied to the second terminal, and a ground potential is applied to the third terminal to apply a second flying capacitor. In the third phase, a power supply potential is applied to the second terminal, a ground potential is applied to the fourth terminal, and a first potential is applied to the first terminal. Short terminal and third terminal The second flying capacitor is charged, and in the fourth phase, the ground potential is applied to the second terminal, the power supply potential is applied to the first terminal, and the power supply potential is applied to the fourth terminal. And controlling to output a positive output potential from the third terminal by discharging the second flying capacitor.

  According to the charge pump circuit of the present invention, a positive potential and a negative potential can be generated, and the number of flying capacitors and the number of switches can be reduced as compared with the conventional charge pump circuit. In addition, since the negative boost is not generated based on the positive boost potential, there is no correlation between them, and even if a load is suddenly applied to the output part of the negative boost, it is possible to prevent a decrease in the output potential of the positive boost.

  A charge pump circuit according to an embodiment of the present invention will be described in detail. FIG. 1 is a circuit diagram of the charge pump circuit. This circuit includes nine switches SW1 to SW9, first and second flying capacitors C1 and C2, and first and second output capacitors Cout1 and Cout2.

  The first flying capacitor C1 in the first stage is connected to a node N1 that is a connection node between SW3 and SW4 and a node N2 that is a connection node between SW1 and SW2. In other words, the first flying capacitor C1 has first and second terminals, the first terminal is connected to the node N1, and the second terminal is connected to the node N2.

  The second flying capacitor C2 at the next stage (final stage) is connected to a node N3 which is a connection node between SW4 and SW5 and a node N4 which is a connection node between SW8 and SW9. That is, the second flying capacitor C2 has third and fourth terminals, the third terminal is connected to the node N3, and the fourth terminal is connected to the node N4. The second flying capacitor C2 is shared by the plus booster and the minus booster.

  The first and second flying capacitors C1 and C2 are often attached outside the IC in which the charge pump circuit is formed, but can also be formed inside the IC. The on / off switching of the switches SW1 to SW9 is controlled by a control circuit (not shown). The switches SW1 to SW9 can be formed by MOS transistors or bipolar transistors.

  Then, 3VDD which is a positive potential is output from the first output terminal P1 (an example of an output terminal which outputs a positive output potential of the present invention), and the second output terminal P2 (the negative output potential of the present invention is output). -VDD, which is a negative potential, is output from an example of an output terminal that performs the above operation. VDD is a power supply potential.

  The steady-state operation of this charge pump circuit will be described with reference to FIGS. This charge pump circuit operates in four cycles of the first phase, the second phase, the third phase, and the fourth phase.

  In the first phase, SW1, SW4, and SW9 are turned on, and the other switches are turned off. Then, the potential of the node N2 becomes VDD, the potential of the node N4 becomes the ground potential, the nodes N1 and N3 are short-circuited, and the potentials of the nodes N1 and N3 become 2VDD. As a result, VDD is applied to the second terminal of the first flying capacitor C1, the fourth terminal of the second flying capacitor C2 is grounded, and the first terminal of the first flying capacitor C1 is connected to the first terminal. In a state where the third terminal of the second flying capacitor C2 is short-circuited, the second flying capacitor C2 is charged to 2VDD.

  Next, in the second phase, SW2, SW3, SW6, and SW7 are turned on, and the other switches are turned off. Then, the potential of the node N1 becomes VDD and the potential of the node N2 becomes VSS. Further, the node N3 changes from 2VDD to VSS. As a result, the first flying capacitor C1 is connected and charged between VDD and VSS, and the potential of the node N4 changes from VSS to −2VDD due to the capacitive coupling of the second flying capacitor C2. That is, by discharging the second flying capacitor C2, an output potential of −2VDD is obtained from the second output terminal P2 through the switch SW7 (an example of the first switch of the present invention) from the fourth terminal.

  Next, in the third phase, similarly to the first phase, SW1, SW4, and SW9 are turned on, and the other switches are turned off. Then, the potential of the node N2 becomes VDD, the potential of the node N4 becomes the ground potential, the nodes N1 and N3 are short-circuited, and the potentials of the nodes N1 and N3 become 2VDD. As a result, VDD is applied to the second terminal of the first flying capacitor C1, the fourth terminal of the second flying capacitor C2 is grounded, and the first terminal of the first flying capacitor C1 is connected to the first terminal. In a state where the third terminal of the second flying capacitor C2 is short-circuited, the second flying capacitor C2 is charged to 2VDD.

  Next, in the fourth phase, SW2, SW3, SW5, and SW8 are turned on, and the other switches are turned off. Then, the potential of the node N1 becomes VDD and the potential of the node N2 becomes VSS. The node N4 changes from VSS to VDD. As a result, the first flying capacitor C1 is connected and charged between VDD and VSS, and the potential of the node N3 changes from 2VDD to 3VDD due to the capacitive coupling of the second flying capacitor C2. That is, the output potential of 3VDD is obtained from the first output terminal P1 through the switch SW5 (an example of the second switch of the present invention) from the third terminal by the discharge of the second flying capacitor C2.

  Next, returning to the first phase, SW1, SW4, and SW9 are turned on, and the other switches are turned off. Then, the potential of the node N2 changes from VSS to VDD, and the node N4 changes from VDD to VSS. Nodes N1 and N3 are short-circuited. As a result, the potentials of the nodes N1 and N2 change from 3VDD to 2VDD due to capacitive coupling of the first flying capacitors C1 and C2.

  By repeating the operations from the first phase to the fourth phase, the output potential of 3VDD from the first output terminal P1 and the potential of −2VDD from the second output terminal P2 are stably obtained. .

  Thus, according to the above-described charge pump circuit, since the second flying capacitor C2 in the final stage of the plus booster is shared with the minus booster, the number of flying capacitors is reduced by one compared to the conventional method. can do. Accordingly, the number of switches can be reduced by two. Further, since the negative boost is not generated based on the positive boost potential, there is no correlation between them, and even if a load is suddenly applied to the output part of the negative boost, a decrease in the output potential of the positive boost can be prevented.

  In the present embodiment, the charge pump circuit that obtains the positive boosted potential 3VDD and the negative boosted potential -2VDD has been described. However, the present invention is not limited to this and can be applied to a multistage charge pump circuit. In other words, the plus boosting unit is configured as in the conventional method of FIG. 5, and the second flying capacitor C2 and switches SW5 to SW9 (the circuit unit surrounded by the broken line in FIG. 1) are added to the final stage. Good. In general, if the number of stages of the plus boosting unit up to the last stage is N, a plus boosted potential (N + 2) VDD and a minus boosted potential − (N + 1) VDD can be obtained. In this case, the charge pump circuit of this embodiment corresponds to N = 1.

1 is a circuit diagram of a charge pump circuit according to an embodiment of the present invention. FIG. It is a figure which shows the ON / OFF state of the switch of the charge pump circuit by embodiment of this invention. It is a figure which shows the state of the flanking capacitor | condenser of the charge pump circuit by embodiment of this invention. It is a wave form diagram showing operation of a charge pump circuit by an embodiment of the present invention. It is a circuit diagram of the charge pump circuit of a prior art example. It is a figure which shows the ON / OFF state of the switch of the charge pump circuit of a prior art example.

Explanation of symbols

SW1 to SW9 Switch C1 First flying capacitor C2 Second flying capacitor P1 First output terminal P2 Second output terminal

Claims (2)

A first flying capacitor having a first terminal and a second terminal;
A second flying capacitor having a third terminal and a fourth terminal;
A switching circuit,
In the first phase, the switching circuit applies a power supply potential to the second terminal, applies a ground potential to the fourth terminal, and short-circuits the first terminal and the third terminal, Charge the flying capacitor
In the second phase, by applying a power supply potential to the first terminal, applying a ground potential to the second terminal, and applying a ground potential to the third terminal to discharge the second flying capacitor Output a negative output potential from the fourth terminal,
In the third phase, the power supply potential is applied to the second terminal, the ground potential is applied to the fourth terminal, and the first and third terminals are short-circuited to charge the second flying capacitor. ,
In the fourth phase, a ground potential is applied to the second terminal, a power supply potential is applied to the first terminal, and a power supply potential is applied to the fourth terminal to discharge the second flying capacitor. A charge pump circuit which controls to output a positive output potential from a third terminal. The switching circuit includes: a first switch connected between the fourth terminal and an output terminal that outputs a negative output potential; and a third switch and an output terminal that outputs a positive output potential. 2. A second switch connected in between, wherein the first switch conducts only in the second phase, and the second switch conducts only in the fourth phase. The charge pump circuit described.

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