JP2008263195A - Reference voltage source circuit using field-effect transistor - Google Patents

Reference voltage source circuit using field-effect transistor Download PDF

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JP2008263195A
JP2008263195A JP2008092067A JP2008092067A JP2008263195A JP 2008263195 A JP2008263195 A JP 2008263195A JP 2008092067 A JP2008092067 A JP 2008092067A JP 2008092067 A JP2008092067 A JP 2008092067A JP 2008263195 A JP2008263195 A JP 2008263195A
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field effect
effect transistor
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JP4847976B2 (en
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Yoshin Zen
容震 全
Hirobumi Watanabe
博文 渡辺
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Ricoh Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a stable reference voltage generating circuit that is free from influence of junction leak at high temperatures. <P>SOLUTION: A reference voltage source circuit comprises a first pair field effect transistor circuit having conductive gates with different polarities, a second pair field effect transistor circuit having gates with the same conductivity and different impurity concentrations, and a compound circuit for composing differences in work functions of the gate electrodes of the first and second pair field effect transistors at an arbitrary ratio. Only to the field effect transistors M1 to M5 in the composing circuit, a substrate electrode W is separated from a source and is connected to a GND instead. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、特に高温でも安定動作する電界効果トランジスタを用いた基準電圧源回路に関する。   The present invention relates to a reference voltage source circuit using a field effect transistor that operates stably even at a high temperature.

従来、電界効果トランジスタ(以下単にトランジスタという)を用いた電圧発生回路及び基準電圧源回路として、図1に示す特開2001-284464があり、導電型の極性が異なるゲートを有するペアのトランジスタ(M1、M2)と、同じ極性の導電型で高濃度と低濃度のゲートを持つペアのトランジスタ(M3、M4)のそれぞれのゲート材の仕事関数差を利用して基準電圧を得るものである。   Conventionally, as a voltage generation circuit and a reference voltage source circuit using a field effect transistor (hereinafter simply referred to as a transistor), there is JP-A-2001-284464 shown in FIG. , M2), and the work function difference between the gate materials of the paired transistors (M3, M4) having the same polarity conductivity type and high concentration and low concentration gates are used to obtain the reference voltage.

図1において、トランジスタM1は(不純物濃度が)高濃度n型のゲートを持ち、ゲートとソースを結線して定電流源となる。トランジスタM2は、高濃度p型のゲートを持ち、n型チャンネルのトランジスタM5と抵抗Rからなるソースフォロア回路によりゲート電位が与えられる。トランジスタM3は、高濃度n型のゲートを持つ。トランジスタM4は、低濃度n型のゲートを持ち、ゲートをソースに結線して定電流源となる。   In FIG. 1, a transistor M1 has a high-concentration n-type gate (impurity concentration) and connects the gate and source to form a constant current source. The transistor M2 has a high-concentration p-type gate, and a gate potential is applied by a source follower circuit including an n-type channel transistor M5 and a resistor R. The transistor M3 has a high concentration n-type gate. The transistor M4 has a low-concentration n-type gate, and connects the gate to the source to become a constant current source.

すべてのトランジスタM1,M2,M3,M4,M5において、特にトランジスタM1とM2およびトランジスタM3とM4ではそれぞれペアのトランジスタとして機能させるために、基板効果が出ないように、基板内のウェルをトランジスタ毎に独立させ、かつ基板電極Wをソースに接続して、基板電位をソース電位としている。   In all the transistors M1, M2, M3, M4, and M5, in particular, the transistors M1 and M2 and the transistors M3 and M4 function as a pair of transistors. The substrate potential is set to the source potential by connecting the substrate electrode W to the source.

第1のペアトランジスタは、両トランジスタM1、M2に同一の電流が流れるため、出力電圧V1は負の温度係数を有する電圧Vpnが得られ、第2のペアトランジスタは、両トランジスタM3、M4に同一の電流が流れるため、出力電圧であるゲート・ソース間電圧Vgsは、正の温度係数を有する電圧−Vptatが得られる。前記電圧V1(=Vpn)を抵抗R1、R2で分圧して得た電圧V2と、Vgs(=−Vptat)とを加算して当該回路より出力電圧V3を得ている。   In the first pair transistor, since the same current flows in both transistors M1 and M2, the output voltage V1 is a voltage Vpn having a negative temperature coefficient, and the second pair transistor is the same as both transistors M3 and M4. Therefore, a voltage −Vptat having a positive temperature coefficient is obtained as the output voltage Vgs between the gate and the source Vgs. The voltage V2 obtained by dividing the voltage V1 (= Vpn) by resistors R1 and R2 and Vgs (= −Vptat) are added to obtain an output voltage V3 from the circuit.

前記電圧Vpnおよび電圧Vptatにおける負および正の温度係数が相殺されるように分圧比を設定すれば、出力電圧V3には、温度係数を持たない基準電圧Vrefが得られる。   If the voltage division ratio is set so that the negative and positive temperature coefficients in the voltage Vpn and the voltage Vptat are offset, a reference voltage Vref having no temperature coefficient can be obtained as the output voltage V3.

上記図1に示される従来の基準電圧源回路では、高温になってpnジャンクションの逆方向リークが発生した場合、トランジスタのドレイン−基板電流が増加するため、回路のそれぞれの段において電流が増加する。トランジスタM1とM2で構成される第1段目においては、ペアトランジスタで構成されているので、トランジスタM1のドレイン−基板電流と、トランジスタM2のドレイン−基板電流とには同じ電流が流れる。そのため、Vpnはpnジャンクションリークの無い場合と同じ値をとるので温度による影響を受けずに一定の値となる。トランジスタM3とM4で構成される第3段目も同様である。   In the conventional reference voltage source circuit shown in FIG. 1, when the reverse leakage of the pn junction occurs at a high temperature, the drain-substrate current of the transistor increases, so that the current increases at each stage of the circuit. . Since the first stage composed of the transistors M1 and M2 is composed of a pair transistor, the same current flows through the drain-substrate current of the transistor M1 and the drain-substrate current of the transistor M2. For this reason, Vpn takes the same value as when there is no pn junction leak, and thus is constant without being affected by temperature. The same applies to the third stage including the transistors M3 and M4.

しかしながら、第2段目のソースフォロア回路を構成するトランジスタM5は、ペア構成のトランジスタではなく、また基板電位をソース電位と等しくしてあるため、トランジスタM5の基板電流増加によって以下に述べるような弊害が生じる。   However, since the transistor M5 constituting the second-stage source follower circuit is not a pair-structured transistor, and the substrate potential is made equal to the source potential, the following problems are caused by the increase in the substrate current of the transistor M5. Occurs.

図2は、トランジスタのゲート電圧(Vg)・ソース電流(Is)の特性を示すグラフであり、“1”は室温での特性を示す。高温でのジャンクションリークによりトランジスタのドレイン−基板電流が増加すると、図1に示すようにトランジスタM5の基板電位をソース電位と等しくしてある(トランジスタ毎に独立したウェルの中に基板端子Wとソース端子がある)ため、基板−ソース電流が加算されてソース電流が増える。そのため、高温では“2”で示した特性になってしまう。   FIG. 2 is a graph showing the characteristics of the gate voltage (Vg) / source current (Is) of the transistor, and “1” indicates the characteristics at room temperature. When the drain-substrate current of the transistor increases due to junction leakage at a high temperature, the substrate potential of the transistor M5 is made equal to the source potential as shown in FIG. 1 (the substrate terminal W and the source are in wells independent for each transistor). Therefore, the substrate-source current is added to increase the source current. Therefore, the characteristics indicated by “2” are obtained at high temperatures.

トランジスタM5は、抵抗R1,R2とVpnで決まる一定電流Vpn/(R1+R2)を保つ必要があるため、トランジスタM5のゲート・ソース間電圧はVg1からVg2に低下する。トランジスタM2のドレイン電圧は、トランジスタM5のゲート電圧で与えられゲート・ソース間電圧Vgsが低下するのに伴って低下し、その結果、トランジスタM2のドレイン・ソース間電圧も下がる。   Since the transistor M5 needs to maintain a constant current Vpn / (R1 + R2) determined by the resistors R1, R2 and Vpn, the gate-source voltage of the transistor M5 decreases from Vg1 to Vg2. The drain voltage of the transistor M2 is given by the gate voltage of the transistor M5 and decreases as the gate-source voltage Vgs decreases. As a result, the drain-source voltage of the transistor M2 also decreases.

トランジスタM2のドレイン・ソース間電圧が(Vth−Vgs)以下になるとトランジスタ動作は飽和領域から線形領域に移り、一段目の定電流源となるトランジスタM1で決められる電流値をトランジスタM2が流すためには、トランジスタM2のVgsを上昇する必要が出てくる。結果としてトランジスタM2のVgs(Vpn)が上昇し、Vrefも上昇してしまうという課題を引き起こした。   When the drain-source voltage of the transistor M2 becomes (Vth−Vgs) or less, the transistor operation shifts from the saturation region to the linear region, and the transistor M2 passes the current value determined by the transistor M1 serving as the first-stage constant current source. Therefore, it is necessary to increase the Vgs of the transistor M2. As a result, Vgs (Vpn) of the transistor M2 rises and Vref also rises.

本発明の目的は、上記の課題を解消するためのもので、ペアのトランジスタ以外のトランジスタ(ソースフォロア回路を構成するトランジスタ)の基板電位をソースから切り離してGNDに接続することにより、高温でもジャンクションリークに依存しない安定した基準電圧を得ることのできる電界効果トランジスタを用いた基準電圧源回路を提供することである。   An object of the present invention is to solve the above-described problems. By separating the substrate potential of transistors other than a pair of transistors (transistors constituting a source follower circuit) from the source and connecting them to GND, the junction can be obtained even at high temperatures. To provide a reference voltage source circuit using a field effect transistor capable of obtaining a stable reference voltage independent of leakage.

基準電圧源回路は、導電型の極性が異なるゲートを有する“第1のペア電界効果トランジスタ回路”と、同一の導電型で不純物の濃度が異なるゲートを有する“第2のペア電界効果トランジスタ回路”と、第1及び第2のペア電界効果トランジスタのゲート電極の仕事関数差を任意の比で合成するために、電界効果トランジスタおよび抵抗からなる“合成回路”とからなる。そして既述したように、各電界トランジスタのゲート電極Wはそれぞれのソースに接続されていたが、本発明では、前記“合成回路”における電界効果トランジスタに対してのみ、基板電極Wをソースから切り離してGNDに接続した。   The reference voltage source circuit includes a “first pair field effect transistor circuit” having gates having different conductivity types and a “second pair field effect transistor circuit” having gates having the same conductivity type and different impurity concentrations. In order to synthesize the work function difference between the gate electrodes of the first and second pair field effect transistors at an arbitrary ratio, a “synthesis circuit” including a field effect transistor and a resistor is included. As described above, the gate electrode W of each field transistor is connected to the source. However, in the present invention, the substrate electrode W is separated from the source only for the field effect transistor in the “synthesis circuit”. Connected to GND.

高温になってpnジャンクションの逆方向リークが発生した場合、トランジスタのドレイン−基板電流が増加するため、本発明の実施形態を示した図3のそれぞれの段において電流が増加する。しかしながら、トランジスタM1とM2で構成される第1段目においては、基板電位をソース電位と等しくした(独立したウェルの中に基板端子とソース端子がある)ペアトランジスタで構成されているため、トランジスタM1のドレイン−基板電流と、トランジスタM2のドレイン−基板電流とには同じ大きさの電流が流れる。したがって、Vpnを得る過程で、両トランジスタにおけるリーク電流による影響が相殺されるため、このVpnは温度による影響を受けずに一定の値となる。トランジスタM3とM4で構成される第3段目も同様である。(この動作は従来例と同じ)   When reverse leakage of the pn junction occurs at a high temperature, the drain-substrate current of the transistor increases, so that the current increases in each stage of FIG. 3 showing the embodiment of the present invention. However, the first stage composed of the transistors M1 and M2 is composed of a pair transistor in which the substrate potential is equal to the source potential (the substrate terminal and the source terminal are in an independent well). The same current flows in the drain-substrate current of M1 and the drain-substrate current of the transistor M2. Therefore, in the process of obtaining Vpn, the influence of the leakage current in both transistors is canceled out, so that Vpn becomes a constant value without being affected by temperature. The same applies to the third stage including the transistors M3 and M4. (This operation is the same as the conventional example)

次に、第2段目は本発明の特徴である「基板電極をソースから切り離してGNDに接続した」トランジスタM5で構成したソースフォロア回路である。まず、このように構成したトランジスタM5の温度に対するドレイン電流(Id)、ソース電流(Is)、基板電流(Ib)の変化を図4のグラフに示す。   Next, the second stage is a source follower circuit constituted by a transistor M5 “a substrate electrode is separated from a source and connected to GND”, which is a feature of the present invention. First, the graph of FIG. 4 shows changes in the drain current (Id), the source current (Is), and the substrate current (Ib) with respect to the temperature of the transistor M5 configured as described above.

図4からわかるように、ある温度以上になるとpnジャンクションの逆方向リークによりトランジスタの基板電流が上昇し、またドレイン電流は、ソース電流と基板電流の和であるため、基板電流の上昇の影響を受けて共に増加する。しかしながら、基板とソースを独立させているため、ソース電流においては高温でも基板電流増加による影響は見られない。   As can be seen from FIG. 4, when the temperature exceeds a certain temperature, the substrate current of the transistor rises due to reverse leakage of the pn junction, and the drain current is the sum of the source current and the substrate current. It increases together. However, since the substrate and the source are independent, the source current is not affected by the increase in the substrate current even at a high temperature.

既述したように、ソースフォロア回路を構成するトランジスタM5は抵抗R1、R2とVpnで決まる一定電流Vpn/(R1+R2)を保つ必要がある。抵抗R1、R2へ流れる電流はトランジスタM5のソース電流に等しく、上に述べたように基板電流をGNDに流すことにより、ソース電流はリーク電流(ドレイン−基板電流)の影響を受けない。従って、本発明ではソースフォロア回路のトランジスタの基板電位をソース電位から切り離してGNDとすること、及びペアのトランジスタを用いることにより、高温でも安定した基準電圧源回路が実現できる。以下、本発明の実施形態を更に詳しく説明する。   As described above, the transistor M5 constituting the source follower circuit needs to maintain a constant current Vpn / (R1 + R2) determined by the resistors R1, R2 and Vpn. The current flowing through the resistors R1 and R2 is equal to the source current of the transistor M5, and the source current is not affected by the leak current (drain-substrate current) by flowing the substrate current to GND as described above. Therefore, in the present invention, a reference voltage source circuit that is stable even at a high temperature can be realized by separating the substrate potential of the source follower circuit transistor from the source potential to GND and using a pair of transistors. Hereinafter, embodiments of the present invention will be described in more detail.

図3において、トランジスタM1、M2、M3、M4、M5はすべてnチャンネルで、基板やチャンネルドーブの不純物濃度は等しく、n型基板の独立したpウェル内に形成され、トランジスタM1,M2,M3,M4の基板電位はソース電位と等しくしてある。   In FIG. 3, transistors M1, M2, M3, M4, and M5 are all n-channel, and the impurity concentrations of the substrate and channel dove are the same, and are formed in independent p-wells of the n-type substrate, and transistors M1, M2, M3, The substrate potential of M4 is equal to the source potential.

しかしながら、ソースフォロア回路を構成するトランジスタM5の基板電位はソース電位から独立させGNDにしてある。チャンネル幅Wとチャンネル長Lの比(W/L)は、トランジスタM1とM2とで等しく、そして、トランジスタM3とM4とで等しい。トランジスタM1は高濃度n型のゲートを持ち、ゲートをソースを結線した定電流源としている。トランジスタM2は、高濃度p型のゲートを持ち、n型チャンネルのトランジスタM5と抵抗Rからなるソースフォロア回路によりゲート電位が与えられる。   However, the substrate potential of the transistor M5 constituting the source follower circuit is set to GND independently of the source potential. The ratio (W / L) of the channel width W to the channel length L is equal for the transistors M1 and M2, and is equal for the transistors M3 and M4. The transistor M1 has a high-concentration n-type gate, and the gate is a constant current source in which the source is connected. The transistor M2 has a high-concentration p-type gate, and a gate potential is applied by a source follower circuit including an n-type channel transistor M5 and a resistor R.

トランジスタM3は、高濃度n型のゲートを持つ。トランジスタM4は、低濃度n型のゲートを持ち、ゲートとソースを結線して定電流源となる。ペアトランジスタM1とM2には同一電流が流れるためトランジスタM2のゲート・ソース間電圧はトランジスタM1とM2のVthの差Vpnとなる。   The transistor M3 has a high concentration n-type gate. The transistor M4 has a low-concentration n-type gate, and connects the gate and the source to become a constant current source. Since the same current flows through the pair transistors M1 and M2, the gate-source voltage of the transistor M2 becomes the difference Vpn between the Vth of the transistors M1 and M2.

また、第2のペアトランジスタM3とM4も、同一電流が流れるため、トランジスタM3、M4のゲート・ソース間電圧の差は、トランジスタM4のゲート・ソース間電圧が0のため、トランジスタM3のゲート・ソース間電圧Vgsに等しくなり、これが正の温度係数を有する電圧(−Vptat)となる。   Also, since the same current flows through the second pair of transistors M3 and M4, the gate-source voltage difference of the transistors M3 and M4 is 0 because the gate-source voltage of the transistor M4 is 0. This is equal to the source-to-source voltage Vgs, which is a voltage (−Vptat) having a positive temperature coefficient.

トランジスタM3のソース電位をV3とすれば、
V2=V3+Vgs、V2=V1*R2/(R1+R2)の関係から
V3=V2+Vptat=V1*R2/(R1+R2)+Vptat
=Vpn*R2/(R1+R2)+Vptat
となり、既述したように、分圧比を適宜設定することにより、もしくはゲートの不純物濃度を変える(VpnおよびVgsが変化)ことにより、V3には、温度特性を持たない基準電圧Vrefを得ることができる。
If the source potential of the transistor M3 is V3,
From the relationship of V2 = V3 + Vgs, V2 = V1 * R2 / (R1 + R2) V3 = V2 + Vptat = V1 * R2 / (R1 + R2) + Vptat
= Vpn * R2 / (R1 + R2) + Vptat
As described above, the reference voltage Vref having no temperature characteristic can be obtained for V3 by appropriately setting the voltage dividing ratio or changing the impurity concentration of the gate (Vpn and Vgs are changed). it can.

本発明によれば、高温でも安定した電界効果トランジスタを用いた基準電圧発生回路を実現することが可能となる。詳しくは、請求項1に記載の発明で、ペア電界効果トランジスタ以外の電界効果トランジスタの基板電位をソースから切り離してGNDとしたことにより、ジャンクションリークによる影響が排除され、高温でも安定した基準電圧発生回路を実現することができる。   According to the present invention, it is possible to realize a reference voltage generation circuit using a field effect transistor that is stable even at a high temperature. Specifically, in the invention according to claim 1, by removing the substrate potential of the field effect transistor other than the pair field effect transistor from the source and setting it to GND, the influence of the junction leakage is eliminated, and stable reference voltage generation is possible even at a high temperature. A circuit can be realized.

従来の基準電圧源回路の図Diagram of conventional reference voltage source circuit トランジスタのゲート電圧対ソース電流の関係を示した特性図Characteristic diagram showing the relationship between the gate voltage and source current of a transistor 本発明の1実施形態になる回路図The circuit diagram which becomes one Embodiment of this invention 本発明で用いたトランジスタの温度変化に対するドレイン電流、ソース電流および基板電流の特性図Characteristics diagram of drain current, source current and substrate current against temperature change of the transistor used in the present invention

符号の説明Explanation of symbols

M1、M2、M3、M4、M5 電界効果トランジスタ、R 抵抗   M1, M2, M3, M4, M5 Field effect transistor, R resistance

Claims (1)

導電型の極性が異なるゲートを有する第1のペア電界効果トランジスタ回路と、同一の導電型で不純物の濃度が異なるゲートを有する第2のペア電界効果トランジスタ回路と、第1及び第2のペア電界効果トランジスタのゲート電極の仕事関数差を任意の比で合成するために、電界効果トランジスタおよび抵抗からなる合成回路とから構成される基準電圧源回路において、
前記合成回路における電界効果トランジスタの基板電極をソースから切り離してGNDに接続したことを特徴とする基準電圧源回路。
A first pair field effect transistor circuit having gates having different conductivity types, a second pair field effect transistor circuit having gates having the same conductivity type and different impurity concentrations, and first and second pair field In order to synthesize the work function difference of the gate electrode of the effect transistor at an arbitrary ratio, in a reference voltage source circuit composed of a synthesis circuit composed of a field effect transistor and a resistor,
A reference voltage source circuit, wherein a substrate electrode of a field effect transistor in the synthesis circuit is separated from a source and connected to GND.
JP2008092067A 2008-03-31 2008-03-31 Reference voltage source circuit using field effect transistor Expired - Fee Related JP4847976B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8692610B2 (en) 2012-02-24 2014-04-08 Panasonic Corporation Reference voltage supply circuit
WO2022091540A1 (en) * 2020-10-27 2022-05-05 パナソニックIpマネジメント株式会社 Substrate current suppression circuit, reference voltage generation circuit, and semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1167931A (en) * 1997-04-04 1999-03-09 Citizen Watch Co Ltd Reference voltage generating circuit
JP2001284464A (en) * 1999-12-28 2001-10-12 Ricoh Co Ltd Voltage generating circuit using field effect transistor and reference voltage source circuit
JP2004014625A (en) * 2002-06-04 2004-01-15 Ricoh Co Ltd Reference voltage source circuit employing field effect transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1167931A (en) * 1997-04-04 1999-03-09 Citizen Watch Co Ltd Reference voltage generating circuit
JP2001284464A (en) * 1999-12-28 2001-10-12 Ricoh Co Ltd Voltage generating circuit using field effect transistor and reference voltage source circuit
JP2004014625A (en) * 2002-06-04 2004-01-15 Ricoh Co Ltd Reference voltage source circuit employing field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8692610B2 (en) 2012-02-24 2014-04-08 Panasonic Corporation Reference voltage supply circuit
WO2022091540A1 (en) * 2020-10-27 2022-05-05 パナソニックIpマネジメント株式会社 Substrate current suppression circuit, reference voltage generation circuit, and semiconductor device

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