JP2008259340A - Motor drive circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enlarge the range of power supply voltage where on/off operation of a drive transistor connected with the drive coil of a motor is performed stably. <P>SOLUTION: The motor drive circuit for controlling a motor by performing on/off control of a field effect type drive transistor connected with the drive coil in a motor and controlling the coil current flowing through the drive coil comprises a circuit for generating a drive signal having a first level dependent on the power supply voltage and performing on/off control of the drive transistor, a charge pump circuit for generating a step-up voltage of second level higher than the first level based on the power supply voltage, a circuit for generating a constant voltage by regulating the step-up voltage from the second level to a third level which is higher than the first level but lower than the second level, and an inverter circuit for transforming the drive signal from the first level to the third level and generating a gate voltage being applied to the gate electrode of the drive transistor. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a motor drive circuit.

The motor drive circuit uses the power supply voltage VCC as an operating voltage, and turns on / off based on a logic circuit that controls the entire motor and a drive signal output from the logic circuit. It is mainly composed of a field effect type drive transistor (such as an H-bridge circuit) that controls supply, stop, direction, and the like. Note that the logic circuit can be operated by applying the regulated voltage VREG which is made constant by lowering the level of the power supply voltage VCC. On the other hand, the drive transistor becomes operable when the power supply voltage VCC is applied, and is turned on / off by a gate voltage corresponding to the power supply voltage VCC generated based on the drive signal (see, for example, Patent Document 1 shown below). reference).
JP 2006-238529 A

  In recent years, there is a demand for operating the motor drive circuit by reducing the level of the power supply voltage VCC. However, as the level of the power supply voltage VCC is lowered, it becomes difficult to generate the regulated voltage VREG, and the operation of the logic circuit and consequently the on / off operation of the drive transistor cannot be performed. Even if the logic circuit can be operated by lowering the level of the power supply voltage VCC, the level of the drive signal output from the logic circuit itself is also lowered. As a result, the drive transistor is turned on / off by a low level drive signal (gate voltage) output from the logic circuit, so that the on-resistance of the drive transistor is lowered and the efficiency is deteriorated. Thus, the conventional motor drive circuit has a problem that the range of the power supply voltage VCC in which the on / off operation of the drive transistor is stably performed is narrow.

  A main invention for solving the above problems is a motor drive that performs motor control by controlling on-off control of a field effect type drive transistor connected to a drive coil of a motor to control a coil current flowing in the drive coil. In the circuit, a drive control circuit which has a first level corresponding to a power supply voltage and generates a drive signal for controlling on / off of the drive transistor, and a first level higher than the first level based on the power supply voltage A charge pump circuit that generates a boosted voltage of level 2, and a regulator that regulates the boosted voltage from the second level to a third level that is higher than the first level and lower than the second level. A regulation circuit for generating a rate voltage; and transforming the drive signal from the first level to the third level to transform the drive transistor An inverter circuit for generating a gate voltage applied to the gate electrode of the capacitor, and having a.

  According to the present invention, it is possible to expand the range of the power supply voltage that can stably perform the on / off control of the drive transistor for causing the coil current to flow through the drive coil.

<<< Signal processing system of sensorless motor drive circuit >>>
With reference to FIG. 2, the signal processing system of the sensorless motor drive circuit 100 according to the present invention will be described with reference to FIG. In addition, as a motor system configured using the sensorless motor driving circuit 100, a fan (fan motor) for exhausting heat generated in an electric appliance (a personal computer, an air conditioner, a refrigerator, etc.) to the outside is driven to rotate. The fan motor system to be made is illustrated. Further, as the sensorless motor driving circuit 100, a case of an integrated circuit of Bi-CMOS process is illustrated.

  The UO terminal, VO terminal, and WO terminal of the sensorless motor driving circuit 100 are three-phase (U-phase, V-phase, and W-phase) that are star-connected and wound around the stator with a phase difference of 120 degrees in electrical angle. Drive coils Lu, Lv, and Lw are connected. Thereby, the three-phase drive coils Lu, Lv, and Lw are connected to the drive transistor circuit configured by the NMOS field effect transistors M1 to M6 via the UO terminal, the VO terminal, and the WO terminal. The NMOS field effect transistors M1, M3, and M5 provided on the source power supply line 102 side receive a coil current IL that flows from the source power supply line 102 toward the U-phase, V-phase, and W-phase drive coils Lu, Lv, and Lw. NMOS field effect transistors M2, M4, and M6 that are discharge source side (discharge side) transistors and are provided on the sink power supply line 104 side are sink power supplies from U-phase, V-phase, and W-phase drive coils Lu, Lv, and Lw. This is a sink side (suction side) transistor that sucks the coil current IL flowing toward the line 104.

  When the NMOS field effect transistors M1 to M6 are turned on and off at an appropriate timing, a coil current IL corresponding to the level of the power supply voltage VCC is supplied to the three-phase drive coils Lu, Lv, and Lw. As a result, the sensorless motor rotates in a predetermined direction (for example, positive rotation), and coil voltages Vu, Vv, having a phase difference of 120 electrical degrees are applied to one end of the three-phase drive coils Lu, Lv, Lw. Vw is generated. The coil voltages Vu, Vv, and Vw can be said to be rotation signals having a frequency corresponding to the rotation speed of the sensorless motor. These coil voltages Vu, Vv, and Vw are applied to the input terminals U, V, and W included in the switch circuit 110 having three inputs and one output via the UO terminal, the VO terminal, and the WO terminal.

  A coil voltage Vu applied to the input terminals U, V, W of the switch circuit 110 in accordance with any one of the U phase, V phase, and W phase, which will be detected by the comparator 120 as a zero cross point described later. Vv and Vw are selected by the sensorless logic circuit 130. Then, the selected voltages Vu, Vv, and Vw are applied to the + terminal of the comparator 120 via the output terminal of the switch circuit 110. On the other hand, the neutral point voltage Vcom of the star connection of the three-phase drive coils Lu, Lv, and Lw is applied to the negative terminal of the comparator 120 via the COM terminal of the sensorless motor drive circuit 100. That is, the coil voltage applied to the + terminal is a coil voltage of a phase for detecting a zero cross point where the output (one of Vu, Vv, Vw) of the switch circuit 110 and the neutral point voltage Vcom intersect, The sex point voltage Vcom is a voltage at the connection point of the two-phase drive coils other than the phase for detecting the zero cross point.

  As a result, the comparator 120 detects a zero cross point where the coil voltages Vu, Vv, Vw selected in the switch circuit 110 applied to the + terminal and the neutral point voltage Vcom applied to the − terminal intersect. . The comparator 120 outputs a rectangular-wave FG signal (binary signal of the rotation signal) whose edge is switched at the zero cross point to the sensorless logic circuit 130 and to the microcomputer 400 via the FG output terminal. Output.

  The sensorless logic circuit 130 performs predetermined energization control according to the system clock MCLK generated by the oscillator 160. Specifically, after removing (masking) the noise corresponding to the kickback pulse KB from the FG signal output from the comparator 120, based on the FG signal after the noise removal, the drive signal U1 shown in FIG. U2, V1, V2, W1, and W2 are generated and output. The drive signals U1, V1, and W1 are control signals for driving the gate electrodes of the NMOS field effect transistors M1, M3, and M5 on the source power line 102 side, and the drive signals U2, V2, and W2 are This is a control signal for driving the gate electrodes of the NMOS field effect transistors M2, M4, and M6 on the sink power supply line 104 side. The levels of the drive signals U1, U2, V1, V2, W1, and W2 are adjusted by the predrive circuit 140, and the NMOS field effect transistor M1 is used as the drive signals U1 ′, U2 ′, V1 ′, V2 ′, W1 ′, and W2 ′. Applied to each of the gate electrodes M6.

  Here, an example of energization control of the NMOS field effect transistors M1 to M6 by the drive signals U1, U2, V1, V2, W1, and W2 will be described with reference to FIG.

  For example, in the first period T0 (a period corresponding to an electrical angle of 60 degrees) shown in FIG. 2, the drive signals U1, V2 are at the H level, and the drive signals U2, V1, W1, W2 are at the L level. Accordingly, only the NMOS field effect transistors M1 and M4 are turned on. As a result, a current path that reaches the source power supply line 102, the drain / source path of the NMOS field effect transistor M1, the drive coil Lv, the drain / source path of the NMOS field effect transistor M4, and the sink power supply line 104 is formed. In other words, the NMOS field effect transistor M1 discharges the coil current IL toward the drive coil Lv, and the NMOS field effect transistor M4 sucks the coil current IL from the drive coil Lv.

  Further, in a period T1 (a period corresponding to an electrical angle of 60 degrees) subsequent to the period T0 shown in FIG. 2, the drive signals U1, W2 are at the H level, and the drive signals U2, V1, V2, W1 are at the L level. Accordingly, only the NMOS field effect transistors M1 and M6 are turned on. As a result, a current path that reaches the source power supply line 102, the drain / source path of the NMOS field effect transistor M1, the drive coil Lw, the drain / source path of the NMOS field effect transistor M6, and the sink power supply line 104 is formed. In other words, the NMOS field effect transistor M1 discharges the coil current IL toward the drive coil Lw, and the NMOS field effect transistor M6 sucks the coil current IL from the drive coil Lw.

  As described above, the sensorless logic circuit 130 considers that the sensorless motor itself cannot specify the relative position between the rotor and the stator before starting, and follows the predetermined energization sequence of the NMOS field effect transistors M1 to M6 in accordance with the U-phase. , Control for energizing the V-phase and W-phase drive coils Lu, Lv, and Lw is performed.

  Incidentally, the FG signal output from the comparator 120 is also input to the activation counter 125 in addition to the sensorless logic circuit 130. The activation counter 125 counts for a predetermined count period based on the FG signal input from the comparator 120. Based on the count result, the sensorless logic circuit 130 performs timing setting for switching energization of the drive coils Lu, Lv, and Lw when the sensorless motor is activated. Specifically, the activation counter 125 can be configured by a counter that counts a predetermined count period longer than the edge interval of the FG signal and resets the count at the edge timing of the FG signal.

<<< Power supply system of sensorless motor drive circuit >>>
The power supply system of the sensorless motor driving circuit 100 according to the present invention will be described with reference to FIGS. 2, 3, and 4.

  A power supply voltage VCC of a level corresponding to the rotation speed is applied to the VM terminal of the sensorless motor driving circuit 100 in order to perform PAM (Pulse Amplitude Modulation) control. Further, the GND terminal of the sensorless motor driving circuit 100 is grounded via a resistance element Rd.

  The power supply voltage VCC applied to the VM terminal is converted into the reference voltage VREF by the reference voltage generation circuit 150. The reference voltage VREF is used as a bias voltage for operating various circuits inside the sensorless motor driving circuit 100. In this embodiment, the level of the power supply voltage VCC is the “first level” according to the present invention, but the level of the reference voltage VREF may be the “first level”.

  The power supply voltage VCC applied to the VM terminal is converted by the charge pump circuit 180 into a boosted voltage VG obtained by boosting the power supply voltage VCC twice. Note that the level of the boosted voltage VG corresponds to the “second level” according to the present invention. Specifically, the charge pump circuit 180 boosts the power supply voltage VCC by charging the capacitive element C3 connected between the CP terminal and the CPC terminal. Further, the boosted voltage VG output from the charge pump circuit 180 is smoothed by the capacitive element C2 connected to the VG terminal, and then supplied to the regulation circuit 190, the pre-drive circuit 140, and the comparator 120. Note that the charge pump circuit 180 limits the level of the boosted voltage VG so as not to exceed the gate breakdown voltage VB of the NMOS field effect transistors M1, M3, and M5, for example, by a voltage limiter circuit using a diode element.

  The regulation circuit 190 reduces the level of the boosted voltage VG supplied from the charge pump circuit 180, and generates a regulated voltage VREG that is a constant voltage. The level of the regulated voltage VREG corresponds to the “third level” according to the present invention. Specifically, the regulation circuit 190 includes an operational amplifier 195 that can operate when a boosted voltage VG is applied. A divided voltage Vd obtained by dividing the boosted voltage VG by the resistance elements R1 and R2 is applied to the + terminal of the operational amplifier 195, and a reference voltage VR is applied to the − terminal of the operational amplifier 195. The level of the divided voltage Vd is set as “VG × R2 ÷ (R1 + R2)”. For example, when the level of the divided voltage Vd becomes higher than the reference voltage VR, the state of the PMOS field effect transistor M7 is changed by the output of the operational amplifier 195 to turn off. As a result, the level of the divided voltage Vd is lowered so as to approach the level of the reference voltage VR. On the other hand, when the level of the divided voltage Vd becomes lower than the reference voltage VR, the state of the PMOS field effect transistor M7 is changed to turn on by the output of the operational amplifier 195. As a result, the level of the divided voltage Vd increases so as to approach the level of the reference voltage VR.

  As described above, the regulator circuit 190 operates with the boosted voltage VG, and performs control to adjust the divided voltage Vd based on the boosted voltage VG to the reference voltage VR. When the divided voltage Vd is adjusted to the reference voltage VR, the level of the regulated voltage VREG output from the regulating circuit 190 is “VR × (R1 + R2) ÷ R2.” The regulated voltage VREG is supplied to the pre-drive circuit 140. The regulation circuit 190 limits the level of the regulator voltage VREG so as not to exceed the gate withstand voltage VB of the NMOS field effect transistors M2, M4, and M6 by adjusting the level of the reference voltage VR.

  As described above, the power supply voltage VCC applied to the VM terminal is converted into the reference voltage VREF by the reference voltage generation circuit 150, converted into the boost voltage VG by the charge pump circuit 180, and the regulation circuit. There are a case where the voltage is converted into the regulated voltage VREG by 190 and a case where the voltage is not converted into any of the reference voltage VREF, the boosted voltage VG and the regulated voltage VREG. The power supply voltage VCC is applied to a drive transistor circuit including NMOS field effect transistors M1 to M6, and the reference voltage VREF is applied to a sensorless logic circuit 130, an oscillator 160, and a charge pump circuit 180. The boosted voltage VG is applied to the comparator 120, the pre-drive circuit 140, and the regulator circuit 190, and the regulated voltage VREG is applied to the pre-drive circuit 140.

  Here, the pre-drive circuit 140 to which the boosted voltage VG and the regulated voltage VREG are applied will be described with reference to FIG.

  The source side inverter circuit 141 becomes operable when the boosted voltage VG is applied from the charge pump circuit 180. Then, the level of the drive signal U1 generated based on the reference voltage VREF in the sensorless logic circuit 130 is transformed to the level of the boosted voltage VG and output as the drive signal U1 '. That is, the drive signal U1 'transformed to the level of the boost voltage VG is applied as the gate voltage to the gate electrode of the NMOS field effect transistor M1 on the source side. Note that the same applies to the source-side inverter circuits 143 and 145, and thus description thereof is omitted.

  The sink-side inverter circuit 142 becomes operable when the regulated voltage VREG is applied from the regulating circuit 190. Then, the level of the drive signal U2 generated based on the reference voltage VREF in the sensorless logic circuit 130 is transformed to the level of the regulated voltage VREG and output as the drive signal U2 '. That is, the drive signal U2 'transformed to the level of the regulated voltage VREG is applied as the gate voltage to the gate electrode of the NMOS field effect transistor M2 on the sink side. Since the same applies to the sink-side inverter circuits 144 and 146, the description thereof is omitted.

  FIG. 4 is a diagram showing the relationship between the boost voltage VG, the regulated voltage VREG, and the gate breakdown voltage VB with respect to the power supply voltage VCC. As shown in FIG. 4, the level of the regulated voltage VREG is proportional to the level of the power supply voltage VCC until the upper limit is limited by the limiter circuit. On the other hand, the levels of the regulated voltage VREG and the gate withstand voltage VB are always constant with respect to the level of the power supply voltage VCC.

  Further, the relationship among the levels of the power supply voltage VCC, the boosted voltage VG, the regulated voltage VREG, and the gate withstand voltage VB is classified into the following first pattern and second pattern. The normal level of the power supply voltage VCC is “3V”, the regulated voltage VREG is “3.5V”, and the gate withstand voltage VB is “10V”. The upper limit value of the boosted voltage VG set so as not to exceed the gate breakdown voltage VB is “9V”.

  First, as the first pattern, when the power supply voltage VCC is “2 V”, the boosted voltage VG is “4 V” which is not limited by the gate withstand voltage VB and is twice the power supply voltage VCC. Therefore, the relationship of “VCC (2 V) <VREG (3.5 V) <VG (4 V) <VB (10 V)” is established. Next, as the second pattern, when the power supply voltage VCC is “6V”, the boosted voltage VG is “12V”, which is double “6V”, but is limited by the gate withstand voltage VB and becomes “9V”. . Accordingly, the relationship of “VREG (3.5 V) <VCC (6 V) <VG (9 V) <VB (10 V)” is established.

<<< Effects of the Present Invention >>>
In the present invention, even if the level of the power supply voltage VCC changes, a constant regulated voltage VREG is always used as the gate voltage of the field effect drive transistor, and the gate voltage is always limited so as not to exceed the gate breakdown voltage. It can be applied. Thereby, when the level of the power supply voltage VCC is lowered, a gate voltage for reliably turning on the NMOS field effect transistors M1 to M6 can be applied to the gate electrodes of the NMOS field effect transistors M1 to M6. On the contrary, when the level of the power supply voltage VCC is increased, the gate voltage applied to the gate electrodes of the NMOS field effect transistors M1 to M6 is limited so as not to exceed the gate breakdown voltage. Failure can be prevented beforehand. As described above, the range of the power supply voltage VCC in which the on / off operations of the NMOS field effect transistors M1 to M6 are stably performed can be expanded.

  In the present invention, the boosted voltage VG is used as the gate voltages (drive signals U1 ', V1', W1 ') of the NMOS field effect transistors M1, M3, M5. That is, when the NMOS field effect transistors M1, M3, and M5 are turned on, the source voltages of the NMOS field effect transistors M1, M3, and M5 are approximated to the power supply voltage VCC applied to the VM terminal. At this time, in order to reliably turn on the NMOS field effect transistors M1, M3, and M5, it is necessary to raise the gate-source voltage Vgs of the NMOS field effect transistors M1, M3, and M5 to a level higher than the power supply voltage VCC. . Therefore, in the present invention, the boosted voltage VG that is higher than the power supply voltage VCC is used as the gate voltage of the NMOS field effect transistors M1, M3, and M5. However, the boosted voltage VG is restricted so as not to exceed the gate breakdown voltage VB of the NMOS field effect transistors M1, M3, and M5. Therefore, even if the power supply voltage VCC becomes high, the boosted voltage VG applied to the gate electrodes of the NMOS field effect transistors M1, M3, and M5 does not exceed the gate breakdown voltage VB.

  Further, in the present invention, the regulated voltage VREG is used as the gate voltages (drive signals U2 ', V2', W2 ') of the NMOS field effect transistors M2, M4, M6. In the conventional case, the gate voltage is a regulated voltage lower than the power supply voltage VCC obtained by regulating the power supply voltage VCC or the power supply voltage VCC itself. However, when it is necessary to lower the level of the power supply voltage VCC in accordance with PAM (Pulse Amplitude Modulation) control or the like, in the conventional case, the level of the gate voltage is lowered as the level of the power supply voltage VCC is lowered. It was difficult to turn on and off the NMOS field effect transistors M2, M4, and M6. Therefore, in the present invention, the regulated voltage VREG regulated from the boosted voltage VG is used as the gate voltage of the NMOS field effect transistors M2, M4, and M6. Thus, a gate voltage (regulated voltage VREG) that can reliably turn on the NMOS field effect transistors M2, M4, and M6 is applied to the gate electrodes of the NMOS field effect transistors M2, M4, and M6. It has become possible. However, the regulated voltage VREG is restricted so as not to exceed the gate breakdown voltage VB of the NMOS field effect transistors M2, M4, and M6. As a result, even when the power supply voltage VCC becomes high, it is possible to apply a gate voltage (regulated voltage VREG) that does not exceed the gate breakdown voltage VB to the gate electrodes of the NMOS field effect transistors M2, M4, and M6. It became.

  Furthermore, in the present invention, the boosted voltage VG is used as the operating voltage of the comparator 120 for generating the FG signal, not the power supply voltage VCC in the conventional case. By the way, the comparator 120 generates a rectangular wave-like FG signal whose edge is switched at a zero cross point where the coil voltage (one of Vu, Vv, Vw) selected in the switch circuit 110 and the neutral point voltage Vcom intersect. is there. The FG signal is used by the sensorless logic circuit 130 to generate the drive signals U1, U2, V1, V2, W1, and W2 when the sensorless motor is activated. Then, if the level of the power supply voltage VCC is lowered, in the conventional case, it becomes difficult to generate the FG signal in the comparator 120, and the sensorless motor may not start. Therefore, in the present invention, since the boosted voltage VG is used as the operating voltage of the comparator 120, the comparator 120 can stably generate the FG signal even if the level of the power supply voltage VCC is lowered. It becomes possible to start stably.

  In the above-described embodiment, not only the NMOS field effect transistors M1 to M6 described above but also PMOS field effect transistors can be used as the source side transistor and the sink side transistor for controlling the coil current flowing in the drive coil of the sensorless motor. It is. However, in order to reduce the size of the sensorless motor driving circuit 100, it is preferable to employ NMOS field effect transistors for both the source side transistor and the sink side transistor.

  Further, the sensorless motor is not limited to the above-described three-phase motor but may be a single-phase motor. In this case, the source side transistor and the sink side transistor are H-bridge connected to the motor coil of the single phase motor.

  Furthermore, the sensorless motor is not limited to the sensorless motor described above, but may be a motor with a sensor including a Hall element. However, when the present invention is applied to a fan motor system for cooling a CPU, it is preferable to employ a sensorless motor and further a sensorless motor driving circuit 100 that can be easily downsized as compared with a motor with a sensor.

It is the figure which showed the whole structure of the sensorless motor drive circuit which concerns on this invention. It is a wave form diagram of the main signal of the sensorless motor drive circuit concerning the present invention. It is a figure showing composition of a predrive circuit concerning the present invention. It is the figure which showed the relationship of the boost voltage with respect to the power supply voltage which concerns on this invention, a regulated voltage, and a gate withstand voltage.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Sensorless motor drive circuit 110 Switch circuit 120 Comparator 125 Start-up counter 130 Sensorless logic circuit 140 Predrive circuit 150 Reference voltage generation circuit 160 Oscillator 180 Charge pump circuit 190 Regulate circuit 400 Microcomputer

Claims (4)

In a motor drive circuit for performing motor control by controlling on / off control of a field effect type drive transistor connected to a drive coil included in a motor and controlling a coil current flowing in the drive coil,
A drive control circuit having a first level corresponding to a power supply voltage and generating a drive signal for controlling on / off of the drive transistor;
A charge pump circuit that generates a boosted voltage of a second level higher than the first level based on the power supply voltage;
A regulation circuit that generates a regulated voltage in which the boosted voltage is regulated from the second level to a third level that is higher than the first level and lower than the second level;
An inverter circuit for generating a gate voltage to transform the drive signal from the first level to the third level and apply the drive signal to a gate electrode of the drive transistor;
A motor drive circuit comprising: The motor drive circuit according to claim 1,
The drive transistor includes a discharge-side transistor that discharges a coil current to the drive coil, and a suction-side transistor that sucks a coil current flowing through the drive coil.
The inverter circuit is
A discharge-side inverter circuit that generates a first gate voltage to be applied to the gate electrode of the discharge-side transistor by transforming the drive signal for controlling on / off of the discharge-side transistor from the first level to the second level. When,
A suction-side inverter circuit that generates a second gate voltage to be applied to the gate electrode of the suction-side transistor by transforming the drive signal for controlling on / off of the suction-side transistor from the first level to the third level. When,
A motor drive circuit comprising: The motor drive circuit according to claim 1,
The motor is a sensorless motor having a drive coil of a plurality of phases,
A binarization circuit that outputs a binarized signal that is binarized from a rotation signal having a frequency corresponding to the rotation speed of the sensorless motor obtained from the sensorless motor, and capable of operating when the boosted voltage is applied; A counter that counts a predetermined count period longer than the edge interval of the binarized signal and resets the count of the predetermined count period at the timing of the edge of the binarized signal,
When the sensorless motor is started, the drive control circuit performs control to switch energization of each phase of the drive coil when the counter counts the predetermined count period. Integrated with a predetermined terminal for connecting a drive coil included in the motor, and controlling the motor by controlling on / off of a field effect type drive transistor for flowing a coil current to the drive coil. In the motor drive circuit,
A drive control circuit having a first level corresponding to a power supply voltage and generating a drive signal for controlling on / off of the drive transistor;
A charge pump circuit that generates a boosted voltage of a second level higher than the first level based on the power supply voltage;
A regulation circuit that generates a regulated voltage in which the boosted voltage is regulated from the second level to a third level that is higher than the first level and lower than the second level;
An inverter circuit for generating a gate voltage to transform the drive signal from the first level to the third level and apply the drive signal to a gate electrode of the drive transistor;
A motor drive circuit comprising:

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