JP2008258423A - Semiconductor device, and manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing a difference of a threshold voltage depending on a gate length of a silicide gate electrode. <P>SOLUTION: A semiconductor device comprises: a semiconductor substrate 11; a channel region 15a wherein an impurity is doped on a surface of the semiconductor substrate 11; a channel region 15b wherein an impurity is doped on the surface of the semiconductor substrate 11 and an impurity concentration is lower than that in the channel region 15a; a gate electrode 25a which is formed on the channel region 15a via a gate insulating film 23 with a large gate length and is constituted of silicide as a whole; and a gate electrode 25b which is formed on the channel region 15b via a gate insulating film with a small gate length and is constituted of silicide as a whole. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  Conventionally, it is well known to use silicide for a gate electrode as a kind of metal gate electrode. Silicide is formed in advance by forming a dummy gate electrode with polysilicon, forming the source / drain of MISFET (Metal Insulator Semiconductor Field Effect Transistor), and then diffusing the metal that becomes the silicide material into the polysilicon to completely silicide it. A (fully silicided) gate electrode is formed. Since silicide can be formed by a technique close to the existing MISFET formation, it is easier to apply compared to other metal gate materials.

  However, when the gate electrode dimension in the gate length direction is different, silicide having a different composition ratio between metal and silicon may appear or full silicidation may not occur. If the silicide composition is different, gate electrodes having different work functions depending on the gate length are formed, and the threshold voltage of the MISFET is different, making it difficult to obtain desired characteristics.

  Therefore, a semiconductor device capable of spreading metal regardless of the dimensions of the gate electrode is disclosed (for example, see Patent Document 1). For example, the disclosed semiconductor device includes a semiconductor substrate, a gate insulating film, a first gate electrode, and a second gate electrode, and the second gate electrode has an area larger than that of the first gate electrode. Although the gate length is large, that is, when the depth is constant, the second gate electrode is formed thinner than the first gate electrode.

In the disclosed semiconductor device, it is considered that both the first gate electrode and the second gate electrode can achieve full silicidation at a certain point in time. However, in the case of a semiconductor device having a plurality of gate lengths, it is necessary to adjust a plurality of film thicknesses of the gate electrode in accordance with the gate length, which causes a problem that the manufacturing process of the semiconductor device becomes complicated. On the other hand, there is no disclosure of a technique for dealing with a difference in threshold voltage or the like when a reaction between metal and silicon progresses and silicide having a different composition depending on the gate length appears.
Japanese Patent Laying-Open No. 2006-140320 (page 6, FIG. 4)

  The present invention provides a semiconductor device and a semiconductor device manufacturing method capable of reducing a difference in threshold voltage depending on the gate length of a silicide gate electrode.

  A semiconductor device of one embodiment of the present invention includes a semiconductor substrate, a first channel region in which impurities are doped on a surface of the semiconductor substrate, and impurities in the surface of the semiconductor substrate. A second channel region having a low concentration; a first gate electrode having a large gate length formed on the first channel region through a gate insulating film; and made entirely of silicide; and the second channel region And a second gate electrode having a small gate length and entirely made of silicide, which is formed via a gate insulating film.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a first channel region and a second channel region having an impurity concentration lower than that of the first channel region on a surface of a semiconductor substrate; A first silicon material film to be a first gate electrode is formed on the first channel region via a gate insulating film, and a gate insulating film is formed on the second channel region. A step of forming a second silicon material film to be a second gate electrode having a gate length smaller than that of the first silicon material film, and a side portion of the first and second silicon material films. Forming a source / drain region spaced from each other across the first and second channel regions, depositing a metal in contact with the first and second silicon material films, 1st and 2nd series And emission material layer is combined with the metal, respectively, the whole is characterized by comprising the step of substantially silicided first and second gate electrodes are formed.

  ADVANTAGE OF THE INVENTION According to this invention, it is possible to provide the semiconductor device which can reduce the difference in the threshold voltage depending on the gate length of a silicide gate electrode, and the manufacturing method of a semiconductor device.

  Embodiments of the present invention will be described below with reference to the drawings. In each figure, the same components are denoted by the same reference numerals.

  A semiconductor device and a method for manufacturing the semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view schematically showing the structure of a semiconductor device. FIG. 2 is a structural cross-sectional view schematically showing the semiconductor device manufacturing method in the order of steps. FIG. 3 is a structural cross-sectional view schematically showing the semiconductor device manufacturing method in the order of steps, following FIG. 2. FIG. 4 is a structural cross-sectional view schematically showing the semiconductor device manufacturing method in the order of steps, following FIG. 3. FIG. 5 is a structural cross-sectional view schematically showing the semiconductor device manufacturing method in the order of steps, following FIG. 4. FIG. 6 is a structural cross-sectional view schematically showing the semiconductor device manufacturing method in the order of steps, following FIG. 5.

  As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 11, a channel region 15 a that is a first channel region in which impurities are doped on the surface of the semiconductor substrate 11, and impurities on the surface of the semiconductor substrate 11. A channel region 15b, which is a second channel region having an impurity concentration lower than that of the channel region 15a, and a first gate formed on the channel region 15a via the gate insulating film 23 and having a large gate length and made entirely of silicide. A gate electrode 25a which is an electrode and a gate electrode 25b which is a second gate electrode made of silicide and having a small gate length formed on the channel region 15b via a gate insulating film are provided.

  The semiconductor substrate 11 is, for example, a silicon substrate having an element formation region on the surface. The region including the channel regions 15a and 15b of the n-channel MISFET (hereinafter referred to as n-MISFET. Similarly, the p-MISFET) is doped with impurities such as boron or indium, and the channel region 15a of the p-MISFET. The region including 15b is formed by doping impurities such as arsenic, phosphorus, or antimony. The impurity concentration in the region (A region or [A]) where the MISFET is formed has a large gate length (the length of the gate electrode in the gate length direction is referred to as the gate length) (for example, about 100 nm or more). For example, it is about twice the impurity concentration of the region (B region or [B]) where the MISFET is formed.

  The element formation region of the semiconductor substrate 11 is isolated by the element isolation region 13. In the element formation region, a source or drain extension region (hereinafter referred to as an extension region 17) on the side close to the gate insulating film 23, and a source / drain which is in contact with the extension region 17 and becomes a source or drain on the side far from the gate insulating film 23 Regions 19 are formed on both sides of the channel regions 15a and 15b so as to be separated from each other. A silicide 21 having at least one of nickel, cobalt, and palladium is formed on the surface of the source / drain region 19.

A gate insulating film 23 is formed on the upper surfaces of the channel regions 15a and 15b. The gate insulating film 23 is a high dielectric insulating film including a silicon oxynitride film (SiON), a hafnium oxide film (HfO ₂ ), a hafnium silicon oxynitride film (HfSiON), and the like.

The gate electrode 25a in the region A is full silicide and is made of, for example, NiSi having a relatively small metal composition ratio with respect to silicon. On the other hand, the gate electrode 25b in the B region is full silicide and has a relatively large metal composition ratio with respect to silicon, for example, Ni ₂ Si. The gate electrode 25a may be a main silicide of NiSi in which silicon is 1 and nickel is approximately 1, and the gate electrode 25b is Ni _x Si _y in which silicon is 1 and nickel is 2 or more. (X ≧ 2y) may be a main silicide. The gate electrode 25a is formed with a gate length of, for example, about 180 nm, and the gate electrode 25b is formed with a gate length of, for example, about 40 nm.

  A sidewall insulating film 31 made of a silicon nitride film is formed on both sides of the gate electrodes 25 a and 25 b and the gate insulating film 23, and on the extension region 17 and the source / drain region 19. The sidewall insulating film 31 may be a silicon oxide film or a laminated structure of a silicon nitride film and a silicon oxide film.

  A liner film 33 made of a silicon nitride film or the like is formed so as to cover the gate electrodes 25a and 25b, the sidewall insulating film 31, the surface of the semiconductor substrate 11, and the like. An interlayer insulating film 41 made of a silicon oxide film or the like is formed on the liner film 33. Although not shown, the semiconductor device 1 is formed so as to penetrate the interlayer insulating film 41 and the liner film 33 and the like so that the contact plug is connected to the silicide film 21. Layers and the like are formed.

  Next, a method for manufacturing the semiconductor device 1 will be described. As shown in FIG. 2A, the element isolation region 13 is formed on the semiconductor substrate 11. Hereinafter, in each figure, the A region having a large gate length is indicated by [A], and the B region having a small gate length is indicated by [B].

  As shown in FIG. 2B, a silicon oxide film 51 is formed on the surface of the semiconductor substrate 11, and ion implantation for forming a well is performed.

  As shown in FIG. 2C, a photoresist 53 is applied, and patterning is performed so that the photoresist 53 in the region A remains. Thereafter, ion implantation (in the direction of the arrow) is performed to form a channel having a large role in determining the threshold voltage of the element in the B region. Impurities such as boron or indium are ion-implanted into the region that becomes the channel of the n-MISFET, and impurities such as arsenic, phosphorus, or antimony are ion-implanted into the region that becomes the channel of the p-MISFET.

  As shown in FIG. 2D, after removing the photoresist 53, a photoresist 55 is applied and patterning is performed so that the photoresist 55 in the B region remains. Thereafter, ion implantation (in the direction of the arrow) is performed to form a channel having a large role in determining the threshold voltage of the element in the A region. Similar to the B region, an impurity such as boron or indium is ion-implanted into a region that becomes a channel of the n-MISFET, and an impurity such as arsenic, phosphorus, or antimony is ion-implanted into a region that becomes a channel of the p-MISFET. Either ion implantation in the A region or the B region can be performed first.

  Here, the ion implantation conditions are set so that the impurity concentration of the A region is larger than the impurity concentration of the B region having the same kind of impurities in the channel region, for example, twice or more. Then, after the photoresist 55 is removed, the ion-implanted impurities in the well and channel regions are activated.

As shown in FIG. 3A, the silicon oxide film 51 is removed, and an insulating film 123 made of a high-dielectric insulating film containing SiON, HfO ₂ , HfSiON, or the like that becomes the gate insulating film 23 is formed on the surface of the semiconductor substrate 11. Form.

As shown in FIG. 3B, a polysilicon film 125 to be the gate electrode 25 is grown on the insulating film 123. Then, an impurity such as arsenic or phosphorus is ionized in the region of the polysilicon film 125 to be an n-MISFET, and an impurity such as boron or boron fluoride (BF ₂ ) is ionized in the region of the polysilicon film 125 to be a p-MISFET. inject. Thereafter, a silicon nitride film 58 is formed as a processing mask material for making the polysilicon film 125 into a gate electrode shape. The polysilicon film 125 can be replaced with an amorphous silicon film.

  As shown in FIG. 3C, the silicon nitride film 58 is patterned using a photolithography process, and the polysilicon film 125 is processed through a RIE (Reactive Ion Etching) process or the like to change the shape of the gate electrode 25. A polysilicon film 125a which is a first silicon material film and a polysilicon film 125b which is a second silicon material film are formed, and the insulating film 123 is processed to form a gate insulating film 23. The silicon nitride film 58 of the mask material is not removed but left.

  As shown in FIG. 3D, in order to form the extension region 17 at a shallow position on the surface of the semiconductor substrate 11, an impurity such as arsenic or phosphorus is used in the case of n-MISFET, and boron is used in the case of p-MISFET. Alternatively, impurities such as boron fluoride are ion-implanted. At this time, in order to suppress punch-through, an impurity such as boron, indium, or boron fluoride is ion-implanted in the case of n-MISFET, and an impurity such as arsenic or phosphorus is ion-implanted in the case of p-MISFET.

  As shown in FIG. 4A, an insulating film such as a silicon nitride film is formed on the entire surface, and then in the RIE process, the silicon nitride film 58, the polysilicon films 125a and 125b, and the gate insulating film 23 side. A sidewall insulating film 31 is formed on the part. The sidewall insulating film 31 may have a multilayer structure in which a silicon oxide film or the like is laminated on the sidewall insulating film 31 as long as the film in contact with the gate electrode is a silicon nitride film.

  As shown in FIG. 4B, impurities such as arsenic or phosphorus in the case of n-MISFET and impurities such as boron or boron fluoride in the case of p-MISFET are ionized in the region to be the source / drain region 19. inject. Thereafter, in order to activate the implanted impurity, annealing is performed, and the extension region 17 and the source / drain region 19 are formed.

  As shown in FIG. 4C, nickel, cobalt, and palladium are formed on the surface of the source / drain region 19 by sputtering, and then annealed to form silicide on the surface of the source / drain region 19. A film 21 is formed. Thereafter, the metal not used for forming the silicide film 21 is removed.

  As shown in FIG. 5A, a silicon nitride film 59 and an insulating film 60 made of a silicon oxide film or the like are sequentially formed, and the surface of the insulating film 60 is planarized by a CMP (Chemical Mechanical Polishing) method or the like. .

  As shown in FIG. 5B, the silicon nitride film 58 and the like on the polysilicon films 125a and 125b are removed in the RIE process.

  As shown in FIG. 5C, the insulating film 60 is removed in the RIE process.

As shown in FIG. 6A, nickel 61 is formed on the entire surface including the upper surfaces of the polysilicon films 125a and 125b by a sputtering method, and then annealed so that nickel on the surfaces of the polysilicon films 125a and 125b and React with silicon. For example, the thickness of the nickel 61 is about 60% of the thickness of the polysilicon films 125a and 125b. In the case of a MISFET having a large gate length, NiSi is mainly formed. On the other hand, in the case of a MISFET having a small gate length, Ni ₂ Si and NixSiy (x> 2y) are mainly formed. That is, the polysilicon films 125a and 125b become the gate electrodes 25a and 25b which are silicided on the entire surface.

  As shown in FIG. 6B, the nickel 61 that has not been silicided on the surface is removed, and a silicon nitride film is deposited on the gate electrodes 25a and 25b, the silicon nitride film 59, and the like. A new silicon nitride film is laminated on the silicon nitride film 59, and a liner film 33 is formed by combining the two. An interlayer insulating film 41 is formed on the liner film 33, and the surface is flattened by a CMP method or the like. Thereafter, although not shown in the figure, a well-known contact plug forming process, a wiring process, etc. are performed, as shown in FIG. Thus, the semiconductor device 1 is completed.

As described above, the semiconductor device 1 includes the channel region 15a in which the surface of the semiconductor substrate 11 is doped with impurities, the channel region 15b in which the surface of the semiconductor substrate 11 is doped with impurities and has a lower impurity concentration than the channel region 15a, Formed on the channel region 15a through the gate insulating film 23 and having a large gate length, a fully silicided gate electrode 25a mainly made of NiSi, and formed on the second channel region 15b through the gate insulating film. And a fully silicided gate electrode 25b mainly composed of Ni _x Si _y (x ≧ 2y) having a small gate length.

In other words, the semiconductor device 1 combines the full silicide gate electrode 25a mainly composed of NiSi having a large gate length and the high impurity concentration of the channel region 15a, and the full silicide gate electrode 25b mainly composed of Ni ₂ Si having a small gate length. As a result of combining the low impurity concentration of the channel region 15b, the work function of silicides having different compositions is modulated, and the difference in threshold voltage between the A region and the B region can be reduced. Since the difference in threshold voltage can be reduced, the semiconductor device 1 can be mounted with MISFETs having different gate lengths, and is an easy-to-use semiconductor device.

  In addition, the impurity concentration of the channel region 15a having a large gate length is set to be approximately equal to the impurity concentration of the channel region 15b having a small gate length, with the gate length being, for example, about 100 nm or more or less than about 100 nm. The semiconductor device 1 can be formed relatively easily only by changing the ion implantation conditions when forming the channel regions 15a and 15b so as to be doubled. That is, since the manufacturing method of the semiconductor device 1 does not need to greatly change the manufacturing process of the conventional semiconductor device, the manufacturing method of the semiconductor device 1 can suppress a decrease in manufacturing yield.

  The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

Sectional drawing which shows typically the structure of the semiconductor device which concerns on the Example of this invention. Sectional drawing which shows typically the manufacturing method of the semiconductor device which concerns on the Example of this invention in order of a process. FIG. 3 is a structural cross-sectional view schematically showing a manufacturing method subsequent to FIG. 2 for a semiconductor device according to an example of the present invention in order of steps. FIG. 4 is a structural cross-sectional view schematically showing the manufacturing method subsequent to FIG. 3 for the semiconductor device according to the example of the present invention in order of steps. FIG. 5 is a structural cross-sectional view schematically showing a method for manufacturing the semiconductor device according to the embodiment of the present invention following FIG. FIG. 6 is a structural cross-sectional view schematically showing a manufacturing method subsequent to FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Semiconductor substrate 13 Element isolation region 15a, 15b Channel region 17 Extension region 19 Source / drain region 21 Silicide film 23 Gate insulating film 25a, 25b Gate electrode 31 Side wall insulating film 33 Liner film 41 Interlayer insulating film 51 Silicon oxide film 53, 55 Photoresist 58, 59 Silicon nitride film 60, 123 Insulating film 61 Nickel 125, 125a, 125b Polysilicon film

Claims (5)

A semiconductor substrate;
A first channel region doped with impurities on the surface of the semiconductor substrate;
A second channel region doped with impurities on the surface of the semiconductor substrate and having a lower impurity concentration than the first channel region;
A first gate electrode having a large gate length formed on the first channel region via a gate insulating film and made entirely of silicide;
A second gate electrode having a small gate length formed on the second channel region through a gate insulating film and made entirely of silicide;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the main silicide of the first gate electrode has a metal composition ratio with respect to silicon smaller than that of the main silicide of the second gate electrode.   The main silicide of the first gate electrode is about 1 for nickel with respect to silicon, and the main silicide of the second gate electrode is about 2 for nickel with respect to silicon. The semiconductor device according to claim 1 or 2.   4. The semiconductor device according to claim 1, wherein an impurity concentration of the first channel region is approximately twice or more than an impurity concentration of the second channel region. 5. Forming a first channel region and a second channel region having an impurity concentration lower than that of the first channel region on a surface of the semiconductor substrate;
A first silicon material film to be a first gate electrode is formed on the first channel region via a gate insulating film, and a gate insulating film is formed on the second channel region. A step of forming a second silicon material film to be a second gate electrode having a gate length smaller than that of the first silicon material film,
Forming source and drain regions spaced apart from each other across the first and second channel regions, respectively, on the side portions of the first and second silicon material films;
A metal is deposited on and in contact with the first and second silicon material films, and the first and second silicon material films combine with the metal, respectively, so that the whole is substantially silicided. Forming first and second gate electrodes;
A method for manufacturing a semiconductor device, comprising:

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