JP2006339172A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which impairment of electron mobility can be reduced while suppressing the depletion of a gate electrode. <P>SOLUTION: The semiconductor device comprises a pair of n-type source/drain regions 6a formed at a predetermined interval to hold a p-channel region 5a between, a gate electrode 8a formed on the p-channel region 5a through a gate insulation film 7a and including a polysilicon layer 10a and a metal containing layer 9a formed in the vicinity of the interface between the polysilicon layer 10a and the gate insulation film 7a, a pair of p-type source/drain regions 6b formed at a predetermined interval to hold a n-channel region 5b between, and a gate electrode 8b formed on the n-channel region 5b through a gate insulation film 7b and including a polysilicon layer 10b and a metal containing layer 9b formed in the vicinity of the interface between the polysilicon layer 10b and the gate insulation film 7b. The metal containing layers 9a and 9b contain Pt and TaN. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a first conductivity type source / drain region and a second conductivity type source / drain region.

  Conventionally, it has an n-channel MOS transistor having an n-type source / drain region and a gate electrode made of an n-type polysilicon layer, and a gate electrode made of a p-type source / drain region and a p-type polysilicon layer. A dual gate CMOS (Complementary Metal Oxide Semiconductor) composed of a p-channel MOS transistor is known. In this conventional dual gate CMOS, the gate electrodes of the n-channel MOS transistor and the p-channel MOS transistor are formed of the polysilicon layer, so that the gate electrode is depleted. Therefore, a dual gate CMOS capable of solving the problem of depletion of the gate electrode has been proposed (for example, see Patent Document 1).

  In the dual gate CMOS proposed in Patent Document 1, the gate electrode of the n-channel MOS transistor and the p-channel MOS transistor is formed of a metal layer, thereby depleting the gate electrode made of semiconductor (polysilicon). It has been resolved.

JP 2004-165346 A

  However, in the dual gate CMOS proposed in the above-mentioned Patent Document 1, the gate electrodes of the n-channel MOS transistor and the p-channel MOS transistor are each formed by only the metal layer. There is a disadvantage that the difference in thermal expansion coefficient between the electrode and the substrate on which the gate insulating film and the source / drain regions are formed becomes large. As a result, the stress acting between the gate electrode, the gate insulating film and the substrate increases, and this causes a problem that the electron mobility in the substrate deteriorates due to this stress.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to reduce deterioration of electron mobility while suppressing depletion of the gate electrode. A semiconductor device is provided.

Means for Solving the Problems and Effects of the Invention

  In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a pair of first conductivity type first electrodes formed at a predetermined interval so as to sandwich a first channel region on a main surface of a semiconductor region. A first source / drain region and a first channel region are formed on the first channel region via a first gate insulating film, and are formed in the vicinity of the interface between the first semiconductor layer and the first semiconductor layer and the first gate insulating film. A first gate electrode including a metal-containing layer; a pair of second source / drain regions of a second conductivity type formed at a predetermined interval so as to sandwich the second channel region on the main surface of the semiconductor region; A second semiconductor layer formed on the second channel region via a second gate insulating film, and including a second metal-containing layer formed in the vicinity of the interface between the second semiconductor layer and the second gate insulating film 2 gate electrodes. In addition, at least one of the first metal-containing layer and the second metal-containing layer includes a plurality of metals.

  In the semiconductor device according to this aspect, as described above, the first gate electrode includes the first semiconductor layer and the first metal-containing layer formed in the vicinity of the interface between the first semiconductor layer and the first gate insulating film. And the second gate electrode includes a second semiconductor layer and a second metal-containing layer formed in the vicinity of the interface between the second semiconductor layer and the second gate insulating film. Unlike the case where the first and second gate electrodes are configured only by the semiconductor layer formed on the gate insulating film, depletion of the first and second gate electrodes can be suppressed. The first gate electrode includes a first semiconductor layer and a first metal-containing layer formed in the vicinity of the interface between the first semiconductor layer and the first gate insulating film, and the second gate electrode includes By including the second semiconductor layer and the second metal-containing layer formed in the vicinity of the interface between the second semiconductor layer and the second gate insulating film, the first and second gate electrodes have the same thickness. The stress acting between the metal-containing layer, the gate insulating film, and the semiconductor region can be reduced as compared with the case where the gate electrode is formed using only the metal-containing layer. Thereby, it is possible to reduce the deterioration of electron mobility due to the stress acting between the metal-containing layer and the gate insulating film and the semiconductor region. In addition, the thickness of the metal-containing layer can be reduced as compared with the case where the gate electrode having the same thickness as the first and second gate electrodes is formed only by the metal-containing layer. Thereby, since processing (patterning) by etching of the metal-containing layer is facilitated, the gate electrode can be easily patterned even when the gate electrode including the metal-containing layer is used.

  Further, in one aspect, by configuring at least one of the first metal-containing layer and the second metal-containing layer to include a plurality of metals, for example, the plurality of metals included in the first metal-containing layer may be A metal that forms a level in the vicinity of an energy level (mid gap) between the conduction band and valence band of one semiconductor layer, and a metal that forms a level closer to the conduction band than the mid gap of the first semiconductor layer; Since the metal that forms a level closer to the conduction band than the mid gap of the first semiconductor layer can facilitate fixing the Fermi level of the first gate electrode to the level closer to the conduction band. It is possible to suppress the Fermi level of the first gate electrode from being pinned to the vicinity of the mid gap by the metal forming a level in the vicinity of the mid gap of the first semiconductor layer. In addition, a plurality of metals contained in the second metal-containing layer are formed with a metal that forms a level near the midgap of the second semiconductor layer and a level closer to the valence band than the midgap of the second semiconductor layer. The metal that forms a level closer to the valence band side than the mid gap of the second semiconductor layer makes it easy to fix the Fermi level of the second gate electrode to the level on the valence band side. Therefore, it is possible to suppress the Fermi level of the second gate electrode from being pinned to the vicinity of the mid gap by the metal that forms a level in the vicinity of the mid gap of the second semiconductor layer. As described above, in at least one of the first gate electrode and the second gate electrode, the Fermi level can be suppressed from being pinned in the vicinity of the mid gap of the first semiconductor layer or the second semiconductor layer. It is possible to suppress the work function of at least one of the gate electrode and the second gate electrode from being fixed to the work function corresponding to the vicinity of the mid gap of the first semiconductor layer or the second semiconductor layer.

  In the semiconductor device according to the above aspect, the first metal-containing layer and the second metal-containing layer are preferably formed so as to partially cover the first gate insulating film and the second gate insulating film, respectively. The first semiconductor layer and the second semiconductor layer are respectively a portion not covered with the first metal-containing layer of the first gate insulating film and a portion not covered with the second metal-containing layer of the second gate insulating film. It is formed so that it may contact. With this configuration, the first and second metals can be easily formed by the first metal-containing layer and the second metal-containing layer formed so as to partially cover the first gate insulating film and the second gate insulating film. Since stress acting between the containing layer, the gate insulating film, and the semiconductor region can be reduced, deterioration of electron mobility caused by the stress can be easily reduced.

  Further, the first semiconductor layer and the second semiconductor layer are respectively a portion not covered with the first metal-containing layer of the first gate insulating film and a portion not covered with the second metal-containing layer of the second gate insulating film. The contact area between the first and second semiconductor layers and the gate insulating film can be reduced. Accordingly, the first and second semiconductor layers are formed of a material containing silicon, and the gate insulating film is also formed of a high dielectric constant material containing a metal and is included in the first and second semiconductor layers. Pinning due to the reaction between silicon and the metal contained in the high dielectric constant material of the gate insulation film is less likely to occur, so it is difficult to adjust the work function of the gate electrode due to pinning. can do. In this case, the work function of the gate electrode can be adjusted by introducing impurities of a predetermined conductivity type into the first and second semiconductor layers that are in contact with the gate insulating film.

  In the configuration in which the first metal-containing layer and the second metal-containing layer are formed so as to partially cover the first gate insulating film and the second gate insulating film, preferably the first metal-containing layer and the second metal The containing layer is formed in a dot shape. If comprised in this way, a 1st metal containing layer and a 2nd metal containing layer can be easily formed so that a 1st gate insulating film and a 2nd gate insulating film may be covered partially.

  In the semiconductor device according to the above aspect, the first metal-containing layer and the second metal-containing layer preferably include the same plurality of metals. If comprised in this way, since the 1st metal content layer and the 2nd metal content layer can be formed simultaneously by patterning the layer containing the same some metal, the 1st and 2nd metal content layer is formed. The manufacturing process can be simplified.

  In the semiconductor device according to the above aspect, the first source / drain region is preferably n-type, the second source / drain region is p-type, and the first gate insulating film is the first semiconductor layer. Including a metal that forms a level on the conduction band side with respect to an energy level intermediate between the conduction band and the valence band of the second semiconductor layer, and the second metal-containing layer is intermediate between the conduction band and the valence band of the second semiconductor layer. It contains a metal that forms a level on the valence band side of the energy level. If comprised in this way, by the metal which forms a level in the conduction band side rather than the intermediate energy level (mid gap) of the conduction band and valence band of the 1st semiconductor layer contained in the 1st gate insulating film, It is possible to easily fix the Fermi level of the first gate electrode of the n-channel transistor including the n-type first source / drain region to the level on the conduction band side of the first semiconductor layer. As a result, the work function of the first gate electrode of the n-channel transistor can be adjusted to be reduced, so that the threshold voltage of the n-channel transistor can be adjusted to be lowered. Further, the p-type first metal is formed by a metal that forms a level closer to the valence band side than the energy level (mid gap) between the conduction band and the valence band of the second semiconductor layer included in the second metal-containing layer. The Fermi level of the second gate electrode of the p-channel transistor including the two source / drain regions can be easily fixed to the valence band side level of the second semiconductor layer. As a result, the work function of the second gate electrode of the p-channel transistor can be adjusted to increase, so that the threshold voltage of the p-channel transistor can be adjusted to decrease. As described above, in the semiconductor device including the n-channel transistor and the p-channel transistor, the threshold voltages of both the n-channel transistor and the p-channel transistor can be adjusted to decrease.

  In the semiconductor device according to the above aspect, the first source / drain region is preferably n-type, the second source / drain region is p-type, and the first metal-containing layer is the first semiconductor layer. Including a metal that forms a level on the conduction band side with respect to an energy level intermediate between the conduction band and the valence band of the second semiconductor layer, and the second metal-containing layer is intermediate between the conduction band and the valence band of the second semiconductor layer. It contains a metal that forms a level on the valence band side of the energy level. If comprised in this way, by the metal which forms a level in the conduction band side rather than the intermediate energy level (mid gap) of the conduction band and valence band of the 1st semiconductor layer contained in the 1st metal content layer, It is possible to easily fix the Fermi level of the first gate electrode of the n-channel transistor including the n-type first source / drain region to the level on the conduction band side of the first semiconductor layer. As a result, the work function of the first gate electrode of the n-channel transistor can be adjusted to be reduced, so that the threshold voltage of the n-channel transistor can be adjusted to be lowered. Further, the p-type first metal is formed by a metal that forms a level closer to the valence band side than the energy level (mid gap) between the conduction band and the valence band of the second semiconductor layer included in the second metal-containing layer. The Fermi level of the second gate electrode of the p-channel transistor including the two source / drain regions can be easily fixed to the valence band side level of the second semiconductor layer. As a result, the work function of the second gate electrode of the p-channel transistor can be adjusted to increase, so that the threshold voltage of the p-channel transistor can be adjusted to decrease. As described above, in the semiconductor device including the n-channel transistor and the p-channel transistor, the threshold voltages of both the n-channel transistor and the p-channel transistor can be adjusted to decrease.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, a CMOS as an example of a semiconductor device according to the present invention will be described as an example.

  FIG. 1 is a cross-sectional view illustrating a structure of a CMOS according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view showing the structure of the n-channel MOS transistor portion of the CMOS according to the embodiment shown in FIG. First, the structure of a CMOS according to an embodiment of the present invention will be described with reference to FIGS.

In the CMOS according to the present embodiment, a buried oxide film 2 having a thickness of about 200 nm is formed on a silicon substrate 1 as shown in FIG. In a predetermined region on the buried oxide film 2, a single crystal silicon layer 3 as an SOI (Silicon on Insulator) layer having a thickness of about 100 nm is formed in an island shape. The single crystal silicon layer 3 is an example of the “semiconductor region” in the present invention. An element isolation insulating film 4 made of an SiO ₂ film reaching the buried oxide film 2 is formed so as to surround the single crystal silicon layer 3.

Further, in the formation region of the n-channel MOS transistor 50a constituting the CMOS according to the present embodiment, the single crystal silicon layer 3 has a pair of n-type sources spaced apart from each other by a predetermined distance so as to sandwich the p-type channel region 5a. / Drain region 6a is formed. The p-type channel region 5a is an example of the “first channel region” in the present invention, and the n-type source / drain region 6a is an example of the “first source / drain region” in the present invention. . A gate insulating film 7a is formed on the p-type channel region 5a. The gate insulating film 7a is an example of the “first gate insulating film” in the present invention. The gate insulating film 7a is formed of an SiO ₂ film or an HfO ₂ film that is a high dielectric constant (High-k) insulating film. This HfO ₂ film has a relative dielectric constant higher than 3.9. When the gate insulating film 7a is made of an SiO ₂ film, the SiO ₂ film has a thickness of about 6 nm or less. When the gate insulating film 7a is made of an HfO ₂ film, the HfO ₂ film has a thickness of about 6 nm or less in terms of oxide film (SiO ₂ film). A gate electrode 8a is formed on the gate insulating film 7a. The gate electrode 8a is an example of the “first gate electrode” in the present invention.

Here, in the present embodiment, the gate electrode 8a includes a metal-containing layer 9a containing Pt and TaN formed on the gate insulating film 7a, and an n ⁺ -type polysilicon layer 10a formed on the metal-containing layer 9a. And is formed by. The metal-containing layer 9a is an example of the “first metal-containing layer” in the present invention, and the polysilicon layer 10a is an example of the “first semiconductor layer” in the present invention. The metal-containing layer 9a has an average film thickness (during film formation) of less than about 3 nm, which is smaller than the average film thickness (about 150 nm) of the polysilicon layer 10a. Thus, by forming the metal-containing layer 9a with a small film thickness, the metal-containing layer 9a is formed in a dot shape so as to partially cover the gate insulating film 7a as shown in FIG. Further, the n ⁺ -type polysilicon layer 10a formed on the metal-containing layer 9a is not covered with the metal-containing layer 9a of the gate insulating film 7a through the region between adjacent dots of the metal-containing layer 9a. Touching part. The p-type channel region 5a, the pair of n-type source / drain regions 6a, the gate insulating film 7a, and the gate electrode 8a constitute an n-channel MOS transistor 50a.

On the other hand, in the formation region of the p-channel MOS transistor 50b constituting the CMOS according to the present embodiment, as shown in FIG. 1, the single crystal silicon layer 3 is spaced apart from the n-type channel region 5b by a predetermined interval. A pair of p-type source / drain regions 6b is formed. The n-type channel region 5b is an example of the “second channel region” in the present invention, and the p-type source / drain region 6b is an example of the “second source / drain region” in the present invention. A gate insulating film 7b having the same composition (SiO ₂ or HfO ₂ ) and thickness (about 6 nm or less) as the gate insulating film 7a of the n-channel MOS transistor 50a is formed on the n-type channel region 5b. Has been. The gate insulating film 7b is an example of the “second gate insulating film” in the present invention. A gate electrode 8b is formed on the gate insulating film 7b. The gate electrode 8b is an example of the “second gate electrode” in the present invention.

Here, in this embodiment, the gate electrode 8b is formed on the gate insulating film 7b, and includes a metal-containing layer 9b containing Pt and TaN, which are the same two types of metals as the metal-containing layer 9a of the gate electrode 8a, and a metal The p ⁺ type polysilicon layer 10b is formed on the containing layer 9b. The metal-containing layer 9b is an example of the “second metal-containing layer” in the present invention, and the polysilicon layer 10b is an example of the “second semiconductor layer” in the present invention. The metal-containing layer 9b is configured similarly to the metal-containing layer 9a of the n-channel MOS transistor 50a described above. That is, the metal-containing layer 9b is formed in a dot shape so as to partially cover the gate insulating film 7b. Then, the p ⁺ -type polysilicon layer 10b formed on the metal-containing layer 9b is not covered with the metal-containing layer 9b of the gate insulating film 7b via the region between the dots of the metal-containing layer 9b. It is formed to contact. The n-type channel region 5b, the pair of p-type source / drain regions 6b, the gate insulating film 7b, and the gate electrode 8b constitute a p-channel MOS transistor 50b.

Note that TaN contained in the metal-containing layers 9a and 9b of the gate electrodes 8a and 8b of the n-channel MOS transistor 50a and the p-channel MOS transistor 50b is an intermediate between the conduction band and the valence band of silicon after heat treatment at about 900 ° C. Has an effective work function in the vicinity of the energy level (mid gap). In the n ⁺ -type polysilicon layer 10a of the gate electrode 8a of the n-channel MOS transistor 50a, the Fermi level is located in the vicinity of the conduction band of silicon, while the p ⁺ -type polysilicon of the gate electrode 8b of the p-channel MOS transistor 50b is located. In the silicon layer 10b, the Fermi level is located near the valence band of silicon.

Further, Pt contained in the metal-containing layers 9a and 9b of the gate electrodes 8a and 8b reacts with silicon (Si) of the polysilicon layers 10a and 10b to form a Pt-Si bond, thereby valence electrons of silicon. A level is formed near the band. Further, when the gate insulating film 7a and 7b are made of HfO ₂ film, the HfO ₂ film and Hf and the polysilicon layer 10a and 10b of silicon (Si) and is HfSi metal-containing layer 9a which is formed by the reaction and 9b. In this case, a level is formed in the vicinity of the conduction band of silicon by the Hf-Si bond. Therefore, in the CMOS according to the present embodiment, as shown in FIG. 3, in the vicinity of the interface between the gate electrode 8a (8b) and the gate insulating film 7a (7b), the level D1 due to the Hf-Si bond near the conduction band of silicon. And a level D2 due to the Pt-Si bond is localized near the valence band of silicon. In the n-channel MOS transistor 50a, the gate electrode 8a is composed of the metal-containing layer 9a containing TaN and the n ⁺ -type polysilicon layer 10a, so that the Fermi level of the gate electrode 8a is reduced from the silicon midgap to the energy on the conduction band side. Since the level is easily fixed, the Fermi level of the gate electrode 8a is pinned to the energy level corresponding to the level D1 on the conduction band side among the levels D1 and D2. On the other hand, in the p-channel MOS transistor 50b, the gate electrode 8b is composed of the metal-containing layer 9b containing TaN and the p ⁺ -type polysilicon layer 10b, so that the Fermi level of the gate electrode 8b changes from the silicon midgap to the valence band. The Fermi level of the gate electrode 8b is pinned to an energy level corresponding to the valence band level D2 of the levels D1 and D2.

  When the work function Φm of the polysilicon layer 10a (10b) of the gate electrode 8a (8b) is changed, the effective work function Φm of the gate electrode expected from the gate capacitance-gate voltage (CV) measurement. Eff changes in direct proportion to the work function Φm of the polysilicon layer 10a (10b). However, the level D1 due to the Hf-Si bond is localized near the conduction band of silicon as in the present embodiment, and the level D2 due to the Pt-Si bond is localized near the valence band of silicon. 4, even if the work function of the polysilicon layer 10a (10b) of the gate electrode 8a (8b) is changed, the effective work function Φm · eff of the gate electrode 8a (8b) is changed as shown in FIG. The change is suppressed in the effective work function corresponding to the level D1 near the conduction band and the level D2 near the valence band. Thereby, in the present embodiment, the work function of the gate electrode 8a of the n-channel MOS transistor 50a is adjusted to a work function corresponding to the energy level in the vicinity of the valence band, and the work of the gate electrode 8b of the p-channel MOS transistor 50b is adjusted. The function is adjusted to a work function corresponding to the energy level near the conduction band.

Further, as shown in FIG. 1, SiO having a thickness of about 200 nm so as to cover the element isolation region 4, the n-type source / drain region 6a, the p-type source / drain region 6b, and the gate electrodes 8a and 8b. _An interlayer insulating film 11 composed of _two films is formed. The interlayer insulating film 11 includes a pair of n-type source / drain regions 6a, a pair of p-type source / drain regions 6b, an n ⁺ -type polysilicon layer 10a, and a p ⁺ -type polysilicon layer 10b, respectively. Reaching contact holes 11a, 11b, 11c, 11d, 11e and 11f are formed. Plugs 12a, 12b, 12c, 12d, 13a and 13b made of tungsten are buried in the contact holes 11a, 11b, 11c, 11d, 11e and 11f, respectively.

  A wiring 14 is formed on the interlayer insulating film 11 so as to be connected to the plug 12a, and a wiring 15 is formed so as to connect the plugs 12b and 12c. Thus, one source / drain region 6a of n channel MOS transistor 50a and one source / drain region 6b of p channel MOS transistor 50b are connected via plugs 12b and 12c and wiring 15. A wiring 16 is formed on the interlayer insulating film 11 so as to be connected to the plug 12d. On the interlayer insulating film 11, wirings 17a and 17b are formed so as to be connected to the plugs 13a and 13b, respectively. The gate electrode 8a of the n-channel MOS transistor 50a and the gate electrode 8b of the p-channel MOS transistor 50b are connected through plugs 13a and 13b and wirings 17a and 17b.

  5 to 10 are cross-sectional views for explaining a CMOS manufacturing process according to an embodiment of the present invention. Next, with reference to FIGS. 1 and 5 to 10, a description will be given of a CMOS manufacturing process according to an embodiment of the present invention.

First, as shown in FIG. 5, an SOI substrate is prepared in which a single crystal silicon layer 3 having a thickness of about 100 nm is formed in an island shape on a silicon substrate 1 via a buried oxide film 2 having a thickness of about 200 nm. To do. Then, the photolithography technique and the etching technique are used to remove the single crystal silicon layer 3 located in the element isolation region, and then an SiO ₂ film (not shown) is formed. Then, by removing the excessively deposited portion of the SiO ₂ film by a CMP (Chemical Mechanical Polishing) method or an etch back method, the element isolation insulating film 4 made of the SiO ₂ film as shown in FIG. 5 is formed. .

Next, as shown in FIG. 6, a gate insulating film 7 is formed on the top surfaces of the single crystal silicon layer 3 and the element isolation insulating film 4 using a CVD (Chemical Vapor Deposition) method or a sputtering method. At this time, in this embodiment, the gate insulating film 7 is formed of a high dielectric constant (High-k) insulating film such as a SiO ₂ film or a HfO ₂ film. When the gate insulating film 7 is formed by the SiO ₂ film, the SiO ₂ film is formed to have an approximately 6nm or less in thickness. On the other hand, in the case where the gate insulating film 7 is formed by the HfO ₂ film, the HfO ₂ film is formed to have an oxide film (SiO ₂ film) in terms of film about 6nm or less in thickness in thickness.

  Thereafter, in this embodiment, a TaN film having an average film thickness (at the time of film formation) of about 1 nm is deposited on the gate insulating film 7 using the CVD method, and an average film of less than about 1 nm is formed using the sputtering method. A Pt film having a thickness (during film formation) is deposited. At this time, the TaN film and the Pt film are not deposited in layers on the gate insulating film 7. That is, it is considered that the TaN film and the Pt film are formed on the gate insulating film 7 in a partially mixed state. In this way, the metal-containing layer 9 containing Pt and TaN having an average film thickness (during film formation) of less than about 3 nm is formed on the gate insulating film 7. In the case of forming a Pt film, it is preferable to form a Pt film after forming a protective film (not shown) on the gate insulating film 7 in order to suppress damage to the gate insulating film 7. At this time, in the present embodiment, it is preferable to use a protective film made of a material other than a material containing nitrogen, such as a SiN film, as the protective film (not shown). As a result, Pt is influenced by nitrogen (N) in the SiN film, and an unintended shift of the Fermi level silicon to the mid gap side of the gate electrode 8a (8b) (see FIG. 1) occurs. Is suppressed.

  Thereafter, an amorphous silicon layer 10 having a thickness of about 150 nm is deposited on the metal-containing layer 9 by CVD. The deposition is performed in the deposition of the metal-containing layer 9 and the amorphous silicon layer 10 by the CVD method, the heat treatment for activating impurities introduced into the source / drain regions 6a and 6b and the amorphous silicon layer 10 described later, and other steps. Due to the generated heat, the metal-containing layer 9 is considered to aggregate in a dot shape due to the small average film thickness. Thereby, the metal-containing layer 9 is formed in a dot shape so as to partially cover the gate insulating film 7, and the amorphous silicon layer 10 is formed in the gate via the region between adjacent dots of the metal-containing layer 9. The insulating film 7 is formed so as to be in contact with a portion not covered with the metal-containing layer 9. Thereafter, a resist layer 20 is formed on the region of the amorphous silicon layer 10 where the gate electrodes 8a and 8b (see FIG. 1) are to be formed using photolithography.

  Next, as shown in FIG. 7, the amorphous silicon layer 10, the metal-containing layer 9, and the gate insulating film 7 are etched using the resist layer 20 as a mask. Etching at this time is performed by RIE (Reactive Ion Etching). In addition, when the thickness of the metal-containing layer 9 is large during the etching process by RIE, it is difficult to etch the metal-containing layer 9. In particular, vertical processing by etching the metal-containing layer 9 becomes difficult. However, in this embodiment, since the metal-containing layer 9 is formed to have a small average film thickness of less than about 3 nm (during film formation), the metal-containing layer 9 can be easily etched by RIE. Is possible. Then, by this etching, portions corresponding to the gate electrodes 8a and 8b (see FIG. 1) of the amorphous silicon layer 10 are formed. At the same time, metal-containing layers 9a and 9b constituting gate electrodes 8a and 8b (see FIG. 1) are formed, respectively, and gate insulating films 7a and 7b corresponding to gate electrodes 8a and 8b (see FIG. 1) are formed. Each is formed. Thereafter, the resist layer 20 is removed.

Next, as shown in FIG. 8, in order to suppress damage in the vicinity of the edge portions of the gate insulating films 7a and 7b due to ion implantation, a protective film 21 made of a SiO ₂ film is formed so as to cover the entire surface. Then, using a photolithography technique, a resist layer 22 is formed so as to cover the region corresponding to the formation region of the p-channel MOS transistor 50b (see FIG. 1) of the protective film 21. Thereafter, phosphorus (P), which is an n-type impurity, is ion-implanted under the conditions of implantation energy: about 30 kev and implantation amount: about 3 × 10 ¹⁵ cm ⁻² . As a result, phosphorus (which is an n-type impurity) is added to the amorphous silicon layer 10 in the formation region of the n-channel MOS transistor 50a (see FIG. 1) and the source / drain region 6a of the single crystal silicon layer 3 through the protective film 21. P) is introduced. Thereafter, the resist layer 22 is removed.

Next, as shown in FIG. 9, a resist layer 23 is formed using a photolithography technique so as to cover the region corresponding to the formation region of the n-channel MOS transistor 50 a (see FIG. 1) of the protective film 21. Thereafter, BF ₂ which is a p-type impurity is ion-implanted under the conditions of implantation energy: about 35 kev and implantation amount: about 3 × 10 ¹⁵ cm ⁻² . Thus, BF ₂ that is a p-type impurity is formed in the amorphous silicon layer 10 in the formation region of the p-channel MOS transistor 50b (see FIG. 1) and the source / drain region 6b in the single crystal silicon layer 3 through the protective film 21. Is introduced. Thereafter, the resist layer 23 is removed.

Next, as shown in FIG. 10, by CVD, on the protective film 21 made of SiO ₂ film, by depositing a SiO ₂ film, an interlayer insulating film 11 having a thickness of about 200 nm. Thereafter, a heat treatment (about 950 ° C., about 20 seconds) by an RTA (Rapid Thermal Annealing) method is performed to electrically activate the impurities implanted into the source / drain regions 6 a and 6 b and the amorphous silicon layer 10. The amorphous silicon layer 10 is polycrystallized by this heat treatment. Thereby, an n ⁺ type polysilicon layer 10a is formed in the formation region of n channel MOS transistor 50a, and a p ⁺ type polysilicon layer 10b is formed in the formation region of p channel MOS transistor 50b. In the formation region of the n-channel MOS transistor 50a, the gate electrode 8a is formed by the metal-containing layer 9a and the n ⁺ -type polysilicon layer 10a formed on the metal-containing layer 9a. In the formation region of the p-channel MOS transistor 50b, the gate electrode 8b is formed by the metal-containing layer 9b and the p ⁺ -type polysilicon layer 10b formed on the metal-containing layer 9b.

In the present embodiment, during the heat treatment, in the vicinity of the interface between the gate electrode 8a (8b) and the gate insulating film 7a (7b), Pt of the metal-containing layer 9a (9b) and the polysilicon layer 10a (10b) By reacting with silicon (Si), a Pt—Si bond is formed. Due to this Pt—Si bond, a level is formed in the vicinity of the valence band of silicon. Further, when the gate insulating film 7a of (7b) is formed by HfO ₂ film, HfSi the silicon in the HfO ₂ film Hf and the polysilicon layer 10a (10b) and (Si) is formed by the reaction of metal It is contained in the containing layer 9a (9b). Moreover, a level is formed in the vicinity of the conduction band of silicon by this HfSi.

  Next, as shown in FIG. 1, contact holes 11a are formed in regions corresponding to the source / drain regions 6a and 6b of the interlayer insulating film 11 and the polysilicon layers 10a and 10b by using a photolithography technique and an etching technique. , 11b, 11c, 11d, 11e and 11f. Thereafter, a CVD method is used to form a tungsten layer embedded in the contact holes 11a, 11b, 11c, 11d, 11e, and 11f, and then an extra deposited portion of the tungsten layer is removed using a CMP method. Thus, plugs 12a, 12b, 12c, 12d, 13a and 13b are formed. Finally, wirings 14, 15, 16, 17a and 17b are formed in predetermined regions on the upper surface of the interlayer insulating film 11. As described above, the CMOS according to the present embodiment shown in FIG. 1 is formed.

  In the present embodiment, as described above, the gate electrode 8a (8b) is formed of the polysilicon layer 10a (10b) and the metal formed in the vicinity of the interface between the polysilicon layer 10a (10b) and the gate insulating film 7a (7b). Unlike the case where the gate electrode 8a (8b) is constituted only by the polysilicon layer formed on the gate insulating film 7a (7b), the gate electrode 8a (8b) is constituted by the inclusion layer 9a (9b). Depletion can be suppressed.

  In the present embodiment, the gate electrode 8a (8b) is made of the polysilicon layer 10a (10b), and the metal-containing layer 9a formed in the vicinity of the interface between the polysilicon layer 10a (10b) and the gate insulating film 7a (7b). (9b), the metal-containing layer 9a (9b) and the gate insulating film 7a (7b) are compared with the case where the gate electrode having the same thickness as the gate electrode 8a (8b) is formed only by the metal-containing layer. ) And the stress caused by the difference in thermal expansion coefficient from the single crystal silicon layer 3 can be reduced. Thereby, it is possible to reduce deterioration of electron mobility caused by stress acting between the metal-containing layer 9a (9b), the gate insulating film 7a (7b) and the single crystal silicon layer 3.

  In this embodiment, the metal-containing layer 9a (9b) and the gate insulating film 7a are formed by forming the metal-containing layer 9a (9b) in a dot shape so as to partially cover the gate insulating film 7a (7b). (7b) and the stress caused by the difference in thermal expansion coefficient from the single crystal silicon layer 3 can be further reduced. Thereby, it is possible to further reduce the deterioration of the electron mobility caused by the stress acting between the metal-containing layer 9a (9b), the gate insulating film 7a (7b) and the single crystal silicon layer 3.

In the present embodiment, the metal-containing layer 9b is configured to contain Pt and TaN, so that Pt contained in the metal-containing layer 9b reacts with silicon in the polysilicon layer 10b to form a Pt—Si bond. Thus, the Fermi level of the gate electrode 8b of the p-channel MOS transistor 50b can be easily fixed to the level on the valence band side of silicon. As a result, the work function of the gate electrode 8b of the p-channel MOS transistor 50b can be adjusted to be increased, so that the threshold voltage of the p-channel MOS transistor 50b can be adjusted to be decreased. Further, by configuring the gate insulating film 7a by the HfO ₂ film, by forming the Hf-Si bond Hf contained in HfO ₂ film of the gate insulating film 7a reacts with silicon of the polysilicon layer 10a, n The Fermi level of the gate electrode 8a of the channel MOS transistor 50a can be easily fixed to the level on the silicon conduction band side. As a result, the work function of the gate electrode 8a of the n-channel MOS transistor 50a can be adjusted to be reduced, so that the threshold voltage of the n-channel MOS transistor 50a can be adjusted to be lowered. As described above, in the CMOS constituted by n-channel MOS transistor 50a and p-channel MOS transistor 50b, the threshold voltages of both n-channel MOS transistor 50a and p-channel MOS transistor 50b are adjusted to decrease. Can do.

  In the present embodiment, the metal-containing layer 9a (9b) is formed in a dot shape so as to partially cover the gate insulating film 7a (7b), and the polysilicon layer 10a (10b) is formed in the gate insulating film 7a ( The contact area between the polysilicon layer 10a (10b) and the gate insulating film 7a (7b) can be reduced by forming it so as to be in contact with the portion not covered with the metal-containing layer 9a (9b) of 7b). Therefore, the Fermi level pinning of the polysilicon layer 10a (10b) due to the interface reaction between the polysilicon layer 10a (10b) and the gate insulating film 7a (7b) is less likely to occur. As a result, it can be suppressed that it is difficult to adjust the work functions of gate electrodes 8a and 8b to values suitable for n channel MOS transistor 50a and p channel MOS transistor 50b due to pinning.

  In the present embodiment, the metal-containing layer 9a of the gate electrode 8a of the n-channel MOS transistor 50a and the metal-containing layer 9b of the gate electrode 8b of the p-channel MOS transistor 50b contain the same metal (Pt and TaN). By configuring, the metal-containing layers 9a and 9b can be simultaneously formed by patterning the same layer containing Pt and TaN, so that the manufacturing process when forming the metal-containing layers 9a and 9b is simplified. be able to.

(Example)
Next, the presence / absence of the metal-containing layer (Pt) of the gate electrode (Example 1), the presence / absence of the SiN film between the SiO ₂ film of the gate insulating film and the metal-containing layer of the gate electrode (Example 2), A comparative experiment conducted to examine how the threshold voltage of the MOS transistor changes depending on the type and concentration (Example 3) of the impurity introduced into the polysilicon layer of the gate electrode will be described. In this comparative experiment, an n-channel MOS transistor and a p-channel MOS transistor were fabricated, and gate capacitance-gate voltage (CV) characteristics were examined using the fabricated n-channel MOS transistor and p-channel MOS transistor. Details will be described below.

Example 1
In the first embodiment, an experiment conducted to investigate how the threshold voltages of the n-channel MOS transistor and the p-channel MOS transistor change depending on the presence / absence of the metal-containing layer (Pt) of the gate electrode will be described. . First, MOS transistors according to the following Example 1-1, Example 1-2, Comparative Example 1-1, and Comparative Example 1-2 were fabricated.

(Example 1-1)
In Example 1-1, an n-channel MOS transistor having a size of 100 μm × 100 μm was fabricated. In Example 1-1, a dot-like metal-containing layer containing only Pt having a thickness of 0.9 nm was formed on the gate insulating film made of the SiO ₂ film by sputtering. Then, an n ⁺ type polysilicon layer having a thickness of 150 nm was formed on the metal-containing layer. The gate electrode of the n-channel MOS transistor according to Example 1-1 was formed by the metal-containing layer and the polysilicon layer thus formed. Except for this, an n-channel MOS transistor according to Example 1-1 was fabricated in the same manner as the n-channel MOS transistor according to the above embodiment.

(Example 1-2)
In Example 1-2, a p-channel MOS transistor having a size of 100 μm × 100 μm was fabricated. In Example 1-2, as in Example 1-1 above, a dot-like metal-containing layer containing only Pt having a thickness of 0.9 nm and a p ⁺ type poly having a thickness of 150 nm are used. A silicon layer was formed. The gate electrode of the p-channel MOS transistor according to Example 1-2 was formed by the metal-containing layer and the polysilicon layer thus formed. Except for this, a p-channel MOS transistor according to Example 1-2 was fabricated in the same manner as the p-channel MOS transistor according to the above embodiment.

(Comparative Example 1-1)
In Comparative Example 1-1, an n-channel MOS transistor was fabricated in the same manner as in Example 1-1 except that the gate electrode was formed only by an n ⁺ type polysilicon layer having a thickness of 150 nm. That is, in the n-channel MOS transistor according to Comparative Example 1-1, the metal-containing layer of the gate electrode was not formed.

(Comparative Example 1-2)
In Comparative Example 1-2, a p-channel MOS transistor was fabricated in the same manner as in Example 1-2, except that the gate electrode was formed only by a p ⁺ type polysilicon layer having a thickness of 150 nm. That is, in the p-channel MOS transistor according to Comparative Example 1-2, the metal-containing layer of the gate electrode was not formed.

  Then, by performing high-frequency CV measurement using the MOS transistors according to Example 1-1, Example 1-2, Comparative Example 1-1, and Comparative Example 1-2 produced as described above, The gate capacitance-gate voltage (CV) characteristics of the MOS transistor were examined. The result is shown in FIG. As can be seen from FIG. 11, in the n-channel MOS transistor according to Example 1-1, the position of the falling portion of the CV curve is positive (+ ) To increase. This indicates that the flat band voltage of the n-channel MOS transistor according to Example 1-1 changed in the positive (+) direction with respect to the flat band voltage of the n-channel MOS transistor according to Comparative Example 1-1. . The flat band voltage is a gate voltage necessary for flattening the energy band structure at the interface between the gate insulating film and the silicon layer constituting the channel region. When the flat band voltage changes The threshold voltage of the MOS transistor also changes in the same direction (positive or negative). Therefore, from FIG. 11, in the n-channel MOS transistor according to Example 1-1, Comparative Example 1 in which the metal-containing layer (Pt) of the gate electrode is formed by forming the metal-containing layer (Pt) of the gate electrode. It can be seen that the threshold voltage can be changed (increased) in the positive (+) direction as compared with the n-channel MOS transistor of -1.

This is considered to be due to the following reason. That is, the n ⁺ -type polysilicon layer of the gate electrode of the n-channel MOS transistor has a Fermi level near the conduction band of silicon. In addition, Pt contained in the metal-containing layer at the interface between the gate electrode and the gate insulating film reacts with silicon (Si) in the polysilicon layer of the gate electrode to form a Pt—Si bond, thereby forming silicon (Si). A level is formed in the vicinity of the valence band. Therefore, when the gate electrode is formed by the n ⁺ type polysilicon layer and the metal-containing layer containing Pt, the gate electrode and the gate insulating film are affected by Fermi level pinning due to the Pt—Si bond. The effective Fermi level at the interface is shifted from the position near the conduction band of silicon by the n ⁺ -type polysilicon layer to the valence band side of silicon by the Pt—Si bond. This increases the effective work function of the gate electrode. Therefore, in the n-channel MOS transistor according to Example 1-1, the flat band voltage changes in the positive (+) direction and the threshold voltage is positive (positive) as compared with the n-channel MOS transistor according to Comparative Example 1-1. It is thought that it has changed in the + direction.

In addition, it can be seen from FIG. 11 that the p-channel MOS transistor according to Example 1-2 and the p-channel MOS transistor according to comparative example 1-1 show substantially similar CV curves. This is considered to be due to the following reason. That is, the Fermi level of the p ⁺ type polysilicon layer of the gate electrode of the p-channel MOS transistor is located near the valence band of silicon (Si). Thereby, a level is formed in the vicinity of the valence band of silicon by a Pt-Si bond formed by a reaction between Pt contained in the metal-containing layer of the gate electrode and silicon (Si) of the polysilicon layer, Even if the gate electrode is affected by Fermi level pinning due to Pt-Si bonding, the position of the effective Fermi level at the interface between the gate electrode and the gate insulating film hardly changes from the vicinity of the valence band of silicon. For this reason, even if the gate electrode includes a metal-containing layer containing Pt, the effective work function of the gate electrode of the p-channel MOS transistor hardly changes. Thus, the p-channel MOS transistor according to Example 1-2 in which the gate electrode includes the metal-containing layer (Pt) and the p-channel MOS transistor according to comparative example 1-2 in which the gate electrode does not include the metal-containing layer (Pt). It is thought that almost the same CV curve was shown.

(Example 2)
In the second embodiment, how the threshold voltages of the n-channel MOS transistor and the p-channel MOS transistor change depending on the presence or absence of the SiN film between the SiO ₂ film of the gate insulating film and the metal-containing layer of the gate electrode. An experiment conducted to investigate whether this will be described. In Example 2, MOS transistors according to Example 2-1, Example 2-2, Comparative Example 2-1, and Comparative Example 2-2 were fabricated.

(Example 2-1)
In Example 2-1, an n-channel MOS transistor having a size of 100 μm × 100 μm was fabricated. Further, in Example 2-1, after forming a gate insulating film made of a SiO ₂ film having a thickness of 10 nm, a SiN film having a thickness of 2 nm was formed on the gate insulating film. Then, using a sputtering method, a dot-shaped metal-containing layer containing only Pt having a thickness of 0.9 nm was formed on the SiN film. Further, an n ⁺ type polysilicon layer having a thickness of 150 nm was formed on the metal-containing layer. Except for this, an n-channel MOS transistor according to Example 2-1 was fabricated in the same manner as in Example 1-1.

(Example 2-2)
In Example 2-2, a p-channel MOS transistor having a size of 100 μm × 100 μm was fabricated. Further, in this Example 2-2, similarly to the above Example 2-1, a gate insulating film made of a SiO ₂ film having a thickness of 10 nm, a SiN film having a thickness of 2 nm on the gate insulating film, A dot-like metal-containing layer containing only Pt having a thickness of 0.9 nm was formed. In addition, a p ⁺ type polysilicon layer having a thickness of 150 nm was formed on the metal-containing layer. A p-channel MOS transistor according to Example 2-2 was fabricated in the same manner as in Example 1-2, except for the above.

(Comparative Example 2-1)
In this comparative example 2-1, except that the SiN film was not formed between the gate insulating film made of the SiO ₂ film and the metal-containing layer of the gate electrode, An n-channel MOS transistor was produced.

(Comparative Example 2-2)
In this Comparative Example 2-2, except that the SiN film was not formed between the gate insulating film made of the SiO ₂ film and the metal-containing layer of the gate electrode, the same as in Example 2-2, A p-channel MOS transistor was produced.

  Then, by performing high-frequency CV measurement using the MOS transistors according to Example 2-1, Example 2-2, Comparative Example 2-1, and Comparative Example 2-2 manufactured as described above, The gate capacitance-gate voltage (CV) characteristics of the MOS transistor were examined. The result is shown in FIG. As can be seen from FIG. 12, in the n-channel MOS transistor according to Example 2-1 including the SiN film, the falling portion of the CV curve is smaller than that of the n-channel MOS transistor according to Comparative Example 2-1 including no SiN film. Is shifted in the direction in which the gate voltage increases positively (+). That is, in the n-channel MOS transistor according to Example 2-1, the flat band voltage changes in the positive (+) direction and the threshold voltage is positive (+) compared to the n-channel MOS transistor according to Comparative Example 2-1. ) You can see that the direction has changed. This means that the effective work function of the gate electrode of the shifted n-channel MOS transistor (Example 1-1) in Example 1 is further shifted in the midgap (+) direction.

  From FIG. 12, in the p-channel MOS transistor according to Example 2-2, the gate voltage is negative (−) at the position of the falling portion of the CV curve as compared with the p-channel MOS transistor according to comparative example 2-2. It can be seen that there is a shift in a decreasing direction. Thereby, in the p-channel MOS transistor according to Example 2-2, the flat band voltage changes in the negative (−) direction and the threshold voltage is negative (−) as compared with the p-channel MOS transistor according to Comparative Example 2-2. -) It can be seen that the direction has changed. This means that the effective work function of the gate electrode of the p-channel MOS transistor (Embodiment 1-2) that has hardly changed in Embodiment 1 is shifted in the midgap (−) direction. From these results, when the SiN film is used as the cap layer when the metal-containing layer made of Pt is formed on the gate insulating film by the sputtering method, the flat band voltage and threshold voltage of the p-channel MOS transistor are reduced. It was found that adjustment in the negative (-) direction was possible. These results show that the Pt of the metal-containing layer is affected by nitrogen (N) in the SiN film, and the charge neutral point at the interface between the gate electrode and the gate insulating film as a whole shifts to the silicon midgap. This is thought to be due to the generation of such a level.

(Example 3)
In the third embodiment, an experiment conducted for examining how the threshold voltage of an n-channel MOS transistor changes depending on the type and concentration of impurities introduced into the polysilicon layer of the gate electrode will be described. In this Example 3, n-channel MOS transistors according to the following Example 3-1, Example 3-2, Example 3-3 and Example 3-4 were produced.

(Example 3-1)
In Example 3-1, an n-channel MOS transistor having a size of 100 μm × 100 μm was fabricated. In Example 3-1, a dot-like metal-containing layer containing only TaN having a thickness of 0.5 nm (during film formation) is formed on the gate insulating film made of the SiO ₂ film by using the CVD method. did. Then, a p ⁺ type polysilicon layer having a thickness of 150 nm was formed on the metal-containing layer. At this time, in Example 3-1, BF ₂ was ion-implanted into the polysilicon layer under the condition of an implantation amount of 1 × 10 ¹⁵ cm ⁻² . Thereby, the impurity concentration of the p ⁺ type polysilicon layer was set to 6.7 × 10 ¹⁹ cm ⁻³ . Except for this, an n-channel MOS transistor according to Example 3-1 was fabricated in the same manner as in Example 1-1.

(Example 3-2)
In Example 3-2, BF ₂ is ion-implanted into the polysilicon layer under the condition of an implantation amount: 2 × 10 ¹⁵ cm ⁻² to have an impurity concentration of 1.3 × 10 ²⁰ cm ^−3. A p ⁺ type polysilicon layer of the gate electrode was formed. Except for this, an n-channel MOS transistor according to Example 3-2 was fabricated in the same manner as in Example 3-1.

(Example 3-3)
In Example 3-3, the gate electrode having an impurity concentration of 2 × 10 ²⁰ cm ⁻³ is obtained by ion-implanting BF ₂ into the polysilicon layer under the condition of the implantation amount: 3 × 10 ¹⁵ cm ^−2. A p ⁺ -type polysilicon layer was formed. Except for this, an n-channel MOS transistor according to Example 3-3 was fabricated in the same manner as in Example 3-1.

(Example 3-4)
In this Example 3-4, phosphorus (P ⁺ ) is ion-implanted into the polysilicon layer under the condition of the implantation amount: 3 × 10 ¹⁵ cm ⁻² to obtain an impurity concentration of 2 × 10 ²⁰ cm ^−3. An n ⁺ type polysilicon layer of the gate electrode was formed. Other than this, an n-channel MOS transistor according to Example 3-4 was fabricated in the same manner as in Example 3-1.

Then, by performing high-frequency CV measurement using the n-channel MOS transistors according to Example 3-1 to Example 3-4 manufactured as described above, the gate capacitance-gate voltage of these n-channel MOS transistors. (CV) characteristics were examined. The result is shown in FIG. From FIG. 13, the impurity concentration of the p ⁺ type polysilicon layer of the gate electrode is changed from 6.7 × 10 ¹⁹ cm ⁻³ (Example 3-1) to 1.3 × 10 ²⁰ cm ⁻³ (Example 3- 2) and 2 × 10 ²⁰ cm ⁻³ (Example 3-3), the position of the falling part of the CV curve gradually shifts in the direction in which the gate voltage increases positively (+) as it increases. I understand. Accordingly, it has been found that the flat band voltage and the threshold voltage in the MOS transistor can be adjusted by adjusting the impurity concentration of the polysilicon layer of the gate electrode.

Further, from FIG. 13, in the n-channel MOS transistor of Example 3-3 using the p ⁺ type polysilicon layer having an impurity concentration of 2 × 10 ²⁰ cm ⁻³ , the same impurity concentration (2 × 10 ²⁰ cm ^{− 3} ) In comparison with the n-channel MOS transistor of Example 3-4 using the n ⁺ -type polysilicon layer having ³ ), the falling position of the CV curve is in the direction in which the gate voltage increases positively (+). It turns out that it grows. From this result, it is possible to adjust the flat band voltage and the threshold voltage in the n-channel MOS transistor by making the polysilicon layer p-type or n-type depending on the type of impurities introduced into the polysilicon layer of the gate electrode. It turns out that it is possible. From the above results, in the MOS device in which a dot-like metal made of TaN is introduced at the interface between the gate insulating film and the polysilicon layer constituting the gate electrode, the type and concentration of impurities introduced into the polysilicon layer can be changed. Thus, the effective work function of the gate electrode can be continuously adjusted.

  The embodiments and examples disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments and examples but by the scope of claims for patent, and includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

For example, in the above embodiment, both of the metal-containing layer 9a constituting the gate electrode 8a of the n-channel MOS transistor 50a and the metal-containing layer 9b constituting the gate electrode 8b of the p-channel MOS transistor 50b contain Pt and TaN. However, the present invention is not limited to this, and only one of the metal-containing layer constituting the gate electrode of the n-channel MOS transistor and the metal-containing layer constituting the gate electrode of the p-channel MOS transistor is plural. You may comprise so that other metals may be included. For example, as shown in FIG. 14, the metal-containing layer 9b constituting the gate electrode 8b of the p-channel MOS transistor 50b is constituted to contain Pt and TaN, and the metal constituting the gate electrode 8a of the n-channel MOS transistor 50a. The inclusion layer 19a may be configured to include only TaN. In this case, at least the gate insulating film 7a of the n-channel MOS transistor 50a is preferably composed of an HfO ₂ film.

In the above embodiment, both the metal-containing layer 9a constituting the gate electrode 8a of the n-channel MOS transistor 50a and the metal-containing layer 9b constituting the gate electrode 8b of the p-channel MOS transistor 50b are made of the same metal (Pt and However, the present invention is not limited to this, and the metal-containing layer constituting the gate electrode of the n-channel MOS transistor and the metal-containing layer constituting the gate electrode of the p-channel MOS transistor are different from each other. You may comprise so that a some metal may be included. For example, as shown in FIG. 15, the metal-containing layer 29a constituting the gate electrode 8a of the n-channel MOS transistor 50a is constituted to contain Hf and TaN, and the metal constituting the gate electrode 8b of the p-channel MOS transistor 50b. The containing layer 9b may be configured to contain Pt and TaN. In this case, the gate insulating film 7a of the n-channel MOS transistor 50a may be formed of either an SiO ₂ film or an HfO ₂ film.

  In the above embodiment, the CMOS as an example of the semiconductor device according to the present invention has been described as an example. However, the present invention is not limited to this, and the present invention can be applied to semiconductor devices other than the CMOS.

  In the above embodiment, an example in which the polysilicon layer of the gate electrode of the n-channel MOS transistor constituting the CMOS is n-type and the polysilicon layer of the gate electrode of the p-channel MOS transistor is p-type has been described. The present invention is not limited to this, and the polysilicon layers of the gate electrodes of the n-channel MOS transistor and the p-channel MOS transistor constituting the CMOS may be of the same conductivity type.

  In the above embodiment, the metal-containing layer of the gate electrode is formed in a dot shape. However, the present invention is not limited to this, and the metal-containing layer of the gate electrode is partially formed on the gate insulating film in a shape other than the dot shape. It may be formed automatically. Further, the metal-containing layer of the gate electrode may be formed of a continuous thin film formed on the entire surface of the gate insulating film.

  In the above embodiment, the metal-containing layer is formed in a dot shape by aggregating the metal-containing layer by heat treatment after forming the metal-containing layer on the gate insulating film, but the present invention is not limited thereto, The metal-containing layer may be formed in a dot shape using various methods other than those described above. For example, the CVD method is used to form a metal-containing layer on the gate insulating film, and heat treatment is performed by controlling the formation conditions by the CVD method so that the metal-containing layer is already formed in a dot shape. The metal-containing layer may be formed in a dot shape without performing the above.

  In the above embodiment, after forming the metal-containing layer of the gate electrode, a step of depositing an amorphous silicon layer by a CVD method, or a heat treatment step for activating impurities introduced into the source / drain regions and the amorphous silicon layer In addition, the metal-containing layer is agglomerated in the form of dots using heat applied in other processes. However, the present invention is not limited to this, and after the metal-containing layer is formed on the gate insulating film, the heat treatment is subsequently performed. By performing the above, the metal-containing layer may be aggregated in a dot shape.

  In the above embodiment, the metal-containing layer of the gate electrode is configured to contain TaN. However, the present invention is not limited to this, and other materials may be used instead of TaN of the metal-containing layer of the gate electrode. . For example, metal silicides such as TiSi and TaSi, metal nitrides, and simple metals may be used instead of TaN.

  In the above embodiment, the metal-containing layer of the gate electrode is configured to contain Pt. However, the present invention is not limited to this, and a level can be formed on the valence band side of the silicon midgap. If the metal is a metal, another metal may be included in the metal-containing layer of the gate electrode instead of Pt. For example, the metal-containing layer of the gate electrode may be configured to include a metal such as Ru or Ir instead of Pt.

Further, in the above embodiment, the HfO ₂ film as the high dielectric constant insulating film to form the gate insulating film, the present invention is not limited to this, the HfO ₂ film as the high dielectric constant insulating film to form the gate insulating film An insulating film made of a material other than the above may be used. For example, a ZrO ₂ film, HfAlO film, SiN film, SiON film, HfSiO film, HfNO film, or the like may be used as the high dielectric constant insulating film for forming the gate insulating film.

In the above embodiment, the gate insulating film is formed using the HfO ₂ film containing Hf that forms a level on the conduction band side of the energy level (mid gap) between the conduction band and the valence band of silicon. However, the present invention is not limited to this, and the gate insulating film may be formed using a material containing a metal that forms a level closer to the valence band than the mid gap of silicon. For example, the gate insulating film may be formed using an Al ₂ O ₃ film or the like.

  Moreover, in the said embodiment, although CMOS was formed using the SOI substrate, this invention is not limited to this, You may form CMOS using semiconductor substrates other than an SOI substrate. For example, a CMOS may be formed using a single crystal silicon substrate or the like.

  In the above embodiment, the gate electrode 8a of the n-channel MOS transistor 50a and the gate electrode 8b of the p-channel MOS transistor 50b are connected via the plugs 13a and 13b and the wirings 17a and 17b. However, the present invention is not limited to this, and the gate electrode 8a of the n-channel MOS transistor 50a and the gate electrode 8b of the p-channel MOS transistor 50b may be connected by various configurations other than those described above. For example, by using salicide technology, a single layer made of Ti, Co, or the like that connects the polysilicon layer 10a of the gate electrode 8a of the n-channel MOS transistor 50a and the polysilicon layer 10b of the gate electrode 8b of the p-channel MOS transistor 50b. A silicide layer is formed on polysilicon layers 10a and 10b by forming a metal-containing layer and heat-treating, and via the silicide layer, gate electrode 8a of n-channel MOS transistor 50a and p-channel MOS transistor 50b The gate electrode 8b may be connected.

1 is a cross-sectional view illustrating a structure of a CMOS according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view showing the structure of an n-channel MOS transistor portion of the CMOS according to the embodiment shown in FIG. 1. FIG. 5 is an energy band diagram for explaining levels formed in the vicinity of the conduction band and the vicinity of the valence band in the n-channel MOS transistor and the p-channel MOS transistor constituting the CMOS according to the embodiment of the present invention. It is the correlation figure which showed the relationship between the work function of the polysilicon layer and the effective work function of a gate electrode in the n channel MOS transistor and p channel MOS transistor which comprise CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing process of CMOS by one Embodiment of this invention. It is the figure which showed the gate capacity-gate voltage characteristic of the MOS transistor by Example 1-1 of this invention, Example 1-2, Comparative example 1-1, and Comparative example 1-2. It is the figure which showed the gate capacity-gate voltage characteristic of the MOS transistor by Example 2-1 of this invention, Example 2-2, Comparative example 2-1, and Comparative example 2-2. It is the figure which showed the gate capacity-gate voltage characteristic of the n channel MOS transistor by Example 3-1 to Example 3-4 of this invention. It is sectional drawing which showed the structure of CMOS by the modification of one Embodiment of this invention. It is sectional drawing which showed the structure of CMOS by the modification of one Embodiment of this invention.

Explanation of symbols

3 Single crystal silicon layer (semiconductor region)
5a channel region (first channel region)
5b channel region (second channel region)
6a Source / drain region (first source / drain region)
6b Source / drain region (second source / drain region)
7a Gate insulating film (first gate insulating film)
7b Gate insulating film (second gate insulating film)
8a Gate electrode (first gate electrode)
8b Gate electrode (second gate electrode)
9a Metal-containing layer (first metal-containing layer)
9b Metal-containing layer (second metal-containing layer)
10a Polysilicon layer (first semiconductor layer)
10b Polysilicon layer (second semiconductor layer)

Claims (6)

A pair of first source / drain regions of the first conductivity type formed at a predetermined interval so as to sandwich the first channel region on the main surface of the semiconductor region;
A first semiconductor layer formed on the first channel region through a first gate insulating film; and a first metal-containing layer formed in the vicinity of an interface between the first semiconductor layer and the first gate insulating film; A first gate electrode comprising:
A pair of second source / drain regions of the second conductivity type formed at a predetermined interval so as to sandwich the second channel region on the main surface of the semiconductor region;
A second semiconductor layer formed on the second channel region via a second gate insulating film; and a second metal-containing layer formed in the vicinity of an interface between the second semiconductor layer and the second gate insulating film. A second gate electrode including
At least one of the first metal-containing layer and the second metal-containing layer is a semiconductor device including a plurality of metals. The first metal-containing layer and the second metal-containing layer are formed so as to partially cover the first gate insulating film and the second gate insulating film, respectively.
The first semiconductor layer and the second semiconductor layer are a portion of the first gate insulating film not covered with the first metal-containing layer, and the second metal-containing layer of the second gate insulating film, respectively. The semiconductor device according to claim 1, wherein the semiconductor device is formed so as to be in contact with a portion that is not covered by the substrate.   The semiconductor device according to claim 2, wherein the first metal-containing layer and the second metal-containing layer are formed in a dot shape.   The semiconductor device according to claim 1, wherein the first metal-containing layer and the second metal-containing layer include the same plurality of metals. The first source / drain region is n-type, and the second source / drain region is p-type,
The first gate insulating film includes a metal that forms a level on the conduction band side with respect to an energy level intermediate between a conduction band and a valence band of the first semiconductor layer,
The said 2nd metal content layer contains the said metal which forms a level in the said valence band side rather than the intermediate energy level of the said conduction band and the said valence band of the said 2nd semiconductor layer. 5. The semiconductor device according to claim 4. The first source / drain region is n-type, and the second source / drain region is p-type,
The first metal-containing layer includes the metal that forms a level on the conduction band side with respect to an energy level intermediate between a conduction band and a valence band of the first semiconductor layer,
The said 2nd metal content layer contains the said metal which forms a level in the said valence band side rather than the intermediate energy level of the said conduction band and the said valence band of the said 2nd semiconductor layer. 5. The semiconductor device according to claim 4.

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