JP2008258318A - Semiconductor chip, its packaging method and semiconductor device - Google Patents

Semiconductor chip, its packaging method and semiconductor device Download PDF

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JP2008258318A
JP2008258318A JP2007097492A JP2007097492A JP2008258318A JP 2008258318 A JP2008258318 A JP 2008258318A JP 2007097492 A JP2007097492 A JP 2007097492A JP 2007097492 A JP2007097492 A JP 2007097492A JP 2008258318 A JP2008258318 A JP 2008258318A
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semiconductor chip
sealing resin
semiconductor
electrode
substrate
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JP5022756B2 (en
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Katsuhiko Kitagawa
勝彦 北川
Hiroyuki Shinoki
裕之 篠木
Koji Yamada
紘士 山田
Takashi Noma
崇 野間
Yuichi Morita
祐一 森田
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Sanyo Electric Co Ltd
System Solutions Co Ltd
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Sanyo Electric Co Ltd
Sanyo Semiconductor Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip and its packaging method which facilitate repair work after packaging and also suppress manufacturing cost, and a semiconductor device packaging the semiconductor chip. <P>SOLUTION: A projection electrode 3 is formed on the back of a semiconductor substrate 1. Next, a sealing resin 5 is selectively formed on the back of the semiconductor substrate 1. At least a part of the projection electrode 3 is not covered with the sealing resin 5 and exposed from the outer peripheral direction of the individual semiconductor chip. Next, the semiconductor substrate 1 is cut along a predetermined dicing line DL to be divided into the semiconductor chips 10. Next, the projection electrode 3 is connected to a pad electrode 11, and when heat treatment is applied in this state, the projection electrode 3 is jointed to the pad electrode 11. In this process, the sealing resin 5 in a semi-hardened state is softened so as to be charged into a part between the semiconductor chip 10 and a packaging substrate 12, and the semiconductor chip 10 is bonded to the packaging substrate 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、複数の突起電極が形成された半導体チップ及びその実装方法、当該半導体チップが実装された半導体装置に関するものである。   The present invention relates to a semiconductor chip on which a plurality of protruding electrodes are formed, a mounting method thereof, and a semiconductor device on which the semiconductor chip is mounted.

近年、新たなパッケージ技術としてCSP(Chip Size Package)が注目されている。CSPとは、半導体チップの外形寸法と略同サイズの外形寸法を有する小型パッケージをいう。そして、CSPの一種としてBGA(Ball Grid Array)型の半導体装置が知られている。BGA型の半導体装置は、ハンダ等の金属材料から成るボール状の端子がパッケージの一方の面上に複数配列されたものである。   In recent years, CSP (Chip Size Package) has attracted attention as a new packaging technology. The CSP refers to a small package having an outer dimension substantially the same as the outer dimension of a semiconductor chip. A BGA (Ball Grid Array) type semiconductor device is known as a kind of CSP. A BGA type semiconductor device has a plurality of ball-shaped terminals made of a metal material such as solder arranged on one surface of a package.

BGA型の半導体チップの従来の実装方法について図5を参照しながら説明する。半導体基板100と、その一方の面(裏面)上に一定の間隔で形成された複数の突起電極101と、半導体基板100の他方の面(表面)上に貼り合わされた支持体102(例えばガラス基板)とを備える半導体チップ103を準備する。なお、突起電極101が形成された部分以外の半導体基板100の裏面はソルダーレジスト等から成る絶縁性の保護膜104で被覆されている。   A conventional method for mounting a BGA type semiconductor chip will be described with reference to FIG. Semiconductor substrate 100, a plurality of protruding electrodes 101 formed on one surface (back surface) thereof at regular intervals, and a support 102 (for example, a glass substrate) bonded on the other surface (front surface) of semiconductor substrate 100 ) Is prepared. The back surface of the semiconductor substrate 100 other than the portion where the protruding electrode 101 is formed is covered with an insulating protective film 104 made of a solder resist or the like.

続いて、表面上にアルミニウム等から成る複数のパッド電極105が形成された実装基板106を準備する。次に、実装基板106上に半導体チップ100を重ねて突起電極101とパッド電極105とを接続し、実装基板106上に半導体チップ103を固定する。この工程の際、突起電極101は過熱融解されることでパッド電極105と接合される。このような実装方式は、一般にフリップチップ(Flip Chip)接続と呼ばれている。   Subsequently, a mounting substrate 106 having a plurality of pad electrodes 105 made of aluminum or the like formed on the surface is prepared. Next, the semiconductor chip 100 is overlaid on the mounting substrate 106 to connect the protruding electrode 101 and the pad electrode 105, and the semiconductor chip 103 is fixed on the mounting substrate 106. In this step, the protruding electrode 101 is bonded to the pad electrode 105 by being heated and melted. Such a mounting method is generally called a flip chip connection.

ただし、近年における半導体チップの微細化に伴って、突起電極のサイズを小さくすることや突起電極のピッチを出来る限り短くする等の要求がある。そのため、突起電極とパッド電極との接合のみでは実装強度の確保が困難な場合がある。実装強度が十分でない場合に熱的応力や物理的応力が突起電極の接合部に集中すると、クラックの発生等が起きてしまい、信頼性を確保できない。   However, with recent miniaturization of semiconductor chips, there are demands such as reducing the size of the protruding electrodes and shortening the pitch of the protruding electrodes as much as possible. For this reason, it may be difficult to ensure mounting strength only by bonding the protruding electrode and the pad electrode. When the mounting strength is not sufficient, if thermal stress or physical stress is concentrated on the joint portion of the bump electrode, cracks occur and reliability cannot be ensured.

そこで、微細な半導体チップを実装する際には、半導体チップと実装基板との接続を補強する材料として図5に示すようなアンダーフィルと呼ばれる封止樹脂107を半導体チップ103と実装基板106との間に充填させ、これによって高い実装強度を確保していた。   Therefore, when a fine semiconductor chip is mounted, a sealing resin 107 called an underfill as shown in FIG. 5 is used as a material for reinforcing the connection between the semiconductor chip and the mounting substrate. By filling in between, high mounting strength was secured.

封止樹脂107は、実装基板106に半導体チップ103を実装した後、ディスペンサーノズル等を用いて半導体チップ103の周囲にペースト状の封止樹脂材を供給し、毛細管現象により半導体チップ103と実装基板106との隙間に封止樹脂材を充填させ、当該封止樹脂材を加熱硬化させることによって形成される。なお、封止樹脂107としては、エポキシ樹脂、シリコーン樹脂、フェノール樹脂、ポリイミド樹脂、アクリル樹脂等があるが、特性やコストの面からエポキシ樹脂を含む熱硬化性樹脂が一般的である。   After the semiconductor chip 103 is mounted on the mounting substrate 106, the sealing resin 107 supplies a paste-like sealing resin material around the semiconductor chip 103 using a dispenser nozzle or the like, and the semiconductor chip 103 and the mounting substrate are caused by a capillary phenomenon. The gap is formed by filling a gap between the sealing resin material 106 and the sealing resin material by heat curing. The sealing resin 107 includes an epoxy resin, a silicone resin, a phenol resin, a polyimide resin, an acrylic resin, and the like, but a thermosetting resin including an epoxy resin is generally used from the viewpoint of characteristics and cost.

本発明に関連した技術は、例えば以下の特許文献に記載されている。
特開2001−284380号公報
Techniques related to the present invention are described in, for example, the following patent documents.
JP 2001-284380 A

しかしながら、上述したように封止樹脂107を形成すると、以下に説明するような問題があった。それは、実装後の信頼性検査によって半導体チップ103と実装基板106との接合部で不良(実装ズレ等)が発見された場合に、当該接合部のリペア作業が困難であるという問題である。なぜなら、エポキシ樹脂等の多くの封止樹脂107は、一度熱処理を施して硬化させると接続強度が強く、実装後に実装基板106から半導体チップ103を取り外すことは極めて困難だからである。従ってこのような場合には、それら全体を廃棄することになってしまうことが多い。   However, when the sealing resin 107 is formed as described above, there is a problem as described below. The problem is that when a defect (such as mounting displacement) is found at the joint between the semiconductor chip 103 and the mounting substrate 106 by a reliability inspection after mounting, the repair of the joint is difficult. This is because many sealing resins 107 such as epoxy resins have strong connection strength once heat-treated and cured, and it is extremely difficult to remove the semiconductor chip 103 from the mounting substrate 106 after mounting. Therefore, in such a case, they are often discarded.

また、封止樹脂107の材料を選別し、仮に半導体チップ103を実装基板106から取り外すことができるとしても、ヒートガン等の局所ヒータを用いて封止樹脂107を軟化させる作業、実装基板106上の周辺部品に損傷を及ぼさないように半導体チップ103を剥がす作業、実装基板106上に残った封止樹脂107の除去作業等が必要である。このような手間がかかるため、リペア作業が容易とはいえない。   Further, even if the material of the sealing resin 107 is selected and the semiconductor chip 103 can be removed from the mounting substrate 106, an operation of softening the sealing resin 107 using a local heater such as a heat gun is performed on the mounting substrate 106. An operation of peeling the semiconductor chip 103 so as not to damage peripheral components, an operation of removing the sealing resin 107 remaining on the mounting substrate 106, and the like are necessary. Because of this time and effort, repair work is not easy.

また、従来のような実装工程時における封止樹脂107の形成によると製造コストが増大するという問題もあった。   Further, the formation of the sealing resin 107 in the conventional mounting process has a problem that the manufacturing cost increases.

そこで本発明は、実装後のリペア作業が容易に行えるとともに、製造コストを抑えることができる半導体チップとその実装方法、及び当該半導体チップが実装された半導体装置を提供することを主たる目的とする。   SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a semiconductor chip, a mounting method thereof, and a semiconductor device on which the semiconductor chip is mounted, in which repair work after mounting can be easily performed and manufacturing cost can be reduced.

本発明は上記課題に鑑みてなされたものであり、その主な特徴は以下のとおりである。すなわち、本発明の半導体チップの実装方法は、半導体基板と、前記半導体基板の一方の面上に形成された複数の突起電極と、前記半導体基板の一方の面上に部分的に形成された封止樹脂とを備えた半導体チップを形成する工程と、一方の面上に電極が形成された実装基板を準備し、前記突起電極と前記電極とを電気的に接触させ、かつ前記封止樹脂を軟化させて前記半導体チップと前記実装基板とを前記封止樹脂を介して接着させる工程と、その後前記封止樹脂を硬化させる工程とを有し、前記半導体チップを形成する工程は、前記突起電極の外側が露出するように行うことを特徴とする。   The present invention has been made in view of the above problems, and its main features are as follows. That is, the semiconductor chip mounting method of the present invention includes a semiconductor substrate, a plurality of projecting electrodes formed on one surface of the semiconductor substrate, and a seal partially formed on the one surface of the semiconductor substrate. A step of forming a semiconductor chip provided with a stop resin, and a mounting substrate having an electrode formed on one surface thereof, and electrically contacting the protruding electrode and the electrode; and The step of softening and bonding the semiconductor chip and the mounting substrate via the sealing resin, and the step of curing the sealing resin thereafter, the step of forming the semiconductor chip includes the protruding electrode It is characterized in that it is performed so that the outside of the surface is exposed.

また、本発明の半導体チップは、半導体基板と、前記半導体基板の一方の面上に形成された複数の突起電極と、前記半導体基板の一方の面上に部分的に形成された封止樹脂とを備え、前記複数の突起電極の外側が露出しており、前記封止樹脂は、第1の熱処理によって流動性が低下し、前記第1の熱処理よりも高温の第2の熱処理によって流動性が増加する特性を有することを特徴とする。   The semiconductor chip of the present invention includes a semiconductor substrate, a plurality of protruding electrodes formed on one surface of the semiconductor substrate, and a sealing resin partially formed on one surface of the semiconductor substrate. And the outside of the plurality of protruding electrodes is exposed, and the fluidity of the sealing resin is lowered by the first heat treatment, and the fluidity is lowered by the second heat treatment higher than the first heat treatment. It has the characteristic of increasing.

また、本発明の半導体装置は、一方の面上に複数の突起電極を備えた半導体チップと、一方の面上に電極を備え、前記電極が前記突起電極と電気的に接続された実装基板と、前記半導体チップの一方の面と前記実装基板の一方の面との間の空間の一部に充填された封止樹脂とを備え、前記突起電極または前記電極の少なくとも一部が、前記封止樹脂で被覆されずに外側から露出していることを特徴とする。   The semiconductor device of the present invention includes a semiconductor chip having a plurality of protruding electrodes on one surface, a mounting substrate having electrodes on one surface, and the electrodes are electrically connected to the protruding electrodes; A sealing resin filled in a part of a space between one surface of the semiconductor chip and one surface of the mounting substrate, and at least a part of the protruding electrode or the electrode is the sealing It is exposed from the outside without being covered with resin.

本発明では、半導体チップの実装面側に封止樹脂が選択的に形成され、突起電極の側面が外側から露出している。そのため、実装基板に半導体体チップを実装した後であっても、突起電極の接合部が半導体チップの外側から露出するようになり、当該露出部から導電材料等を補充することでリペア作業を容易に行うことが出来る。   In the present invention, the sealing resin is selectively formed on the mounting surface side of the semiconductor chip, and the side surface of the protruding electrode is exposed from the outside. Therefore, even after the semiconductor chip is mounted on the mounting substrate, the joint portion of the protruding electrode is exposed from the outside of the semiconductor chip, and repair work can be facilitated by replenishing the exposed material from the exposed portion. Can be done.

また、個片化した半導体チップを得る前の工程で一括して封止樹脂を形成している。そのため、半導体チップの実装工程の際に個別に封止樹脂を形成していた従来方法に比べて生産性を向上させるとともに、製造コストを抑えることが出来る。また、本発明の封止樹脂は半導体チップの一方の面上に部分的に形成されており、封止樹脂の材料を効率的に使用できるため、製造コストを抑えることができる。   Further, the sealing resin is formed in a lump in the process before obtaining the separated semiconductor chips. Therefore, productivity can be improved and manufacturing cost can be reduced as compared with the conventional method in which the sealing resin is individually formed in the mounting process of the semiconductor chip. Moreover, since the sealing resin of the present invention is partially formed on one surface of the semiconductor chip and the material of the sealing resin can be used efficiently, the manufacturing cost can be suppressed.

本発明の実施形態について図面を参照しながら説明する。図1乃至図3は半導体チップの製造工程から、製造された半導体チップの実装工程までを順番に示す断面図あるいは平面図である。なお、図1及び図2を用いて説明する半導体チップの製造工程では、ダイシングラインDLを境界として多数の半導体チップがマトリクス状に形成されることになるが、便宜上その一部のみを図示して説明する。   Embodiments of the present invention will be described with reference to the drawings. 1 to 3 are cross-sectional views or plan views sequentially showing a manufacturing process from a manufacturing process of a semiconductor chip to a mounting process of the manufactured semiconductor chip. In the semiconductor chip manufacturing process described with reference to FIGS. 1 and 2, a large number of semiconductor chips are formed in a matrix with dicing lines DL as boundaries, but only a part of them is shown for convenience. explain.

まず図1に示すように、多数の半導体素子(例えばMOSトランジスタやバイポーラトランジスタやキャパシタ等から成る集積回路)がチップ領域ごとに形成されたウェハ状の半導体基板1を準備する。半導体基板1の表面上には接着層(不図示)を介して支持体2が貼り合わされている。支持体2はガラス等から成り、半導体基板1を支持するとともに、半導体基板1の表面上に形成された半導体素子(例えばMOSトランジスタやキャパシタ等から構成される半導体集積回路)を保護するためのものである。   First, as shown in FIG. 1, a wafer-like semiconductor substrate 1 on which a large number of semiconductor elements (for example, integrated circuits composed of MOS transistors, bipolar transistors, capacitors, etc.) are formed for each chip region is prepared. A support 2 is bonded on the surface of the semiconductor substrate 1 via an adhesive layer (not shown). The support 2 is made of glass or the like, and supports the semiconductor substrate 1 and protects a semiconductor element (for example, a semiconductor integrated circuit composed of a MOS transistor, a capacitor, etc.) formed on the surface of the semiconductor substrate 1. It is.

次に、半導体基板1の裏面上に露出させた金属層(例えばアルミニウム配線)上に導電材料(たとえばハンダペースト)をスクリーン印刷し、この導電材料を熱処理でリフローさせることで突起電極3を形成する。突起電極3は、半導体基板1に形成された多数の半導体素子と電気的に接続された外部接続用の電極である。突起電極3は、電解メッキ法やディスペンサを用いて導電材料を塗布するディスペンス法(塗布法)等で形成することも出来る。なお、突起電極3が形成された部分以外の半導体基板1の裏面はソルダーレジスト等から成る絶縁性の保護膜4で被覆されている。   Next, a conductive material (for example, solder paste) is screen-printed on a metal layer (for example, aluminum wiring) exposed on the back surface of the semiconductor substrate 1, and the protruding material 3 is formed by reflowing the conductive material by heat treatment. . The protruding electrode 3 is an external connection electrode electrically connected to a large number of semiconductor elements formed on the semiconductor substrate 1. The protruding electrode 3 can also be formed by an electrolytic plating method or a dispensing method (application method) in which a conductive material is applied using a dispenser. The back surface of the semiconductor substrate 1 other than the portion where the protruding electrodes 3 are formed is covered with an insulating protective film 4 made of a solder resist or the like.

1つの半導体チップ領域に対応する突起電極3の数は設計で予め決められており、本実施形態の設計では、図2Aに示すように4つの突起電極3が半導体チップの各コーナーに対応して配置される構成である。また、隣り合う突起電極3のピッチは例えば0.4mm〜0.65mm程度であり、その高さは例えば0.05mm〜0.2mm程度である。   The number of protruding electrodes 3 corresponding to one semiconductor chip region is determined in advance by design. In the design of this embodiment, four protruding electrodes 3 correspond to each corner of the semiconductor chip as shown in FIG. 2A. It is a configuration to be arranged. Further, the pitch of the adjacent protruding electrodes 3 is, for example, about 0.4 mm to 0.65 mm, and the height thereof is, for example, about 0.05 mm to 0.2 mm.

次に、図2A及び図2Bに示すように、半導体基板1の裏面上に柱状に突起した封止樹脂5を選択的に形成する。図2Aは、封止樹脂5が形成された状態を示す概略平面図であり、図2Bは図2AのX−X線に沿った断面図に対応するものである。   Next, as shown in FIGS. 2A and 2B, a sealing resin 5 protruding in a columnar shape is selectively formed on the back surface of the semiconductor substrate 1. 2A is a schematic plan view showing a state in which the sealing resin 5 is formed, and FIG. 2B corresponds to a cross-sectional view taken along line XX in FIG. 2A.

封止樹脂5について説明する。封止樹脂5は、後述する熱処理(第2の熱処理)によって半硬化状態からペースト状に状態変化(軟化)して、半導体チップ10と実装基板12との間の隙間に部分的に充填され、両者の接続強度を補強する役割を有するものである。   The sealing resin 5 will be described. The sealing resin 5 is changed in state (softened) from a semi-cured state to a paste state by a heat treatment (second heat treatment) to be described later, and is partially filled in a gap between the semiconductor chip 10 and the mounting substrate 12, It serves to reinforce the connection strength between the two.

次に封止樹脂5の特性について説明する。封止樹脂5は絶縁性であって、半導体基板1の裏面上に塗布した時点ではペースト状であって流動性を有するが(第1の状態)、第1の熱処理によって流動性が低下して半硬化状態(第2の状態)となり、第1の熱処理と異なる温度(本実施形態では、第1の熱処理よりも高い温度)の第2の熱処理によって再び流動性が増してペースト状になり(第3の状態)、その後第2の熱処理よりも高い温度の第3の熱処理及びその後の冷却を経ることによって完全に硬化するという特性を有する樹脂の材料からなる。なお、本実施形態で説明している半硬化状態は、「Bステージ」と呼ばれることもある。また、ここでいうペースト状とは粘性が約5000〜50000センチポアズ(cp)程度の状態をいい、半硬化状態とは粘性がほとんど無く、ペーストの状態と固体の状態の中間的な状態をいう。本発明者が検証する際に用いた封止樹脂5は、約120℃〜140℃での第1の熱処理で上記半硬化状態となり、約160℃〜170℃での第2の熱処理で再びペースト状(第3の状態)となり、約175℃以上の第3の熱処理及びその後の冷却処理で完全硬化する樹脂層である。   Next, the characteristics of the sealing resin 5 will be described. The sealing resin 5 is insulative and is pasty and fluid when applied to the back surface of the semiconductor substrate 1 (first state), but the fluidity is reduced by the first heat treatment. A semi-cured state (second state) is obtained, and the fluidity is increased again by the second heat treatment at a temperature different from the first heat treatment (in this embodiment, a temperature higher than the first heat treatment) to become a paste ( (Third state), and thereafter, it is made of a resin material having a characteristic of being completely cured through a third heat treatment at a temperature higher than that of the second heat treatment and subsequent cooling. Note that the semi-cured state described in the present embodiment may be referred to as a “B stage”. The pasty state here refers to a state with a viscosity of about 5000 to 50000 centipoise (cp), and the semi-cured state refers to an intermediate state between a paste state and a solid state with almost no viscosity. The encapsulating resin 5 used when the inventor conducted verification becomes the above-mentioned semi-cured state by the first heat treatment at about 120 ° C. to 140 ° C., and is pasted again by the second heat treatment at about 160 ° C. to 170 ° C. This is a resin layer that is in a state (third state) and is completely cured by the third heat treatment at about 175 ° C. or higher and the subsequent cooling treatment.

封止樹脂5は熱硬化性樹脂(例えばエポキシ樹脂やポリイミド樹脂)を含む材料が好適に用いられ、上記状態変化の特性を有するのであればその材料に限定はない。従って、複数の種類の樹脂層を混合したものでもよいし、種々の熱硬化剤や熱可塑剤が含まれていてもよい。なお、封止樹脂5に用いられる樹脂は、プリアプライド用封止樹脂と呼ばれることもある。   As the sealing resin 5, a material containing a thermosetting resin (for example, an epoxy resin or a polyimide resin) is preferably used, and the material is not limited as long as it has the above-described state change characteristics. Accordingly, a mixture of a plurality of types of resin layers may be used, and various thermosetting agents and thermoplastic agents may be included. Note that the resin used for the sealing resin 5 may be referred to as a pre-applied sealing resin.

封止樹脂5の形成は例えば以下のようにして行う。まず、所定の印刷用マスク及びスキージを用いたスクリーン印刷法やディスペンサを用いたディスペンサ法等によって、封止樹脂5のペースト状の材料を半導体基板1の中央領域であって突起電極3で囲まれた位置に選択的に塗布する。なお、封止樹脂5の半導体基板1からの高さは、突起電極3と同程度(例えば、0.05mm〜0.2mm程度)であることが好ましい。   For example, the sealing resin 5 is formed as follows. First, the paste-like material of the sealing resin 5 is surrounded by the protruding electrodes 3 in the central region of the semiconductor substrate 1 by a screen printing method using a predetermined printing mask and squeegee, a dispenser method using a dispenser, or the like. Selectively apply to the position. The height of the sealing resin 5 from the semiconductor substrate 1 is preferably about the same as that of the protruding electrode 3 (for example, about 0.05 mm to 0.2 mm).

次に、例えば120℃〜140℃程度の熱処理(第1の熱処理)を施し、当該ペースト状の材料を半硬化状態(第2の状態)にさせる。封止樹脂5は、本実施形態のように突起電極3で囲まれた位置に形成する等して、突起電極3の少なくとも外側6が封止樹脂5で被覆されずに露出されるようにする。換言すれば、突起電極3の側面の少なくとも一部が封止樹脂5で被覆されず、個々の半導体チップ領域の外周方向から露出されるようにする。なお、突起電極3の外側6が露出されるのであれば、封止樹脂5の平面的形状や数、形成位置に限定はない。   Next, for example, heat treatment (first heat treatment) at about 120 ° C. to 140 ° C. is performed to make the paste-like material in a semi-cured state (second state). The sealing resin 5 is formed at a position surrounded by the protruding electrodes 3 as in the present embodiment so that at least the outer side 6 of the protruding electrodes 3 is exposed without being covered with the sealing resin 5. . In other words, at least a part of the side surface of the protruding electrode 3 is not covered with the sealing resin 5 and is exposed from the outer peripheral direction of each semiconductor chip region. In addition, as long as the outer side 6 of the protruding electrode 3 is exposed, there is no limitation on the planar shape, number, and formation position of the sealing resin 5.

次に、所定のダイシングラインDLに沿って半導体基板1及び支持体2を切断し、チップ状の半導体チップ10に分割する。半導体チップ10に分割する方法としては、ダイシング法、エッチング法、レーザーカット法等がある。   Next, the semiconductor substrate 1 and the support 2 are cut along a predetermined dicing line DL and divided into chip-like semiconductor chips 10. As a method of dividing the semiconductor chip 10, there are a dicing method, an etching method, a laser cutting method, and the like.

次に、図3に示すように、アルミニウム等から成るパッド電極11が形成された実装基板12を準備する。実装基板12は半導体チップ10が搭載される基板であり、例えばガラス・エポキシ樹脂やフェノール樹脂等から成る。パッド電極11は、実装基板12上に形成された回路素子と電気的に接続された配線パターンの一部である。   Next, as shown in FIG. 3, a mounting substrate 12 on which a pad electrode 11 made of aluminum or the like is formed is prepared. The mounting substrate 12 is a substrate on which the semiconductor chip 10 is mounted, and is made of, for example, glass / epoxy resin or phenol resin. The pad electrode 11 is a part of a wiring pattern electrically connected to a circuit element formed on the mounting substrate 12.

次に、個片化された半導体チップ10を所定のボンディングツール(不図示)に吸着保持させた後、突起電極3とパッド電極11との位置合わせを行う。次に、突起電極3とパッド電極11とを接触させ、この状態でボンディングツールに圧力と熱を加える。そうすると、突起電極3あるいはパッド電極11が融解されて、突起電極3とパッド電極11とが接合される(第2の熱処理)。なお、突起電極3とパッド電極11の電気的接続及び接合強度を向上させるため、事前にハンダ材等の導電性接着剤を対応する突起電極3とパッド電極11との間に塗布しても良い。   Next, after the separated semiconductor chip 10 is sucked and held by a predetermined bonding tool (not shown), the protruding electrode 3 and the pad electrode 11 are aligned. Next, the protruding electrode 3 and the pad electrode 11 are brought into contact with each other, and pressure and heat are applied to the bonding tool in this state. Then, the protruding electrode 3 or the pad electrode 11 is melted, and the protruding electrode 3 and the pad electrode 11 are joined (second heat treatment). In order to improve the electrical connection and bonding strength between the protruding electrode 3 and the pad electrode 11, a conductive adhesive such as a solder material may be applied in advance between the corresponding protruding electrode 3 and the pad electrode 11. .

上記第2の熱処理の際、封止樹脂5は半硬化状態から軟化(溶解)してペースト状になり、半導体チップ10と実装基板12との間に充填され、半導体チップ10と実装基板12とがペースト状の封止樹脂5を介して接着される。ここでいう充填とは、半導体チップ10と実装基板12の間の一部が充填されるのであって、突起電極3あるいはパッド電極11の一部は封止樹脂5で被覆されずに実装基板12の外周方向から露出している。第2の熱処理の条件は、封止樹脂5の材料や特性に応じて変更されるものであり、例えば160℃〜170℃程度の条件で行う。   During the second heat treatment, the sealing resin 5 is softened (dissolved) from a semi-cured state to become a paste and is filled between the semiconductor chip 10 and the mounting substrate 12. Is bonded via the paste-like sealing resin 5. The term “filling” as used herein means that a part between the semiconductor chip 10 and the mounting substrate 12 is filled, and a part of the protruding electrode 3 or the pad electrode 11 is not covered with the sealing resin 5 and is mounted on the mounting substrate 12. It is exposed from the outer peripheral direction. The conditions for the second heat treatment are changed according to the material and characteristics of the sealing resin 5, and are performed under conditions of, for example, about 160 ° C to 170 ° C.

次に、温度を更に上げた(第3の熱処理、例えば175℃以上)後、冷却することによってペースト状の封止樹脂5を硬化させる。   Next, after further raising the temperature (third heat treatment, for example, 175 ° C. or higher), the paste-like sealing resin 5 is cured by cooling.

以上の工程により、実装基板12上に半導体チップ10が実装された半導体装置20が完成する。半導体装置20は、半導体チップ10と実装基板12との間に形成された完全硬化状態の封止樹脂5によって実装強度が補強されている。   Through the above steps, the semiconductor device 20 in which the semiconductor chip 10 is mounted on the mounting substrate 12 is completed. The mounting strength of the semiconductor device 20 is reinforced by the completely cured sealing resin 5 formed between the semiconductor chip 10 and the mounting substrate 12.

本実施形態では、個片化された半導体チップを得る以前の工程で、個々の半導体チップ領域に対して半硬化状態の柱状の封止樹脂5を一括形成している。そのため、半導体チップの実装工程の際に個別に封止樹脂を形成していた従来方法に比べて生産性を向上させるとともに、製造コストを抑えることが出来る。また、本発明の封止樹脂は半導体チップの一方の面上に選択的に形成されており、封止樹脂の材料を効率的に使用できるため、製造コストを抑えることができる。   In this embodiment, the column-shaped sealing resin 5 in a semi-cured state is collectively formed for each semiconductor chip region in a process before obtaining individual semiconductor chips. Therefore, productivity can be improved and manufacturing cost can be reduced as compared with the conventional method in which the sealing resin is individually formed in the mounting process of the semiconductor chip. Moreover, since the sealing resin of the present invention is selectively formed on one surface of the semiconductor chip and the material of the sealing resin can be used efficiently, the manufacturing cost can be suppressed.

また、図2A及び図2Bで示したように、個片化された半導体チップ10を得る時点で、突起電極3の外側6は封止樹脂5で被覆されておらず、半導体チップ10の外周方向から露出している。そのため、半導体チップ10が実装工程を経ても、従来構造(図5参照)のように突起電極101及びパッド電極105の全てが封止樹脂107で被覆されるのではなく、図3に示すように突起電極3とパッド電極11の接合部の側面が半導体装置20の外側から露出している。従って、後の信頼性検査により突起電極3とパッド電極11との接合部で電気的な接続不良(実装ズレ等)が発見された場合であっても、当該接合部に導電材料(例えばハンダ)を補充することができる。つまり、実装後に半導体チップを実施基板から取り外すことなくリペア作業を行うことでき、接続不良等の問題を容易に解消することができる。   2A and 2B, when the separated semiconductor chip 10 is obtained, the outer side 6 of the protruding electrode 3 is not covered with the sealing resin 5, and the outer peripheral direction of the semiconductor chip 10 is obtained. Is exposed from. Therefore, even if the semiconductor chip 10 undergoes a mounting process, the protruding electrode 101 and the pad electrode 105 are not all covered with the sealing resin 107 as in the conventional structure (see FIG. 5), but as shown in FIG. The side surface of the joint portion between the protruding electrode 3 and the pad electrode 11 is exposed from the outside of the semiconductor device 20. Therefore, even if a poor electrical connection (mounting misalignment, etc.) is found at the joint between the protruding electrode 3 and the pad electrode 11 by a subsequent reliability test, a conductive material (for example, solder) is present at the joint. Can be replenished. That is, repair work can be performed without removing the semiconductor chip from the implementation substrate after mounting, and problems such as poor connection can be easily solved.

以上説明したように、本実施形態によれば従来に比べて実装後のリペア作業が容易に行えるとともに、製造コストを抑えた半導体チップとその実装方法、及び当該半導体チップが実装された半導体装置を提供することができる。   As described above, according to the present embodiment, the repair work after mounting can be performed more easily than in the past, and the semiconductor chip and its mounting method with reduced manufacturing costs, and the semiconductor device mounted with the semiconductor chip are provided. Can be provided.

なお、本発明は上述した実施形態に限定されることはなく、その要旨を逸脱しない範囲で変更が可能なことは言うまでも無い。例えば、上述した実施形態で支持体2が半導体チップの一方の面に貼り合わされていたが、支持体2が貼り合わされていない半導体チップに対して本発明を適用することも出来る。また、突起電極3及び封止樹脂5の数や形状は、上述した実施形態に限定されない。従って、図4Aに示すように半導体基板1の一方の面上に3個の突起電極3と封止樹脂5が形成されていてもよいし、図4Bに示すように半導体基板1の一方の面上に平板状の突起電極3aと封止樹脂5aが形成されていてもよい。本発明は、半導体チップの一方の面上に突起電極が形成され、当該チップを実装基板に実装する技術として広く適用できるものである。   Needless to say, the present invention is not limited to the above-described embodiment, and can be changed without departing from the gist thereof. For example, although the support 2 is bonded to one surface of the semiconductor chip in the above-described embodiment, the present invention can be applied to a semiconductor chip to which the support 2 is not bonded. Further, the numbers and shapes of the protruding electrodes 3 and the sealing resin 5 are not limited to the above-described embodiments. Therefore, three protruding electrodes 3 and sealing resin 5 may be formed on one surface of the semiconductor substrate 1 as shown in FIG. 4A, or one surface of the semiconductor substrate 1 as shown in FIG. 4B. A flat projection electrode 3a and a sealing resin 5a may be formed thereon. The present invention is widely applicable as a technique in which a protruding electrode is formed on one surface of a semiconductor chip and the chip is mounted on a mounting substrate.

本発明の実施形態に係る半導体チップ及びその実装方法、半導体チップが実装された半導体装置を説明する断面図である。It is sectional drawing explaining the semiconductor device which mounted the semiconductor chip concerning the embodiment of the present invention, its mounting method, and a semiconductor chip. 本発明の実施形態に係る半導体チップ及びその実装方法、半導体チップが実装された半導体装置を説明する平面図及び断面図である。1A and 1B are a plan view and a cross-sectional view illustrating a semiconductor chip, a mounting method thereof, and a semiconductor device mounted with the semiconductor chip according to an embodiment of the present invention. 本発明の実施形態に係る半導体チップ及びその実装方法、半導体チップが実装された半導体装置を説明する断面図である。It is sectional drawing explaining the semiconductor device which mounted the semiconductor chip concerning the embodiment of the present invention, its mounting method, and a semiconductor chip. 本発明の変更例を示す平面図である。It is a top view which shows the example of a change of this invention. 従来の半導体チップの実装方法を説明する断面図である。It is sectional drawing explaining the mounting method of the conventional semiconductor chip.

符号の説明Explanation of symbols

1 半導体基板 2 支持体 3,3a 突起電極 4 保護膜
5,5a 封止樹脂 6 (突起電極の)外側 10 半導体チップ
11 パッド電極 12 実装基板 20 半導体装置 100 半導体基板
101 突起電極 102 支持体 103 半導体チップ 104 保護膜
105 パッド電極 106 実装基板 107 封止樹脂
DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Support body 3, 3a Protrusion electrode 4 Protective film 5, 5a Sealing resin 6 (Outside of protrusion electrode) 10 Semiconductor chip 11 Pad electrode 12 Mounting substrate 20 Semiconductor device 100 Semiconductor substrate 101 Protrusion electrode 102 Support body 103 Semiconductor Chip 104 Protective film 105 Pad electrode 106 Mounting substrate 107 Sealing resin

Claims (6)

半導体基板と、前記半導体基板の一方の面上に形成された複数の突起電極と、前記半導体基板の一方の面上に部分的に形成された封止樹脂とを備えた半導体チップを形成する工程と、
一方の面上に電極が形成された実装基板を準備し、
前記突起電極と前記電極とを電気的に接触させ、かつ前記封止樹脂を軟化させて前記半導体チップと前記実装基板とを前記封止樹脂を介して接着させる工程と、
その後前記封止樹脂を硬化させる工程とを有し、
前記半導体チップを形成する工程は、前記突起電極の外側が露出するように行うことを特徴とする半導体チップの実装方法。
Forming a semiconductor chip comprising: a semiconductor substrate; a plurality of protruding electrodes formed on one surface of the semiconductor substrate; and a sealing resin partially formed on the one surface of the semiconductor substrate. When,
Prepare a mounting board with electrodes on one side,
Electrically contacting the protruding electrode and the electrode, and softening the sealing resin to bond the semiconductor chip and the mounting substrate via the sealing resin;
And then curing the sealing resin,
The method of mounting a semiconductor chip, wherein the step of forming the semiconductor chip is performed such that the outside of the protruding electrode is exposed.
前記封止樹脂は、
前記半導体基板の一方の面上にペースト状の樹脂を形成する工程と、その後第1の熱処理を施して前記樹脂を半硬化させる工程を経て形成され、
前記半導体チップと前記実装基板とを前記封止樹脂を介して接着させる工程は、
前記第1の熱処理よりも高温の第2の熱処理を施して前記封止樹脂の流動性を増加させる工程を含み、
前記封止樹脂を硬化させる工程は、前記第2の熱処理よりも高温の第3の熱処理を施す工程を含むことを特徴とする請求項1に記載の半導体チップの実装方法。
The sealing resin is
Formed through a step of forming a paste-like resin on one surface of the semiconductor substrate, and then a step of semi-curing the resin by applying a first heat treatment;
The step of bonding the semiconductor chip and the mounting substrate through the sealing resin,
Including a step of increasing the fluidity of the sealing resin by performing a second heat treatment at a temperature higher than that of the first heat treatment,
The method for mounting a semiconductor chip according to claim 1, wherein the step of curing the sealing resin includes a step of performing a third heat treatment higher than the second heat treatment.
半導体基板と、
前記半導体基板の一方の面上に形成された複数の突起電極と、
前記半導体基板の一方の面上に部分的に形成された封止樹脂とを備え、
前記複数の突起電極の外側が露出しており、
前記封止樹脂は、第1の熱処理によって流動性が低下し、前記第1の熱処理よりも高温の第2の熱処理によって流動性が増加する特性を有することを特徴とする半導体チップ。
A semiconductor substrate;
A plurality of protruding electrodes formed on one surface of the semiconductor substrate;
A sealing resin partially formed on one surface of the semiconductor substrate,
The outside of the plurality of protruding electrodes is exposed,
The semiconductor chip is characterized in that the fluidity is lowered by the first heat treatment, and the fluidity is increased by the second heat treatment at a temperature higher than that of the first heat treatment.
前記封止樹脂は、その周囲が前記複数の突起電極で囲まれていることを特徴とする請求項3に記載の半導体チップ。 The semiconductor chip according to claim 3, wherein the sealing resin is surrounded by the plurality of protruding electrodes. 一方の面上に複数の突起電極を備えた半導体チップと、
一方の面上に電極を備え、前記電極が前記突起電極と電気的に接続された実装基板と、
前記半導体チップの一方の面と前記実装基板の一方の面との間の空間の一部に充填された封止樹脂とを備え、
前記突起電極または前記電極の少なくとも一部が、前記封止樹脂で被覆されずに外側から露出していることを特徴とする半導体装置。
A semiconductor chip having a plurality of protruding electrodes on one surface;
A mounting substrate comprising an electrode on one surface, wherein the electrode is electrically connected to the protruding electrode;
A sealing resin filled in a part of a space between one surface of the semiconductor chip and one surface of the mounting substrate;
The semiconductor device, wherein the protruding electrode or at least a part of the electrode is exposed from the outside without being covered with the sealing resin.
前記封止樹脂は、前記複数の突起電極で囲まれていることを特徴とする請求項5に記載の半導体装置。 The semiconductor device according to claim 5, wherein the sealing resin is surrounded by the plurality of protruding electrodes.
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