JP2008251846A - Method of manufacturing semiconductor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a high-quality semiconductor wherein an element isolation region can be formed stably, regardless of the intervals of patterns. <P>SOLUTION: An insulation film layer consists of a silicon nitride layer 203 and a silicon oxide film 204 which are formed immediately below an antireflection film 202 existing below a patterned resist 201. In etching the insulation film layer, etching is conducted at a treatment pressure of 0.5 to 1.5 Pa, using a mixed gas of HBr and CHF<SB>3</SB>which have a low selectivity of the silicon oxide film 204 relative to the silicon substrate 205, and CF<SB>4</SB>close to finishing of the etching, and etching is progressed, while making a reactive product 207 attach to the wall surface of the insulation film layer consisting of the silicon nitride film 203 and the silicon oxide film 204. Consequently, a trench having few variations in shape and a fully rounded top round can be formed, irrespective of the pattern intervals. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing method including a step of forming a trench using plasma. The present invention particularly relates to a method for manufacturing a semiconductor including a step of forming roundness (top round) at the upper end of a trench.

  Among the steps of manufacturing a semiconductor, there is a step of separating semiconductor elements from each other by an insulating film layer. In recent years, Shallow Trench Isolation (STI) has been widely used as an element isolation region on a semiconductor substrate in this process. In order to form this STI, it is necessary to etch the silicon substrate into a trench shape, bury an insulating film, and separate the semiconductor elements from each other by an insulating film layer.

  Depending on the trench shape and the method of embedding the insulating film, electric field concentration is considered to be caused by crystal defects and non-uniform thickness of the PAD oxide film at the upper and lower ends of the trench. As a solution, electric field concentration can be suppressed by rounding the upper and lower ends of the trench on the silicon substrate.

As a conventional technique, an example in which the upper end of a trench on a silicon substrate is rounded using HBr and CF ₄ as an etching gas in a state where a resist is used as a mask (see, for example, Patent Document 1) or on a silicon substrate using a resist as a mask. An example in which the upper end of a trench on a silicon substrate is rounded using an etching gas of C ₄ F ₈ and Ar after etching an insulating film layer composed of a silicon nitride film and a silicon oxide film (for example, Patent Documents) 2).

  In addition, a mechanism for etching a silicon nitride film to a predetermined thickness is proposed instead of switching to a high-pressure condition after completion of etching in an insulating film layer composed of a silicon nitride film and a silicon oxide film (patent) Reference 3).

As described above, the rounding of the upper end portion of the trench opening formed in the silicon substrate for forming the element isolation region has been frequently performed.
When rounding the upper end of the trench, after the etching of the insulating film layer that constitutes the upper layer of the silicon substrate is completed, the silicon substrate is formed by using a highly depositable gas in which a large amount of reaction products are formed and etching conditions with a high processing pressure. Etching was allowed to proceed while adhering a reaction product of an etching gas and a silicon substrate to the side surface of the opening to form a top round.
JP 2001-345375 A JP 2006-237182 A JP 2006-119145 A

With the recent miniaturization and high density of devices, the trench interval is narrowing in a dense portion (pattern dense portion) where adjacent patterns on a semiconductor substrate are arranged close to each other. Accordingly, an etching atmosphere between a dense portion (pattern dense portion) in which the adjacent patterns are arranged close to each other and a sparse portion (pattern sparse portion) in which the adjacent patterns are arranged apart from each other. Differences in the state begin to occur more than ever, and the atmosphere difference affects the trench shape on the silicon substrate and the round portion at the upper end. In particular, when a plasma treatment is performed under a high pressure etching condition of a CHF ₃ and CF ₄ mixed gas in order to form a round portion at the upper end of the trench, there is a difference in shape between the pattern dense portion and the sparse portion. It was difficult to achieve both compatibility.

  In order to address the above problems, the present invention performs etching through an insulating film composed of silicon nitride and silicon oxide through a patterned resist mask, and does not peel off the resist and the antireflection film. When the top round part is formed at the upper end of the trench on the silicon substrate using the subsequent insulating film layer as a mask, the shape difference of the top round part formed at the upper end of the trench between the pattern dense part and the pattern sparse part is determined. The purpose is to reduce.

  That is, an object of the present invention is to provide a dry etching method for manufacturing a high-quality semiconductor capable of forming a stable element isolation region regardless of the pattern interval, and to round the top end of the trench. In the semiconductor manufacturing method to be formed, the top-round shape difference between the dense pattern portion and the sparse pattern portion is reduced, and in particular, the crystal defects in the dense pattern and the film thickness non-uniformity of the insulating film embedded in the trench are improved. With the goal.

In order to solve the above-mentioned problems, the present invention provides etching for forming a top round portion at the upper end of a trench in a range of 0.5 to 1.5 Pa, not a high pressure condition of 2.0 Pa or more as in the prior art. Processing is performed under low pressure conditions. In order to form a reaction product with a silicon substrate in the present invention, a treatment with a low pressure condition requires a highly depositable gas that forms a large amount of a reaction product with a silicon substrate even at a low pressure. In addition, an HBr gas generally used in gate etching is added to a CHF ₃ and CF ₄ mixed gas to perform an etching process.

In addition, in the etching of the insulating film layer composed of the silicon nitride film and the silicon oxide film shown in Patent Document 3, the silicon nitride film is etched to a predetermined film thickness instead of switching to a high pressure condition after the etching is completed. The remaining silicon nitride film is etched using a mixed gas of CHF ₃ , CF ₄ and HBr and using a low pressure condition in the range of 0.5 to 1.5 Pa. .

According to the present invention, after etching a silicon nitride film and a silicon oxide film made of an insulating film using a patterned resist as a mask, or in the middle of etching the silicon nitride film, the HBr gas is changed to CHF ₃ and CF. _By using the mixed gas added to 4 as an etching gas with a CHF ₃ : CF ₄ : HBr ratio of 4 to 6: 1: 1, and etching under a low pressure condition in the range of 0.5 to 1.5 Pa, A predetermined top round shape can be formed. In addition, the top round shape can be maintained even if adjustment for reducing the shape difference between the pattern dense portion and the pattern sparse portion is performed.

  Thereby, the top-round shape difference between the dense pattern portion and the sparse pattern portion can be reduced, and in particular, the crystal defects in the dense portion pattern and the nonuniformity of the film thickness of the insulating film embedded in the trench can be improved.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining the configuration of a plasma generation unit of a plasma processing apparatus to which a semiconductor manufacturing method according to the present invention is applied. 2 and 3 are diagrams for explaining the processing steps of the semiconductor manufacturing method according to the present invention. FIG. 4 is a diagram for explaining the relationship between the amount of HBr added and the difference in the top round taper angle of the pattern dense part and the pattern sparse part of the trench part on the semiconductor substrate. FIG. 5 is a diagram for explaining the relationship between the processing pressure and the radius of the top round formed at the upper end of the trench portion.

  An outline of a plasma processing apparatus to which a semiconductor manufacturing method (dry etching method) according to the present invention is applied will be described with reference to FIG. As shown in FIG. 1, a plasma processing apparatus (etching apparatus) to which a semiconductor manufacturing method according to the present invention is applied is, for example, an apparatus that generates plasma using UHF waves and a magnetic field as means for generating plasma. The wafer 105 is placed on the antenna 101, the UHF transmission plate 102, the solenoid coil 103, and the processing table 107, and plasma 104 is generated between the wafer 105 and the UHF transmission plate 102. The UHF wave that has passed through the antenna 101 from the UHF power source, which is a plasma generation power source, and passed through the UHF transmission plate 102 and reached the processing chamber, acts on the magnetic field generated by the solenoid coil 103 disposed so as to surround the processing chamber. As a result, ECR (Electron Cyclotron Resonance) is generated with the process gas, and a high-density plasma 104 is generated in the processing chamber.

  The wafer 105 is electrostatically attracted to a processing stage 107 to which a DC voltage is applied by an electrostatic adsorption power source 108. A plasma generating gas is supplied into the processing chamber, plasma generating high frequency power is applied, and a magnetic field is formed from the solenoid coil 103 in the processing chamber to generate high-density plasma in the processing chamber. From 106, a high-frequency bias voltage is applied, and an acceleration potential is applied to the ions (wafer) direction side (downward) to ions localized in the high-density plasma, thereby starting the process.

  During the process, the pressure in the processing chamber can be regulated by an exhaust structure including a vacuum pump, a turbo molecular pump, and a variable valve provided between the turbo molecular pump.

  With reference to FIGS. 2 and 3, the wafer processing process when the semiconductor manufacturing method according to the present invention is applied to the etching apparatus shown in FIG. 1 will be described.

[Embodiment 1] FIG. 2A shows that a wafer 105 is composed of a resist 201, an antireflection film 202, a silicon nitride film 203, a silicon oxide film 204, and a silicon substrate 205 that are already patterned in order from the upper layer by an exposure technique. It is shown that.

After etching the antireflection film 202 with a Cl ₂ and O ₂ mixed gas using the patterned resist 201 as a mask using the above etching apparatus (FIG. 2 (b)), the silicon nitride film 203 is then replaced with SF ₆ , Etching was performed using a CHF ₃ and Ar mixed gas at a low processing pressure of 0.8 Pa (FIG. 2C).

Next, a top-round step based on a mixed gas of CHF ₃ , CF ₄ and HBr and a low pressure condition is performed, a low pressure of 0.5 to 1.5 Pa, and a gas flow rate ratio of CHF ₃ , CF ₄ and HBr of _{4 to} 6/1. As a result, the reaction product 207 was deposited on the side wall of the insulating film to form a top round (FIG. 2D).

Here, the above composition of the processing gas has the above composition in order to achieve a combination of maintaining the top round shape and reducing the shape difference between the sparse part and the dense part. That is, if CHF ₃ exceeds 6 and the amount increases excessively, the etching on the surface of the trench sidewall is hindered, and the top round shape of the sparse part and the dense part tends to be different. Conversely, if CHF ₃ is too small, less than 4, it will be difficult to form a top round. Therefore, the ratio of CHF ₃ : CF ₄ : HBr is set in the range of 4 to 6: 1: 1.

When the etching of the silicon chamber film 203 and the silicon oxide film 204 constituting the insulating layer on the silicon substrate 205 is completed (FIG. 2C), the opening of the trench 206 formed on the silicon substrate 205 is formed. When the pattern dense part and the pattern sparse part are compared, the etching amount of the silicon oxide film 204 is small in the pattern dense part, whereas the etching of the silicon oxide film 204 is almost completed in the pattern sparse part, The silicon substrate 205 is exposed. Here, when etching is performed under the above-mentioned mixed gas of CHF ₃ , CF ₄ and HBr and low pressure conditions, the etching proceeds simultaneously in the pattern sparse part where the silicon substrate 205 is exposed and the pattern dense part where the silicon oxide film 204 is localized. In addition, HBr having a high deposition property is deposited and silicon is not easily scraped. This is because CF ₄ and HBr are added to CHF ₃ and the etching speed of polycrystalline or amorphous silicon is increased with respect to the silicon oxide film by lowering the processing pressure (low selectivity). It is. Further, the top round angle and the round amount can be controlled by the gas flow rate ratio of CHF ₃ , CF ₄ and HBr and the etching time. In top-round etching using a gas obtained by adding CF ₄ and HBr to CHF ₃ , the silicon oxide film etching selection ratio with respect to polycrystalline silicon is preferably about 2.0 to 1.0.

The top-round shape can be obtained by controlling the gas composition and RF power and process pressure conditions. Alternatively, the silicon nitride film 203 is etched to a predetermined film thickness, and the remaining film thickness is etched using the mixed gas obtained by adding CF ₄ and HBr to the CHF _{3 under the} low pressure condition. Shape formation is possible.

[Embodiment 2] Using the same wafer (FIG. 3A) as shown in FIG. 2A, the antireflection film 202 is etched using the patterned resist 201 as a mask. Next, the silicon nitride film 203 is etched to a predetermined film thickness by using a mechanism for processing the silicon nitride film 203 to a predetermined film thickness with respect to the initial film thickness using SF ₆ , CHF ₃ and Ar mixed gas (FIG. 3B). )). In this case, the remaining film thickness of the silicon nitride film 203 is preferably about 20 nm.

Next, the remaining silicon nitride film 203 and the silicon oxide film 204 are mixed with CHF ₃ , CF _4, and HBr at a low pressure (1.0 Pa or less), and the mixed gas flow rate is obtained by adding CF ₄ and HBr to CHF _3. Processing is performed under etching conditions with a ratio of 4 to 6/1/1, and a top-round shape can be easily obtained (FIG. 3C). As the shape of the top round, a top round having a required top round taper angle 208 can be formed as in the enlarged view shown in the lower part of FIG. In the present invention, the slope at the bottom of the trench is referred to as a top round. In addition, by controlling the seed folding pressure in the range of 0.5 to 1.5 Pa, the top round shape can be maintained even when the shape difference between the sparse part and the dense part of the top round shape is adjusted. Is possible.

FIG. 4 is a result of measuring the relationship between the flow rate of HBr and the difference in density of the top round taper angle at the wafer center and the wafer edge when the CHF ₃ , CF ₄ and HBr mixed gas used in the present invention is used. is there. In FIG. 4, the vertical axis indicates the difference between the sparse part and the dense part by calculating the taper angle of the top round at the measurement points at the center and the outer peripheral part.
Here, the flow rates of CHF ₃ and CF ₄ were 100 mL / min and 20 mL / min, respectively. Compared with the mixed gas system of CHF ₃ and CF _4, the mixed gas system of CHF ₃ , CF _4, and HBr has a better result in the difference in density of the top round taper angle. That is, when there is no HBr, the taper angle difference at the sparse / dense portion in the center (Center) portion is about 23 degrees and the taper angle difference at the sparse / dense portion in the outer periphery (Edge) portion is about 17 degrees, while the HBr is 20 mL / min. As a result of addition, the taper angle difference at the sparse / dense portion at the center is about 12 degrees, and the taper angle difference at the sparse / dense portion at the outer periphery (Edge) is about 14 degrees, so the difference in density is reduced. Can be small.

Further, FIG. 5 shows the processing pressure and the top-round radius formed at the upper end of the trench when the mixed gas of CHF ₃ , CF ₄ and HBr used in the present invention and the mixed gas of CHF ₃ and CF ₄ are used. When a CHF ₃ and CF ₄ mixed gas is used, a sufficiently large top round shape cannot be obtained at the upper end of the trench at low to medium pressure (1.5 Pa or less). When a mixed gas of CHF ₃ , CF _4, and HBr is used, a sufficiently large top-round shape can be obtained even in a range from a low pressure of 0.5 Pa to an intermediate pressure of 1.5 Pa.

1 is a schematic view of a UHF plasma etching apparatus to which a semiconductor manufacturing method of the present invention is applied. Sectional drawing explaining the process of a semiconductor substrate by the semiconductor manufacturing method (Example 1) of this invention. Sectional drawing explaining the process of a semiconductor substrate by the semiconductor manufacturing method (Example 2) of this invention. The figure explaining the relationship between the amount of HBr addition and the top round taper angle difference of the pattern dense part of a trench part on a semiconductor substrate, and a pattern sparse part. The figure explaining the relationship between a process pressure and the radius of the top round formed in a trench part upper end.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 ... Antenna, 102 ... UHF transmission board, 103 ... Solenoid coil, 104 ... Plasma, 105 ... Processing wafer, 106 ... High frequency power supply, 107 ... Processing stand, 108 ... Electrostatic adsorption power supply, 201 ... Patterned resist, 202 DESCRIPTION OF SYMBOLS ... Antireflection film, 203 ... Silicon nitride film, 204 ... Silicon oxide film, 205 ... Silicon substrate, 206 ... Trench opening, 207 ... Reaction product, 208 ... Top round taper angle

Claims (3)

In a semiconductor manufacturing method including a step of etching a multilayer film composed of a resist and an insulating film layer on a silicon substrate by using a plasma etching apparatus to form a trench processing mask for forming a roundness at the upper end of the trench ,
A method for manufacturing a semiconductor, comprising performing an etching process on the insulating film layer and the silicon substrate using a mixed gas of CHF ₃ , CF _4, and HBr. The semiconductor manufacturing method according to claim 1,
A method for manufacturing a semiconductor, wherein a gas flow ratio of CHF ₃ , CF ₄ and HBr is 4 to 6: 1: 1, and a processing pressure is in a range of 0.5 to 1.5 Pa. The semiconductor manufacturing method according to claim 1,
The etching process is interrupted at a predetermined film thickness in the insulating film layer etching process, the gas flow ratio of CHF ₃ , CF ₄ and HBr is 4 to 6: 1: 1, and the processing pressure is 0.5 to 1.5 Pa. A method for producing a semiconductor, characterized in that the etching process is continued under the etching conditions in the range described above.

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